dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712). Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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320296a4cfe414ce59f406b8a5ce15272f563103 |
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08-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCTargetStreamer interface. This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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55d7d83b6c9e55fa73d667660c8e90f92999385b |
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01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use upper words of GR64s for codegen This just adds the basics necessary for allocating the upper words to virtual registers (move, load and store). The move support is parameterised in a way that makes it easy to handle zero extensions, but the associated zero-extend patterns are added by a later patch. The easiest way of testing this seemed to be add a new "h" register constraint for high words. I don't expect the constraint to be useful in real inline asms, but it should work, so I didn't try to hide it behind an option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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eb2f72f454048a1d179d1c75f5a953c7dfe43fc9 |
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30-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add GRH32 for the high word of a GR64 The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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514756983e9ba3684a89ed583bf5a98ffb20c203 |
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30-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Rename 32-bit GPR registers I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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c2b840cb7c58e59c68aaa589841c41fb272df66d |
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25-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add instruction-shortening pass When loading immediates into a GR32, the port prefered LHI, followed by LLILH or LLILL, followed by IILF. LHI and IILF are natural 32-bit operations, but LLILH and LLILL also clear the upper 32 bits of the register. This was represented as taking a 32-bit subreg of a 64-bit assignment. Using subregs for something as simple as a move immediate was probably a bad idea. Also, I have patches to add support for the high-word facility, and we don't want something like LLILH and LLILL to stop the high word of the same GPR from being used. This patch therefore uses LHI and IILF to begin with and adds a late machine-specific pass to use LLILH and LLILL if the other half of the register is not live. The high-word patches extend this behavior to IIHF, LLIHL and LLIHH. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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f917bc0406e47866eb1f6c0378de16498018b620 |
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14-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Match operands to fields by name rather than by order The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b |
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13-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the MachineMove class. It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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6e53180db120b30f600ac31611a9dd47ef7f4921 |
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10-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove unused argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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7a1ead46fb629839e5ce25574246ee743ab8b54f |
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07-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Fix InitMCCodeGenInfo call createSystemZMCCodeGenInfo was not passing the optimization level to InitMCCodeGenInfo(), so -O0 would be ignored. Fixes DebugInfo/namespace.ll after the changes in r181271. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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1d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07 |
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06-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[SystemZ] Add back end This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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29074ccf6cb00a3cbe32a3b7809d970ecaf8c9bf |
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25-Oct-2011 |
Dan Gohman <gohman@apple.com> |
Remove the SystemZ backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
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24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong. These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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7801136b95d1fbe515b9655b73ada39b05a33559 |
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23-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some refactoring so TargetRegistry.h no longer has to include any files from MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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7f8dff65717b1e4090ba4a648f9ec4f037a66c1e |
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23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
createXXXMCCodeGenInfo should be static. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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e78085a3c03de648a481e9751c3094c517bd7123 |
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22-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo, InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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34ad6db8b958fdc0d38e122edf753b5326e69b03 |
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20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo. - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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439661395fd2a2a832dba01c65bc88718528313c |
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19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Introduce MCCodeGenInfo, which keeps information that can affect codegen (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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0e6a052331f674dd70e28af41f654a7874405eab |
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18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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1abf2cb59b8d63415780a03329307c0997b2670c |
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15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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c60f9b752381baa6c4b80c0739034660f1748c84 |
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14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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