| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| 9b06dd6ca25fd1f8d2cf9227fdffc304c9f51564 |
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26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.
beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or $2, $3, $zero => move $2, $3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| 3209baefd4ab8242563118c37d8357bd9de6b421 |
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16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add branch macro definitions
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm
The corresponding test cases are added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| a2b9d3d8ba0e886971f953040a72e2b8e624f4dd |
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24-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add 64 bit testing for JAL
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| ef1762b6a1d3353790bdb415788e7d8963e70372 |
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14-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| 94fcfaf3a9f1179edb3b8053fe7b23eab6fb83bb |
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29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs
This patch provides alias definitions in td files and test cases to show the usage.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| d3107fbc54a5b5156f0aabc8788724f1469eb9df |
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22-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
Fix the invalid opcode for Mips branch instructions in the assembler
For mips a branch an 18-bit signed offset (the 16-bit
offset field shifted left 2 bits) is added to the
address of the instruction following the branch
(not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
Previously, the code generator did not perform the
shift of the immediate branch offset which resulted
in wrong instruction opcode. This patch fixes the issue.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| 0c66403efdf88ff4f247b6a9f45339bb3a893235 |
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07-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| 189225369446136f82e080dbdcab3a0fa63c71ac |
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22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| 04376ebe9f203213ef1eb4c69396fe280dc8c8b1 |
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07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler aliased instruction support.
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.
These changes are in the instruction td file.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
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| ad51a4a5984a365d671ddfe9eaa23d2e12ee4281 |
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06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific llvm assembler support for branch and jump instructions.
Test case included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-jump-instructions.s
|