/art/compiler/dex/ |
H A D | reg_storage.h | 279 static constexpr bool SameRegType(RegStorage reg1, RegStorage reg2) { argument 280 return ((reg1.reg_ & kShapeTypeMask) == (reg2.reg_ & kShapeTypeMask)); 283 static constexpr bool SameRegType(int reg1, int reg2) { argument 284 return ((reg1 & kShapeTypeMask) == (reg2 & kShapeTypeMask));
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/art/compiler/dex/quick/mips/ |
H A D | int_mips.cc | 238 RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, argument 240 NewLIR2(kMipsDiv, reg1.GetReg(), reg2.GetReg()); 250 RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, argument 254 NewLIR2(kMipsDiv, reg1.GetReg(), t_reg.GetReg());
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/art/compiler/utils/ |
H A D | assembler_test.h | 83 for (auto reg1 : registers) { 85 (assembler_.get()->*f)(*reg1, *reg2); 88 size_t reg1_index = base.find("{reg1}"); 91 sreg << *reg1; local
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/art/compiler/utils/arm/ |
H A D | assembler_arm.h | 736 static int RegisterCompare(const Register* reg1, const Register* reg2) { argument 737 return *reg1 - *reg2;
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/art/compiler/dex/quick/arm/ |
H A D | int_arm.cc | 695 RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { argument 703 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); 709 RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, argument 714 OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2); 717 // temp = reg1 / reg2 - integer division 719 // dest = reg1 - temp 722 OpRegRegReg(kOpDiv, temp, reg1, reg2); 724 OpRegRegReg(kOpSub, rl_result.reg, reg1, temp);
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/art/compiler/dex/quick/arm64/ |
H A D | int_arm64.cc | 597 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { argument 605 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); 1388 * int reg1 = -1, reg2 = -1; 1390 * reg_mask = GenPairWise(reg_mask, & reg1, & reg2); 1392 * // Single register in reg1. 1394 * // Pair in reg1, reg2. 1399 static uint32_t GenPairWise(uint32_t reg_mask, int* reg1, int* reg2) { argument 1402 int reg = *reg1 + first_bit_set; 1410 *reg1 = reg + second_bit_set; 1415 *reg1 1421 int reg1 = -1, reg2 = -1; local 1437 int reg1 = -1, reg2 = -1; local 1487 int reg1 = -1, reg2 = -1; local 1605 int reg1 = -1, reg2 = -1; local 1621 int reg1 = -1, reg2 = -1; local [all...] |
/art/compiler/dex/quick/x86/ |
H A D | int_x86.cc | 905 void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { argument 906 NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset);
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/art/compiler/utils/x86/ |
H A D | assembler_x86.cc | 761 void X86Assembler::cmpl(Register reg0, Register reg1) { argument 764 EmitOperand(reg0, Operand(reg1)); 802 void X86Assembler::testl(Register reg1, Register reg2) { argument 805 EmitRegisterOperand(reg1, reg2);
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/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.cc | 848 void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) { argument 850 EmitOptionalRex32(reg0, reg1); 852 EmitOperand(reg0.LowBits(), Operand(reg1)); 864 void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) { argument 866 EmitRex64(reg0, reg1); 868 EmitOperand(reg0.LowBits(), Operand(reg1)); 919 void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) { argument 921 EmitOptionalRex32(reg1, reg2); 923 EmitRegisterOperand(reg1.LowBits(), reg2.LowBits());
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/art/compiler/dex/quick/ |
H A D | mir_to_lir.h | 1163 bool IsSameReg(RegStorage reg1, RegStorage reg2) { argument 1164 RegisterInfo* info1 = GetRegInfo(reg1);
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