Searched refs:opcode (Results 51 - 71 of 71) sorted by relevance

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/art/compiler/dex/quick/mips/
H A Dint_mips.cc395 void MipsMir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, argument
417 void MipsMir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, argument
439 void MipsMir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, argument
441 switch (opcode) {
444 GenAddLong(opcode, rl_dest, rl_src1, rl_src2);
448 GenSubLong(opcode, rl_dest, rl_src1, rl_src2);
459 Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
630 void MipsMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, argument
633 GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
636 void MipsMir2Lir::GenArithImmOpLong(Instruction::Code opcode, argument
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H A Dmips_lir.h494 // Struct used to define the snippet positions for each MIPS opcode.
502 MipsOpCode opcode; member in struct:art::MipsEncodingMap
/art/compiler/utils/arm/
H A Dassembler_thumb2.h324 Opcode opcode,
333 Opcode opcode,
341 Opcode opcode,
349 Opcode opcode,
356 Opcode opcode,
384 int32_t opcode,
391 int32_t opcode,
397 int32_t opcode,
403 int32_t opcode,
408 int32_t opcode,
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H A Dassembler_arm32.h288 Opcode opcode,
314 Shift opcode,
320 Shift opcode,
326 int32_t opcode,
333 int32_t opcode,
339 int32_t opcode,
345 int32_t opcode,
350 int32_t opcode,
H A Dassembler_arm32.cc516 Opcode opcode,
525 static_cast<int32_t>(opcode) << kOpcodeShift |
616 Shift opcode,
626 static_cast<int32_t>(opcode) << kShiftShift |
633 Shift opcode,
643 static_cast<int32_t>(opcode) << kShiftShift |
694 void Arm32Assembler::EmitMulOp(Condition cond, int32_t opcode, argument
702 int32_t encoding = opcode |
976 void Arm32Assembler::EmitVFPsss(Condition cond, int32_t opcode, argument
983 B27 | B26 | B25 | B11 | B9 | opcode |
514 EmitType01(Condition cond, int type, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument
615 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
632 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
994 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument
1012 EmitVFPsd(Condition cond, int32_t opcode, SRegister sd, DRegister dm) argument
1027 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument
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H A Dassembler_arm.cc155 bool ShifterOperand::CanHoldThumb(Register rd, Register rn, Opcode opcode,
161 switch (opcode) {
H A Dassembler_arm.h128 static bool CanHoldThumb(Register rd, Register rn, Opcode opcode,
/art/compiler/dex/quick/arm/
H A Dint_arm.cc379 bool skip = ((target != NULL) && (target->opcode == kPseudoThrowTarget));
403 int opcode; local
414 opcode = kThumbMovRR;
416 opcode = kThumbMovRR_H2H;
418 opcode = kThumbMovRR_H2L;
420 opcode = kThumbMovRR_L2H;
421 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
664 LOG(FATAL) << "Unexpected opcode passed to GenEasyMultiplyTwoOps";
1131 || (barrier != nullptr && (barrier->opcode != kThumb2Dmb || barrier->operands[0] != dmb_flavor))) {
1165 void ArmMir2Lir::GenMulLong(Instruction::Code opcode, RegLocatio argument
1271 GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument
1471 GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) argument
1544 GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument
[all...]
H A Darm_lir.h577 // Struct used to define the snippet positions for each Thumb opcode.
585 ArmOpcode opcode; member in struct:art::ArmEncodingMap
/art/compiler/dex/quick/
H A Dcodegen_util.cc132 DCHECK(GetTargetInstFlags(lir->opcode) & (IS_LOAD | IS_STORE));
159 DCHECK(!(GetTargetInstFlags(lir->opcode) & IS_STORE));
195 switch (lir->opcode) {
256 std::string op_name(BuildInsnString(GetTargetInstName(lir->opcode),
258 std::string op_operands(BuildInsnString(GetTargetInstFmt(lir->opcode),
307 if (!lir->flags.is_nop && !IsPseudoLirOp(lir->opcode)) {
309 } else if (lir->opcode == kPseudoPseudoAlign4) {
666 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoSafepointPC)) {
675 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode == kPseudoExportedPC)) {
701 if (!tgt_lir->flags.is_nop && (tgt_lir->opcode
934 EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) argument
[all...]
H A Dgen_common.cc218 void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, argument
224 switch (opcode) {
245 LOG(FATAL) << "Unexpected opcode " << opcode;
263 InexpensiveConstantInt(constant_value, opcode)) {
284 void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, argument
289 switch (opcode) {
310 LOG(FATAL) << "Unexpected opcode " << opcode;
326 void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocatio argument
1394 GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift) argument
1421 GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument
1681 GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, int lit) argument
1832 GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) argument
[all...]
/art/compiler/dex/portable/
H A Dmir_to_gbc.cc708 Instruction::Code opcode = mir->dalvikInsn.opcode; local
709 int op_val = opcode;
716 LOG(INFO) << ".. " << Instruction::Name(opcode) << " 0x" << std::hex << op_val;
725 uint64_t attrs = MirGraph::GetDataFlowAttributes(opcode);
760 switch (opcode) {
1516 UNIMPLEMENTED(FATAL) << "Unsupported Dex opcode 0x" << std::hex << opcode; local
1552 int opcode = mir->dalvikInsn.opcode; local
1725 int opcode = mir->dalvikInsn.opcode; local
[all...]
/art/compiler/utils/mips/
H A Dassembler_mips.h271 void EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);
272 void EmitI(int opcode, Register rs, Register rt, uint16_t imm);
273 void EmitJ(int opcode, int address);
274 void EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, int funct);
275 void EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm);
H A Dassembler_mips.cc41 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument
45 int32_t encoding = opcode << kOpcodeShift |
54 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument
57 int32_t encoding = opcode << kOpcodeShift |
64 void MipsAssembler::EmitJ(int opcode, int address) { argument
65 int32_t encoding = opcode << kOpcodeShift |
70 void MipsAssembler::EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, int funct) { argument
74 int32_t encoding = opcode << kOpcodeShift |
83 void MipsAssembler::EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm) { argument
85 int32_t encoding = opcode << kOpcodeShif
[all...]
/art/compiler/dex/
H A Dmir_dataflow.cc26 * instructions, where extended opcode at the MIR level are appended
915 switch (static_cast<int>(d_insn.opcode)) {
917 LOG(ERROR) << "Unexpected Extended Opcode " << d_insn.opcode;
1065 switch (static_cast<int>(mir->dalvikInsn.opcode)) {
1067 LOG(ERROR) << "Missing case for extended MIR: " << mir->dalvikInsn.opcode;
1087 if (!MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) {
1088 int flags = Instruction::FlagsOf(mir->dalvikInsn.opcode);
1270 Instruction::Code opcode = mir->dalvikInsn.opcode; local
1271 switch (opcode) {
[all...]
H A Dssa_transformation.cc534 phi->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpPhi);
550 if (mir->dalvikInsn.opcode != static_cast<Instruction::Code>(kMirOpPhi))
/art/compiler/dex/quick/arm64/
H A Darm64_lir.h370 * WIDE macro to the non-wide opcode. E.g. WIDE(kA64Sub4RRdT).
373 // Return the wide and no-wide variants of the given opcode.
377 // Whether the given opcode is wide.
422 // Struct used to define the snippet positions for each A64 opcode.
431 ArmOpcode opcode; // can be WIDE()-ned to indicate it has a wide variant. member in struct:art::ArmEncodingMap
453 uint32_t opcode; // can be WIDE()-ned to indicate it has a wide variant.
/art/runtime/
H A Ddex_file.cc817 uint8_t opcode = *stream++; local
823 switch (opcode) {
846 if (opcode == DBG_START_LOCAL_EXTENDED) {
856 if (opcode == DBG_START_LOCAL_EXTENDED) {
907 int adjopcode = opcode - DBG_FIRST_SPECIAL;
H A Ddex_file_verifier.cc918 uint8_t opcode = *(ptr_++); local
919 switch (opcode) {
934 ErrorStringPrintf("Bad reg_num for opcode %x", opcode);
957 ErrorStringPrintf("Bad reg_num for opcode %x", opcode);
965 ErrorStringPrintf("Bad reg_num for opcode %x", opcode);
/art/runtime/verifier/
H A Dmethod_verifier.cc563 Instruction::Code opcode = inst->Opcode(); local
564 switch (opcode) {
771 Fail(VERIFY_ERROR_BAD_CLASS_HARD) << "unexpected opcode " << inst->Name();
776 Fail(VERIFY_ERROR_BAD_CLASS_HARD) << "opcode only expected at runtime " << inst->Name();
1462 * The behavior can be determined from the opcode flags.
2723 Fail(VERIFY_ERROR_BAD_CLASS_HARD) << "Unexpected opcode " << inst->DumpString(dex_file_);
2730 } // end - switch (dec_insn.opcode)
2738 info_messages_ << "Rejecting opcode " << inst->DumpString(dex_file_);
2911 Instruction::Code opcode = ret_inst->Opcode(); local
2912 if ((opcode
4044 Instruction::Code opcode = ret_inst->Opcode(); local
[all...]
/art/runtime/interpreter/
H A Dinterpreter_goto_table_impl.cc64 #define HANDLE_INSTRUCTION_START(opcode) op_##opcode: // NOLINT(whitespace/labels)

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