Searched refs:addq (Results 1 - 6 of 6) sorted by relevance

/art/runtime/arch/x86_64/
H A Dquick_entrypoints_x86_64.S35 addq MACRO_LITERAL(4 * 8), %rsp
130 addq LITERAL(8 + 4*8), %rsp
209 addq MACRO_LITERAL(80 + 4 * 8), %rsp
365 addq MACRO_LITERAL(1), %r10 // shorty++
372 addq MACRO_LITERAL(4), %r11 // arg_array++
376 addq MACRO_LITERAL(4), %r11 // arg_array++
380 addq MACRO_LITERAL(8), %r11 // arg_array+=2
384 addq MACRO_LITERAL(4), %r11 // arg_array++
396 addq MACRO_LITERAL(1), %r10 // shorty++
406 addq MACRO_LITERA
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H A Djni_entrypoints_x86_64.S63 addq LITERAL(72 + 4 * 8), %rsp
/art/compiler/utils/x86_64/
H A Dassembler_x86_64_test.cc102 DriverStr(RepeatRR(&x86_64::X86_64Assembler::addq, "addq %{reg2}, %{reg1}"), "addq");
106 DriverStr(RepeatRI(&x86_64::X86_64Assembler::addq, 4U, "addq ${imm}, %{reg}"), "addqi");
296 str << "addq $" << displacement << ", %rsp\n";
316 str << "addq $0, %rsp\n";
317 str << "addq $-" << kStackAlignment << ", %rsp\n";
318 str << "addq $-" << 10 * kStackAlignment << ", %rsp\n";
334 str << "addq
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H A Dassembler_x86_64.cc1082 void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) { function in class:art::x86_64::X86_64Assembler
1084 CHECK(imm.is_int32()); // addq only supports 32b immediate.
1090 void X86_64Assembler::addq(CpuRegister dst, const Address& address) { function in class:art::x86_64::X86_64Assembler
1098 void X86_64Assembler::addq(CpuRegister dst, CpuRegister src) { function in class:art::x86_64::X86_64Assembler
1100 // 0x01 is addq r/m64 <- r/m64 + r64, with op1 in r/m and op2 in reg: so reverse EmitRex64
1462 addq(CpuRegister(RSP), Immediate(2 * kWordSize));
1786 addq(CpuRegister(RSP), Immediate(static_cast<int64_t>(frame_size) - (gpr_count * kFramePointerSize) - kFramePointerSize));
1798 addq(CpuRegister(RSP), Immediate(-static_cast<int64_t>(adjust)));
1803 addq(CpuRegister(RSP), Immediate(adjust));
2003 addq(CpuRegiste
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H A Dassembler_x86_64.h413 void addq(CpuRegister reg, const Immediate& imm);
414 void addq(CpuRegister dst, CpuRegister src);
415 void addq(CpuRegister dst, const Address& address);
/art/compiler/optimizing/
H A Dcode_generator_x86_64.cc88 __ addq(CpuRegister(RSP),
236 __ addq(CpuRegister(RSP),
797 __ addq(locations->InAt(0).AsX86_64().AsCpuRegister(),

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