| /art/compiler/dex/quick/arm64/ |
| H A D | target_arm64.cc | 235 static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { argument
236 if ((operand & (1 << 6)) == 0) {
237 const char *shift_name = shift_names[(operand >> 7) & 0x3];
238 int amount = operand & 0x3f;
241 const char *extend_name = extend_names[(operand >> 3) & 0x7];
242 int amount = operand & 0x7;
342 int operand; local
352 operand = lir->operands[nc-'0'];
359 if (LIKELY(operand == omittable)) {
362 DecodeRegExtendOrShift(operand, tbu
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| H A D | assemble_arm64.cc | 66 * of the key, "p" is which numeric operand to use and "f" is the
91 * H -> operand shift
670 uint32_t operand = lir->operands[i]; local
677 bool is_zero = A64_REG_IS_ZR(operand);
726 RegStorage reg(operand | RegStorage::kValid);
751 << ". Expected " << expected << ", got 0x" << std::hex << operand;
754 << ". Expected " << expected << ", got 0x" << std::hex << operand;
759 // In the lines below, we rely on (operand & 0x1f) == 31 to be true for register sp
767 value = (operand << encoder->field_loc[i].start) &
780 DCHECK_EQ((operand
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| /art/compiler/dex/quick/arm/ |
| H A D | target_arm.cc | 361 int operand; local
371 operand = lir->operands[nc-'0'];
374 if (operand != 0) {
375 snprintf(tbuf, arraysize(tbuf), ", %s %d", shift_names[operand & 0x3], operand >> 2);
381 switch (operand) {
409 tbuf[i] += operand & 1;
410 operand >>= 1;
414 operand = ~ExpandImmediate(operand);
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| H A D | assemble_arm.cc | 45 * of the key, "p" is which numeric operand to use and "f" is the
71 * H -> operand shift
1087 uint32_t operand; local
1089 operand = lir->operands[i];
1092 value = (operand << encoder->field_loc[i].start) &
1103 value = ((operand & 0xF0) >> 4) << encoder->field_loc[i].end;
1104 value |= (operand & 0x0F) << encoder->field_loc[i].start;
1108 value = ((operand & 0x80000) >> 19) << 26;
1109 value |= ((operand & 0x40000) >> 18) << 11;
1110 value |= ((operand
1140 DCHECK(RegStorage::IsDouble(operand)) << ", Operand = 0x" << std::hex << operand; local
1150 DCHECK(RegStorage::IsSingle(operand)) << ", Operand = 0x" << std::hex << operand; local
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| /art/compiler/dex/quick/mips/ |
| H A D | target_mips.cc | 201 int operand; local
211 operand = lir->operands[nc-'0'];
216 tbuf[i] += operand & 1;
217 operand >>= 1;
221 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand));
224 DCHECK_EQ(RegStorage::RegNum(operand) & 1, 0);
225 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand));
228 snprintf(tbuf, arraysize(tbuf), "%04x", operand);
232 snprintf(tbuf, arraysize(tbuf), "%d", operand);
235 snprintf(tbuf, arraysize(tbuf), "%d", operand
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| H A D | assemble_mips.cc | 47 * of the key, "p" is which numeric operand to use and "f" is the
654 uint32_t operand; local
656 operand = lir->operands[i];
662 value = operand;
664 value = (operand << encoder->field_loc[i].start) &
670 value = (operand & 0x1f);
676 DCHECK(RegStorage::IsDouble(operand)) << ", Operand = 0x" << std::hex << operand; local
677 DCHECK_EQ((operand & 0x1), 0U);
678 value = (RegStorage::RegNum(operand) << encode
684 DCHECK(RegStorage::IsSingle(operand)) << ", Operand = 0x" << std::hex << operand; local
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| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64.h | 151 // Get the operand encoding byte at the given index.
440 void shll(CpuRegister operand, CpuRegister shifter);
442 void shrl(CpuRegister operand, CpuRegister shifter);
444 void sarl(CpuRegister operand, CpuRegister shifter);
626 void EmitOperand(uint8_t rm, const Operand& operand);
628 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate);
634 void EmitGenericShift(int rm, CpuRegister operand, CpuRegister shifter);
645 void EmitOptionalRex32(const Operand& operand);
646 void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
647 void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
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| H A D | assembler_x86_64.cc | 1025 // W - 64-bit operand
1052 // W - 64-bit operand
1248 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { argument
1249 EmitGenericShift(4, operand, shifter);
1263 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) { argument
1264 EmitGenericShift(5, operand, shifter);
1273 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) { argument
1274 EmitGenericShift(7, operand, shifter);
1520 void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) { argument
1523 const int length = operand
1544 EmitComplex(uint8_t reg_or_opcode, const Operand& operand, const Immediate& immediate) argument
1605 EmitGenericShift(int reg_or_opcode, CpuRegister operand, CpuRegister shifter) argument
1658 EmitOptionalRex32(const Operand& operand) argument
1665 EmitOptionalRex32(CpuRegister dst, const Operand& operand) argument
1675 EmitOptionalRex32(XmmRegister dst, const Operand& operand) argument
1693 EmitRex64(CpuRegister dst, const Operand& operand) argument
1707 EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) argument
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| /art/compiler/utils/x86/ |
| H A D | assembler_x86.cc | 1053 void X86Assembler::shll(Register operand, Register shifter) { argument
1054 EmitGenericShift(4, operand, shifter);
1063 void X86Assembler::shrl(Register operand, Register shifter) { argument
1064 EmitGenericShift(5, operand, shifter);
1073 void X86Assembler::sarl(Register operand, Register shifter) { argument
1074 EmitGenericShift(7, operand, shifter);
1324 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) { argument
1327 const int length = operand.length_;
1330 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
1331 EmitUint8(operand
1344 EmitComplex(int reg_or_opcode, const Operand& operand, const Immediate& immediate) argument
1401 EmitGenericShift(int reg_or_opcode, Register operand, Register shifter) argument
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| H A D | assembler_x86.h | 123 // Get the operand encoding byte at the given index.
400 void shll(Register operand, Register shifter);
402 void shrl(Register operand, Register shifter);
404 void sarl(Register operand, Register shifter);
582 void EmitOperand(int rm, const Operand& operand);
584 void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
590 void EmitGenericShift(int rm, Register operand, Register shifter);
|
| /art/compiler/dex/quick/x86/ |
| H A D | target_x86.cc | 352 int operand = lir->operands[operand_number]; local
355 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName));
356 buf += x86CondName[operand];
359 buf += StringPrintf("%d", operand);
362 int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 |
367 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand));
372 if (RegStorage::IsFloat(operand)) {
373 int fp_reg = RegStorage::RegNum(operand);
376 int reg_num = RegStorage::RegNum(operand);
383 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand,
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| /art/compiler/optimizing/ |
| H A D | code_generator_arm.cc | 578 ShifterOperand operand; local
579 if (ShifterOperand::CanHoldArm(value, &operand)) {
617 ShifterOperand operand; local
618 if (ShifterOperand::CanHoldArm(value, &operand)) {
|