Searched refs:subq (Results 1 - 6 of 6) sorted by relevance

/art/runtime/arch/x86_64/
H A Djni_entrypoints_x86_64.S31 subq LITERAL(72 + 4 * 8), %rsp
H A Dquick_entrypoints_x86_64.S21 subq MACRO_LITERAL(4 * 8), %rsp
61 subq LITERAL(4 * 8), %rsp
68 subq MACRO_LITERAL(8), %rsp // Space for Method* (also aligns the frame).
104 subq LITERAL(8 + 4*8), %rsp
166 subq MACRO_LITERAL(80 + 4 * 8), %rsp
461 subq %rdx, %rsp // Reserve stack space for argument array.
545 subq %rdx, %rsp // Reserve stack space for argument array.
1013 subq LITERAL(8), %rsp // Alignment padding.
1123 subq LITERAL(80 + 4*8), %rsp
1271 subq LITERA
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/art/compiler/utils/x86_64/
H A Dassembler_x86_64_test.cc111 DriverStr(RepeatRR(&x86_64::X86_64Assembler::subq, "subq %{reg2}, %{reg1}"), "subq");
115 DriverStr(RepeatRI(&x86_64::X86_64Assembler::subq, 4U, "subq ${imm}, %{reg}"), "subqi");
266 str << "subq $" << displacement << ", %rsp\n";
H A Dassembler_x86_64.h421 void subq(CpuRegister reg, const Immediate& imm);
422 void subq(CpuRegister dst, CpuRegister src);
423 void subq(CpuRegister dst, const Address& address);
H A Dassembler_x86_64.cc1137 void X86_64Assembler::subq(CpuRegister reg, const Immediate& imm) { function in class:art::x86_64::X86_64Assembler
1139 CHECK(imm.is_int32()); // subq only supports 32b immediate.
1145 void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) { function in class:art::x86_64::X86_64Assembler
1153 void X86_64Assembler::subq(CpuRegister reg, const Address& address) { function in class:art::x86_64::X86_64Assembler
1735 subq(CpuRegister(RSP), Immediate(rest_of_frame));
/art/compiler/optimizing/
H A Dcode_generator_x86_64.cc212 __ subq(CpuRegister(RSP),
863 __ subq(locations->InAt(0).AsX86_64().AsCpuRegister(),

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