| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 257 case ISD::ADDE: {
260 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
265 if (Opcode == ISD::ADDE) {
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| H A D | MipsSEISelDAGToDAG.cpp | 237 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
650 case ISD::ADDE: {
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| H A D | MipsSEISelLowering.cpp | 142 setTargetDAGCombine(ISD::ADDE);
1069 case ISD::ADDE:
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 209 ADDE, SUBE, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 1036 case ISD::ADDE: return true;
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| /external/pcre/dist/sljit/ |
| H A D | sljitNativePPC_32.c | 124 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)));
127 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2));
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| H A D | sljitNativePPC_64.c | 245 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)));
249 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2));
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| H A D | sljitNativePPC_common.c | 134 #define ADDE (HI(31) | LO(138)) macro
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand);
213 setOperationAction(ISD::ADDE, MVT::Other, Expand);
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 113 setOperationAction(ISD::ADDE, VT, Expand);
213 setOperationAction(ISD::ADDE, MVT::Other, Expand);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 206 case ISD::ADDE: return "adde";
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| H A D | LegalizeIntegerTypes.cpp | 1203 case ISD::ADDE:
1350 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1586 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1588 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1601 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1650 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
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| H A D | SelectionDAG.cpp | 2257 case ISD::ADDE: {
2273 // With ADDE, a carry bit may be added in, so we can only use this
2277 if (KnownZeroOut >= 2) // ADDE
3472 case ISD::ADDE:
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 78 ADDE, // Add using carry enumerator in enum:llvm::ARMISD::NodeType
|
| H A D | ARMISelLowering.cpp | 631 setOperationAction(ISD::ADDE, MVT::i32, Custom);
970 case ARMISD::ADDE: return "ARMISD::ADDE";
6065 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6244 case ISD::ADDE:
7802 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7810 // ADDE
7835 // Look for the glued ADDE.
7840 // Make sure it is really an ADDE
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1385 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1386 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1387 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1388 setOperationAction(ISD::ADDE, MVT::i64, Expand);
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1459 setOperationAction(ISD::ADDE, MVT::i64, Custom);
2692 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2693 case ISD::ADDE: hasChain = true; break;
2826 case ISD::ADDE:
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 222 setOperationAction(ISD::ADDE, MVT::i32, Custom);
226 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1285 case ISD::ADDE:
1547 case ISD::ADDE:
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| /external/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 79 setOperationAction(ISD::ADDE, MVT::i32, Legal);
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| H A D | AMDGPUISelLowering.cpp | 314 setOperationAction(ISD::ADDE, VT, Expand);
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| H A D | R600ISelLowering.cpp | 177 setOperationAction(ISD::ADDE, VT, Expand);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 96 setOperationAction(ISD::ADDE, MVT::i32, Expand);
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 223 setOperationAction(ISD::ADDE, MVT::i64, Expand);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 327 case ISD::ADDE:
|
| H A D | X86ISelLowering.cpp | 444 setOperationAction(ISD::ADDE, VT, Custom);
16102 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16246 case ISD::ADDE:
16290 case ISD::ADDE:
|