| /external/llvm/lib/CodeGen/ |
| H A D | ScheduleDAG.cpp | 72 if (!Required && I->getSUnit() == D.getSUnit())
77 SUnit *PredSU = I->getSUnit();
96 SUnit *N = D.getSUnit();
142 SUnit *N = D.getSUnit();
188 SUnit *SuccSU = I->getSUnit();
204 SUnit *PredSU = I->getSUnit();
245 SUnit *PredSU = I->getSUnit();
278 SUnit *SuccSU = I->getSUnit();
304 unsigned MaxDepth = BestI->getSUnit()
[all...] |
| H A D | LatencyPriorityQueue.cpp | 60 SUnit &Pred = *I->getSUnit();
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
95 AdjustPriorityOfUnscheduledPreds(I->getSUnit());
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| H A D | ScheduleDAGInstrs.cpp | 438 SUnit *DefSU = getSUnit(Def);
613 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
644 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
1286 unsigned PredNum = PI->getSUnit()->NodeNum;
1314 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1320 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1370 const SUnit *PredSU = PredDep.getSUnit();
1444 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1473 || PredDep.getSUnit()->isBoundaryNode()) {
1477 if (Impl.isVisited(PredDep.getSUnit())) {
[all...] |
| H A D | AggressiveAntiDepBreaker.cpp | 283 const SUnit *PredSU = P->getSUnit();
296 return (Next) ? Next->getSUnit() : nullptr;
806 SUnit *NextSU = Edge->getSUnit();
850 if (P->getSUnit() == NextSU ?
859 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
864 } else if ((P->getSUnit() != NextSU) &&
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| H A D | MachineScheduler.cpp | 507 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
509 Topo.AddPred(SuccSU, PredDep.getSUnit());
521 SUnit *SuccSU = SuccEdge->getSUnit();
560 SUnit *PredSU = PredEdge->getSUnit();
808 if (SUnit *SU = getSUnit(&(*MI)))
1125 const SUnit *DefSU = getSUnit(DefMI);
1280 if (SI->getSUnit() == SUb)
1282 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1283 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1306 ChainPredID = PI->getSUnit()
[all...] |
| H A D | CriticalAntiDepBreaker.cpp | 140 const SUnit *PredSU = P->getSUnit();
564 const SUnit *NextSU = Edge->getSUnit();
588 if (P->getSUnit() == NextSU ?
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| H A D | PostRASchedulerList.cpp | 422 SUnit *SuccSU = SuccEdge->getSUnit();
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 189 /// getSUnit - Return an existing SUnit for this MI, or NULL.
190 SUnit *getSUnit(MachineInstr *MI) const;
272 /// getSUnit - Return an existing SUnit for this MI, or NULL.
273 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const { function in class:llvm::ScheduleDAGInstrs
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| H A D | ScheduleDAG.h | 159 //// getSUnit - Return the SUnit to which this edge points.
160 SUnit *getSUnit() const { function in class:llvm::SDep
454 if (Preds[i].getSUnit() == N)
462 if (Succs[i].getSUnit() == N)
632 return Node->Preds[Operand].getSUnit();
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 79 SUnit *PredSU = I->getSUnit();
117 SUnit *SuccSU = I->getSUnit();
221 SUnit &Pred = *I->getSUnit();
239 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
283 if (I->getSUnit() == SU)
513 if (I->isCtrl() || (I->getSUnit()->NumRegDefsLeft == 0))
515 --I->getSUnit()->NumRegDefsLeft;
529 adjustPriorityOfUnscheduledPreds(I->getSUnit());
|
| H A D | ScheduleDAGFast.cpp | 141 SUnit *PredSU = PredEdge->getSUnit();
173 LiveRegDefs[I->getReg()] = I->getSUnit();
197 if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
290 else if (I->getSUnit()->getNode() &&
291 I->getSUnit()->getNode()->isOperandOf(LoadNode))
304 if (ChainPred.getSUnit()) {
323 SUnit *SuccDep = D.getSUnit();
331 SUnit *SuccDep = D.getSUnit();
370 SUnit *SuccSU = I->getSUnit();
407 SUnit *SuccSU = I->getSUnit();
[all...] |
| H A D | ScheduleDAGRRList.cpp | 201 Topo.AddPred(SU, D.getSUnit());
209 Topo.RemovePred(SU, D.getSUnit());
367 SUnit *PredSU = PredEdge->getSUnit();
537 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
539 LiveRegDefs[I->getReg()] = I->getSUnit();
793 SUnit *PredSU = PredEdge->getSUnit();
815 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
861 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
862 LiveRegGens[I->getReg()] = I->getSUnit();
1027 else if (isOperandOf(I->getSUnit(), LoadNod
[all...] |
| H A D | ScheduleDAGVLIW.cpp | 118 SUnit *SuccSU = D.getSUnit();
|
| H A D | ScheduleDAGSDNodes.cpp | 763 if (I->getSUnit()->CopyDstRC) {
765 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.cpp | 41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
49 if (SU->Preds[i].getSUnit() == CurGroup[j])
67 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
75 if (SU->Preds[i].getSUnit() == CurGroup[j])
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.cpp | 75 if (I->getSUnit() == SU)
229 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
248 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
430 SUnit &Pred = *I->getSUnit();
448 SUnit &Succ = *I->getSUnit();
509 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
515 if (getSingleUnscheduledSucc(I->getSUnit()) == SU)
|
| H A D | HexagonVLIWPacketizer.cpp | 828 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
911 if (PacketSU->Succs[i].getSUnit() == SU &&
1147 if (SUJ->Succs[i].getSUnit() != SUI) {
|
| /external/llvm/lib/Target/R600/ |
| H A D | R600Packetizer.cpp | 202 if (Dep.getSUnit() != SUI)
|