1/* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#ifndef _UAPI_I915_DRM_H_ 28#define _UAPI_I915_DRM_H_ 29 30#include <drm/drm.h> 31 32/* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36/** 37 * DOC: uevents generated by i915 on it's device node 38 * 39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40 * event from the gpu l3 cache. Additional information supplied is ROW, 41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 42 * track of these events and if a specific cache-line seems to have a 43 * persistent error remap it with the l3 remapping tool supplied in 44 * intel-gpu-tools. The value supplied with the event is always 1. 45 * 46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47 * hangcheck. The error detection event is a good indicator of when things 48 * began to go badly. The value supplied with the event is a 1 upon error 49 * detection, and a 0 upon reset completion, signifying no more error 50 * exists. NOTE: Disabling hangcheck or reset via module parameter will 51 * cause the related events to not be seen. 52 * 53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54 * the GPU. The value supplied with the event is always 1. NOTE: Disable 55 * reset via module parameter will cause this event to not be seen. 56 */ 57#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58#define I915_ERROR_UEVENT "ERROR" 59#define I915_RESET_UEVENT "RESET" 60 61/* Each region is a minimum of 16k, and there are at most 255 of them. 62 */ 63#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64 * of chars for next/prev indices */ 65#define I915_LOG_MIN_TEX_REGION_SIZE 14 66 67typedef struct _drm_i915_init { 68 enum { 69 I915_INIT_DMA = 0x01, 70 I915_CLEANUP_DMA = 0x02, 71 I915_RESUME_DMA = 0x03 72 } func; 73 unsigned int mmio_offset; 74 int sarea_priv_offset; 75 unsigned int ring_start; 76 unsigned int ring_end; 77 unsigned int ring_size; 78 unsigned int front_offset; 79 unsigned int back_offset; 80 unsigned int depth_offset; 81 unsigned int w; 82 unsigned int h; 83 unsigned int pitch; 84 unsigned int pitch_bits; 85 unsigned int back_pitch; 86 unsigned int depth_pitch; 87 unsigned int cpp; 88 unsigned int chipset; 89} drm_i915_init_t; 90 91typedef struct _drm_i915_sarea { 92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93 int last_upload; /* last time texture was uploaded */ 94 int last_enqueue; /* last time a buffer was enqueued */ 95 int last_dispatch; /* age of the most recently dispatched buffer */ 96 int ctxOwner; /* last context to upload state */ 97 int texAge; 98 int pf_enabled; /* is pageflipping allowed? */ 99 int pf_active; 100 int pf_current_page; /* which buffer is being displayed? */ 101 int perf_boxes; /* performance boxes to be displayed */ 102 int width, height; /* screen size in pixels */ 103 104 drm_handle_t front_handle; 105 int front_offset; 106 int front_size; 107 108 drm_handle_t back_handle; 109 int back_offset; 110 int back_size; 111 112 drm_handle_t depth_handle; 113 int depth_offset; 114 int depth_size; 115 116 drm_handle_t tex_handle; 117 int tex_offset; 118 int tex_size; 119 int log_tex_granularity; 120 int pitch; 121 int rotation; /* 0, 90, 180 or 270 */ 122 int rotated_offset; 123 int rotated_size; 124 int rotated_pitch; 125 int virtualX, virtualY; 126 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 133 int pipeA_x; 134 int pipeA_y; 135 int pipeA_w; 136 int pipeA_h; 137 int pipeB_x; 138 int pipeB_y; 139 int pipeB_w; 140 int pipeB_h; 141 142 /* fill out some space for old userspace triple buffer */ 143 drm_handle_t unused_handle; 144 __u32 unused1, unused2, unused3; 145 146 /* buffer object handles for static buffers. May change 147 * over the lifetime of the client. 148 */ 149 __u32 front_bo_handle; 150 __u32 back_bo_handle; 151 __u32 unused_bo_handle; 152 __u32 depth_bo_handle; 153 154} drm_i915_sarea_t; 155 156/* due to userspace building against these headers we need some compat here */ 157#define planeA_x pipeA_x 158#define planeA_y pipeA_y 159#define planeA_w pipeA_w 160#define planeA_h pipeA_h 161#define planeB_x pipeB_x 162#define planeB_y pipeB_y 163#define planeB_w pipeB_w 164#define planeB_h pipeB_h 165 166/* Flags for perf_boxes 167 */ 168#define I915_BOX_RING_EMPTY 0x1 169#define I915_BOX_FLIP 0x2 170#define I915_BOX_WAIT 0x4 171#define I915_BOX_TEXTURE_LOAD 0x8 172#define I915_BOX_LOST_CONTEXT 0x10 173 174/* I915 specific ioctls 175 * The device specific ioctl range is 0x40 to 0x79. 176 */ 177#define DRM_I915_INIT 0x00 178#define DRM_I915_FLUSH 0x01 179#define DRM_I915_FLIP 0x02 180#define DRM_I915_BATCHBUFFER 0x03 181#define DRM_I915_IRQ_EMIT 0x04 182#define DRM_I915_IRQ_WAIT 0x05 183#define DRM_I915_GETPARAM 0x06 184#define DRM_I915_SETPARAM 0x07 185#define DRM_I915_ALLOC 0x08 186#define DRM_I915_FREE 0x09 187#define DRM_I915_INIT_HEAP 0x0a 188#define DRM_I915_CMDBUFFER 0x0b 189#define DRM_I915_DESTROY_HEAP 0x0c 190#define DRM_I915_SET_VBLANK_PIPE 0x0d 191#define DRM_I915_GET_VBLANK_PIPE 0x0e 192#define DRM_I915_VBLANK_SWAP 0x0f 193#define DRM_I915_HWS_ADDR 0x11 194#define DRM_I915_GEM_INIT 0x13 195#define DRM_I915_GEM_EXECBUFFER 0x14 196#define DRM_I915_GEM_PIN 0x15 197#define DRM_I915_GEM_UNPIN 0x16 198#define DRM_I915_GEM_BUSY 0x17 199#define DRM_I915_GEM_THROTTLE 0x18 200#define DRM_I915_GEM_ENTERVT 0x19 201#define DRM_I915_GEM_LEAVEVT 0x1a 202#define DRM_I915_GEM_CREATE 0x1b 203#define DRM_I915_GEM_PREAD 0x1c 204#define DRM_I915_GEM_PWRITE 0x1d 205#define DRM_I915_GEM_MMAP 0x1e 206#define DRM_I915_GEM_SET_DOMAIN 0x1f 207#define DRM_I915_GEM_SW_FINISH 0x20 208#define DRM_I915_GEM_SET_TILING 0x21 209#define DRM_I915_GEM_GET_TILING 0x22 210#define DRM_I915_GEM_GET_APERTURE 0x23 211#define DRM_I915_GEM_MMAP_GTT 0x24 212#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 213#define DRM_I915_GEM_MADVISE 0x26 214#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 215#define DRM_I915_OVERLAY_ATTRS 0x28 216#define DRM_I915_GEM_EXECBUFFER2 0x29 217#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 218#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 219#define DRM_I915_GEM_WAIT 0x2c 220#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 221#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 222#define DRM_I915_GEM_SET_CACHING 0x2f 223#define DRM_I915_GEM_GET_CACHING 0x30 224#define DRM_I915_REG_READ 0x31 225#define DRM_I915_GET_RESET_STATS 0x32 226 227#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 228#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 229#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 230#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 231#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 232#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 233#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 234#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 235#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 236#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 237#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 238#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 239#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 240#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 241#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 242#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 243#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 244#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 245#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 246#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 247#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 248#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 249#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 250#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 251#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 252#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 253#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 254#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 255#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 256#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 257#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 258#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 259#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 260#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 261#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 262#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 263#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 264#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 265#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 266#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 267#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 268#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 269#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 270#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 271#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 272#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 273#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 274#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 275#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 276 277/* Allow drivers to submit batchbuffers directly to hardware, relying 278 * on the security mechanisms provided by hardware. 279 */ 280typedef struct drm_i915_batchbuffer { 281 int start; /* agp offset */ 282 int used; /* nr bytes in use */ 283 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 284 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 285 int num_cliprects; /* mulitpass with multiple cliprects? */ 286 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 287} drm_i915_batchbuffer_t; 288 289/* As above, but pass a pointer to userspace buffer which can be 290 * validated by the kernel prior to sending to hardware. 291 */ 292typedef struct _drm_i915_cmdbuffer { 293 char __user *buf; /* pointer to userspace command buffer */ 294 int sz; /* nr bytes in buf */ 295 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 296 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 297 int num_cliprects; /* mulitpass with multiple cliprects? */ 298 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 299} drm_i915_cmdbuffer_t; 300 301/* Userspace can request & wait on irq's: 302 */ 303typedef struct drm_i915_irq_emit { 304 int __user *irq_seq; 305} drm_i915_irq_emit_t; 306 307typedef struct drm_i915_irq_wait { 308 int irq_seq; 309} drm_i915_irq_wait_t; 310 311/* Ioctl to query kernel params: 312 */ 313#define I915_PARAM_IRQ_ACTIVE 1 314#define I915_PARAM_ALLOW_BATCHBUFFER 2 315#define I915_PARAM_LAST_DISPATCH 3 316#define I915_PARAM_CHIPSET_ID 4 317#define I915_PARAM_HAS_GEM 5 318#define I915_PARAM_NUM_FENCES_AVAIL 6 319#define I915_PARAM_HAS_OVERLAY 7 320#define I915_PARAM_HAS_PAGEFLIPPING 8 321#define I915_PARAM_HAS_EXECBUF2 9 322#define I915_PARAM_HAS_BSD 10 323#define I915_PARAM_HAS_BLT 11 324#define I915_PARAM_HAS_RELAXED_FENCING 12 325#define I915_PARAM_HAS_COHERENT_RINGS 13 326#define I915_PARAM_HAS_EXEC_CONSTANTS 14 327#define I915_PARAM_HAS_RELAXED_DELTA 15 328#define I915_PARAM_HAS_GEN7_SOL_RESET 16 329#define I915_PARAM_HAS_LLC 17 330#define I915_PARAM_HAS_ALIASING_PPGTT 18 331#define I915_PARAM_HAS_WAIT_TIMEOUT 19 332#define I915_PARAM_HAS_SEMAPHORES 20 333#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 334#define I915_PARAM_HAS_VEBOX 22 335#define I915_PARAM_HAS_SECURE_BATCHES 23 336#define I915_PARAM_HAS_PINNED_BATCHES 24 337#define I915_PARAM_HAS_EXEC_NO_RELOC 25 338#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 339#define I915_PARAM_HAS_WT 27 340 341typedef struct drm_i915_getparam { 342 int param; 343 int __user *value; 344} drm_i915_getparam_t; 345 346/* Ioctl to set kernel params: 347 */ 348#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 349#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 350#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 351#define I915_SETPARAM_NUM_USED_FENCES 4 352 353typedef struct drm_i915_setparam { 354 int param; 355 int value; 356} drm_i915_setparam_t; 357 358/* A memory manager for regions of shared memory: 359 */ 360#define I915_MEM_REGION_AGP 1 361 362typedef struct drm_i915_mem_alloc { 363 int region; 364 int alignment; 365 int size; 366 int __user *region_offset; /* offset from start of fb or agp */ 367} drm_i915_mem_alloc_t; 368 369typedef struct drm_i915_mem_free { 370 int region; 371 int region_offset; 372} drm_i915_mem_free_t; 373 374typedef struct drm_i915_mem_init_heap { 375 int region; 376 int size; 377 int start; 378} drm_i915_mem_init_heap_t; 379 380/* Allow memory manager to be torn down and re-initialized (eg on 381 * rotate): 382 */ 383typedef struct drm_i915_mem_destroy_heap { 384 int region; 385} drm_i915_mem_destroy_heap_t; 386 387/* Allow X server to configure which pipes to monitor for vblank signals 388 */ 389#define DRM_I915_VBLANK_PIPE_A 1 390#define DRM_I915_VBLANK_PIPE_B 2 391 392typedef struct drm_i915_vblank_pipe { 393 int pipe; 394} drm_i915_vblank_pipe_t; 395 396/* Schedule buffer swap at given vertical blank: 397 */ 398typedef struct drm_i915_vblank_swap { 399 drm_drawable_t drawable; 400 enum drm_vblank_seq_type seqtype; 401 unsigned int sequence; 402} drm_i915_vblank_swap_t; 403 404typedef struct drm_i915_hws_addr { 405 __u64 addr; 406} drm_i915_hws_addr_t; 407 408struct drm_i915_gem_init { 409 /** 410 * Beginning offset in the GTT to be managed by the DRM memory 411 * manager. 412 */ 413 __u64 gtt_start; 414 /** 415 * Ending offset in the GTT to be managed by the DRM memory 416 * manager. 417 */ 418 __u64 gtt_end; 419}; 420 421struct drm_i915_gem_create { 422 /** 423 * Requested size for the object. 424 * 425 * The (page-aligned) allocated size for the object will be returned. 426 */ 427 __u64 size; 428 /** 429 * Returned handle for the object. 430 * 431 * Object handles are nonzero. 432 */ 433 __u32 handle; 434 __u32 pad; 435}; 436 437struct drm_i915_gem_pread { 438 /** Handle for the object being read. */ 439 __u32 handle; 440 __u32 pad; 441 /** Offset into the object to read from */ 442 __u64 offset; 443 /** Length of data to read */ 444 __u64 size; 445 /** 446 * Pointer to write the data into. 447 * 448 * This is a fixed-size type for 32/64 compatibility. 449 */ 450 __u64 data_ptr; 451}; 452 453struct drm_i915_gem_pwrite { 454 /** Handle for the object being written to. */ 455 __u32 handle; 456 __u32 pad; 457 /** Offset into the object to write to */ 458 __u64 offset; 459 /** Length of data to write */ 460 __u64 size; 461 /** 462 * Pointer to read the data from. 463 * 464 * This is a fixed-size type for 32/64 compatibility. 465 */ 466 __u64 data_ptr; 467}; 468 469struct drm_i915_gem_mmap { 470 /** Handle for the object being mapped. */ 471 __u32 handle; 472 __u32 pad; 473 /** Offset in the object to map. */ 474 __u64 offset; 475 /** 476 * Length of data to map. 477 * 478 * The value will be page-aligned. 479 */ 480 __u64 size; 481 /** 482 * Returned pointer the data was mapped at. 483 * 484 * This is a fixed-size type for 32/64 compatibility. 485 */ 486 __u64 addr_ptr; 487}; 488 489struct drm_i915_gem_mmap_gtt { 490 /** Handle for the object being mapped. */ 491 __u32 handle; 492 __u32 pad; 493 /** 494 * Fake offset to use for subsequent mmap call 495 * 496 * This is a fixed-size type for 32/64 compatibility. 497 */ 498 __u64 offset; 499}; 500 501struct drm_i915_gem_set_domain { 502 /** Handle for the object */ 503 __u32 handle; 504 505 /** New read domains */ 506 __u32 read_domains; 507 508 /** New write domain */ 509 __u32 write_domain; 510}; 511 512struct drm_i915_gem_sw_finish { 513 /** Handle for the object */ 514 __u32 handle; 515}; 516 517struct drm_i915_gem_relocation_entry { 518 /** 519 * Handle of the buffer being pointed to by this relocation entry. 520 * 521 * It's appealing to make this be an index into the mm_validate_entry 522 * list to refer to the buffer, but this allows the driver to create 523 * a relocation list for state buffers and not re-write it per 524 * exec using the buffer. 525 */ 526 __u32 target_handle; 527 528 /** 529 * Value to be added to the offset of the target buffer to make up 530 * the relocation entry. 531 */ 532 __u32 delta; 533 534 /** Offset in the buffer the relocation entry will be written into */ 535 __u64 offset; 536 537 /** 538 * Offset value of the target buffer that the relocation entry was last 539 * written as. 540 * 541 * If the buffer has the same offset as last time, we can skip syncing 542 * and writing the relocation. This value is written back out by 543 * the execbuffer ioctl when the relocation is written. 544 */ 545 __u64 presumed_offset; 546 547 /** 548 * Target memory domains read by this operation. 549 */ 550 __u32 read_domains; 551 552 /** 553 * Target memory domains written by this operation. 554 * 555 * Note that only one domain may be written by the whole 556 * execbuffer operation, so that where there are conflicts, 557 * the application will get -EINVAL back. 558 */ 559 __u32 write_domain; 560}; 561 562/** @{ 563 * Intel memory domains 564 * 565 * Most of these just align with the various caches in 566 * the system and are used to flush and invalidate as 567 * objects end up cached in different domains. 568 */ 569/** CPU cache */ 570#define I915_GEM_DOMAIN_CPU 0x00000001 571/** Render cache, used by 2D and 3D drawing */ 572#define I915_GEM_DOMAIN_RENDER 0x00000002 573/** Sampler cache, used by texture engine */ 574#define I915_GEM_DOMAIN_SAMPLER 0x00000004 575/** Command queue, used to load batch buffers */ 576#define I915_GEM_DOMAIN_COMMAND 0x00000008 577/** Instruction cache, used by shader programs */ 578#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 579/** Vertex address cache */ 580#define I915_GEM_DOMAIN_VERTEX 0x00000020 581/** GTT domain - aperture and scanout */ 582#define I915_GEM_DOMAIN_GTT 0x00000040 583/** @} */ 584 585struct drm_i915_gem_exec_object { 586 /** 587 * User's handle for a buffer to be bound into the GTT for this 588 * operation. 589 */ 590 __u32 handle; 591 592 /** Number of relocations to be performed on this buffer */ 593 __u32 relocation_count; 594 /** 595 * Pointer to array of struct drm_i915_gem_relocation_entry containing 596 * the relocations to be performed in this buffer. 597 */ 598 __u64 relocs_ptr; 599 600 /** Required alignment in graphics aperture */ 601 __u64 alignment; 602 603 /** 604 * Returned value of the updated offset of the object, for future 605 * presumed_offset writes. 606 */ 607 __u64 offset; 608}; 609 610struct drm_i915_gem_execbuffer { 611 /** 612 * List of buffers to be validated with their relocations to be 613 * performend on them. 614 * 615 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 616 * 617 * These buffers must be listed in an order such that all relocations 618 * a buffer is performing refer to buffers that have already appeared 619 * in the validate list. 620 */ 621 __u64 buffers_ptr; 622 __u32 buffer_count; 623 624 /** Offset in the batchbuffer to start execution from. */ 625 __u32 batch_start_offset; 626 /** Bytes used in batchbuffer from batch_start_offset */ 627 __u32 batch_len; 628 __u32 DR1; 629 __u32 DR4; 630 __u32 num_cliprects; 631 /** This is a struct drm_clip_rect *cliprects */ 632 __u64 cliprects_ptr; 633}; 634 635struct drm_i915_gem_exec_object2 { 636 /** 637 * User's handle for a buffer to be bound into the GTT for this 638 * operation. 639 */ 640 __u32 handle; 641 642 /** Number of relocations to be performed on this buffer */ 643 __u32 relocation_count; 644 /** 645 * Pointer to array of struct drm_i915_gem_relocation_entry containing 646 * the relocations to be performed in this buffer. 647 */ 648 __u64 relocs_ptr; 649 650 /** Required alignment in graphics aperture */ 651 __u64 alignment; 652 653 /** 654 * Returned value of the updated offset of the object, for future 655 * presumed_offset writes. 656 */ 657 __u64 offset; 658 659#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 660#define EXEC_OBJECT_NEEDS_GTT (1<<1) 661#define EXEC_OBJECT_WRITE (1<<2) 662#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 663 __u64 flags; 664 665 __u64 rsvd1; 666 __u64 rsvd2; 667}; 668 669struct drm_i915_gem_execbuffer2 { 670 /** 671 * List of gem_exec_object2 structs 672 */ 673 __u64 buffers_ptr; 674 __u32 buffer_count; 675 676 /** Offset in the batchbuffer to start execution from. */ 677 __u32 batch_start_offset; 678 /** Bytes used in batchbuffer from batch_start_offset */ 679 __u32 batch_len; 680 __u32 DR1; 681 __u32 DR4; 682 __u32 num_cliprects; 683 /** This is a struct drm_clip_rect *cliprects */ 684 __u64 cliprects_ptr; 685#define I915_EXEC_RING_MASK (7<<0) 686#define I915_EXEC_DEFAULT (0<<0) 687#define I915_EXEC_RENDER (1<<0) 688#define I915_EXEC_BSD (2<<0) 689#define I915_EXEC_BLT (3<<0) 690#define I915_EXEC_VEBOX (4<<0) 691 692/* Used for switching the constants addressing mode on gen4+ RENDER ring. 693 * Gen6+ only supports relative addressing to dynamic state (default) and 694 * absolute addressing. 695 * 696 * These flags are ignored for the BSD and BLT rings. 697 */ 698#define I915_EXEC_CONSTANTS_MASK (3<<6) 699#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 700#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 701#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 702 __u64 flags; 703 __u64 rsvd1; /* now used for context info */ 704 __u64 rsvd2; 705}; 706 707/** Resets the SO write offset registers for transform feedback on gen7. */ 708#define I915_EXEC_GEN7_SOL_RESET (1<<8) 709 710/** Request a privileged ("secure") batch buffer. Note only available for 711 * DRM_ROOT_ONLY | DRM_MASTER processes. 712 */ 713#define I915_EXEC_SECURE (1<<9) 714 715/** Inform the kernel that the batch is and will always be pinned. This 716 * negates the requirement for a workaround to be performed to avoid 717 * an incoherent CS (such as can be found on 830/845). If this flag is 718 * not passed, the kernel will endeavour to make sure the batch is 719 * coherent with the CS before execution. If this flag is passed, 720 * userspace assumes the responsibility for ensuring the same. 721 */ 722#define I915_EXEC_IS_PINNED (1<<10) 723 724/** Provide a hint to the kernel that the command stream and auxiliary 725 * state buffers already holds the correct presumed addresses and so the 726 * relocation process may be skipped if no buffers need to be moved in 727 * preparation for the execbuffer. 728 */ 729#define I915_EXEC_NO_RELOC (1<<11) 730 731/** Use the reloc.handle as an index into the exec object array rather 732 * than as the per-file handle. 733 */ 734#define I915_EXEC_HANDLE_LUT (1<<12) 735 736#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) 737 738#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 739#define i915_execbuffer2_set_context_id(eb2, context) \ 740 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 741#define i915_execbuffer2_get_context_id(eb2) \ 742 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 743 744struct drm_i915_gem_pin { 745 /** Handle of the buffer to be pinned. */ 746 __u32 handle; 747 __u32 pad; 748 749 /** alignment required within the aperture */ 750 __u64 alignment; 751 752 /** Returned GTT offset of the buffer. */ 753 __u64 offset; 754}; 755 756struct drm_i915_gem_unpin { 757 /** Handle of the buffer to be unpinned. */ 758 __u32 handle; 759 __u32 pad; 760}; 761 762struct drm_i915_gem_busy { 763 /** Handle of the buffer to check for busy */ 764 __u32 handle; 765 766 /** Return busy status (1 if busy, 0 if idle). 767 * The high word is used to indicate on which rings the object 768 * currently resides: 769 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 770 */ 771 __u32 busy; 772}; 773 774/** 775 * I915_CACHING_NONE 776 * 777 * GPU access is not coherent with cpu caches. Default for machines without an 778 * LLC. 779 */ 780#define I915_CACHING_NONE 0 781/** 782 * I915_CACHING_CACHED 783 * 784 * GPU access is coherent with cpu caches and furthermore the data is cached in 785 * last-level caches shared between cpu cores and the gpu GT. Default on 786 * machines with HAS_LLC. 787 */ 788#define I915_CACHING_CACHED 1 789/** 790 * I915_CACHING_DISPLAY 791 * 792 * Special GPU caching mode which is coherent with the scanout engines. 793 * Transparently falls back to I915_CACHING_NONE on platforms where no special 794 * cache mode (like write-through or gfdt flushing) is available. The kernel 795 * automatically sets this mode when using a buffer as a scanout target. 796 * Userspace can manually set this mode to avoid a costly stall and clflush in 797 * the hotpath of drawing the first frame. 798 */ 799#define I915_CACHING_DISPLAY 2 800 801struct drm_i915_gem_caching { 802 /** 803 * Handle of the buffer to set/get the caching level of. */ 804 __u32 handle; 805 806 /** 807 * Cacheing level to apply or return value 808 * 809 * bits0-15 are for generic caching control (i.e. the above defined 810 * values). bits16-31 are reserved for platform-specific variations 811 * (e.g. l3$ caching on gen7). */ 812 __u32 caching; 813}; 814 815#define I915_TILING_NONE 0 816#define I915_TILING_X 1 817#define I915_TILING_Y 2 818 819#define I915_BIT_6_SWIZZLE_NONE 0 820#define I915_BIT_6_SWIZZLE_9 1 821#define I915_BIT_6_SWIZZLE_9_10 2 822#define I915_BIT_6_SWIZZLE_9_11 3 823#define I915_BIT_6_SWIZZLE_9_10_11 4 824/* Not seen by userland */ 825#define I915_BIT_6_SWIZZLE_UNKNOWN 5 826/* Seen by userland. */ 827#define I915_BIT_6_SWIZZLE_9_17 6 828#define I915_BIT_6_SWIZZLE_9_10_17 7 829 830struct drm_i915_gem_set_tiling { 831 /** Handle of the buffer to have its tiling state updated */ 832 __u32 handle; 833 834 /** 835 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 836 * I915_TILING_Y). 837 * 838 * This value is to be set on request, and will be updated by the 839 * kernel on successful return with the actual chosen tiling layout. 840 * 841 * The tiling mode may be demoted to I915_TILING_NONE when the system 842 * has bit 6 swizzling that can't be managed correctly by GEM. 843 * 844 * Buffer contents become undefined when changing tiling_mode. 845 */ 846 __u32 tiling_mode; 847 848 /** 849 * Stride in bytes for the object when in I915_TILING_X or 850 * I915_TILING_Y. 851 */ 852 __u32 stride; 853 854 /** 855 * Returned address bit 6 swizzling required for CPU access through 856 * mmap mapping. 857 */ 858 __u32 swizzle_mode; 859}; 860 861struct drm_i915_gem_get_tiling { 862 /** Handle of the buffer to get tiling state for. */ 863 __u32 handle; 864 865 /** 866 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 867 * I915_TILING_Y). 868 */ 869 __u32 tiling_mode; 870 871 /** 872 * Returned address bit 6 swizzling required for CPU access through 873 * mmap mapping. 874 */ 875 __u32 swizzle_mode; 876}; 877 878struct drm_i915_gem_get_aperture { 879 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 880 __u64 aper_size; 881 882 /** 883 * Available space in the aperture used by i915_gem_execbuffer, in 884 * bytes 885 */ 886 __u64 aper_available_size; 887}; 888 889struct drm_i915_get_pipe_from_crtc_id { 890 /** ID of CRTC being requested **/ 891 __u32 crtc_id; 892 893 /** pipe of requested CRTC **/ 894 __u32 pipe; 895}; 896 897#define I915_MADV_WILLNEED 0 898#define I915_MADV_DONTNEED 1 899#define __I915_MADV_PURGED 2 /* internal state */ 900 901struct drm_i915_gem_madvise { 902 /** Handle of the buffer to change the backing store advice */ 903 __u32 handle; 904 905 /* Advice: either the buffer will be needed again in the near future, 906 * or wont be and could be discarded under memory pressure. 907 */ 908 __u32 madv; 909 910 /** Whether the backing store still exists. */ 911 __u32 retained; 912}; 913 914/* flags */ 915#define I915_OVERLAY_TYPE_MASK 0xff 916#define I915_OVERLAY_YUV_PLANAR 0x01 917#define I915_OVERLAY_YUV_PACKED 0x02 918#define I915_OVERLAY_RGB 0x03 919 920#define I915_OVERLAY_DEPTH_MASK 0xff00 921#define I915_OVERLAY_RGB24 0x1000 922#define I915_OVERLAY_RGB16 0x2000 923#define I915_OVERLAY_RGB15 0x3000 924#define I915_OVERLAY_YUV422 0x0100 925#define I915_OVERLAY_YUV411 0x0200 926#define I915_OVERLAY_YUV420 0x0300 927#define I915_OVERLAY_YUV410 0x0400 928 929#define I915_OVERLAY_SWAP_MASK 0xff0000 930#define I915_OVERLAY_NO_SWAP 0x000000 931#define I915_OVERLAY_UV_SWAP 0x010000 932#define I915_OVERLAY_Y_SWAP 0x020000 933#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 934 935#define I915_OVERLAY_FLAGS_MASK 0xff000000 936#define I915_OVERLAY_ENABLE 0x01000000 937 938struct drm_intel_overlay_put_image { 939 /* various flags and src format description */ 940 __u32 flags; 941 /* source picture description */ 942 __u32 bo_handle; 943 /* stride values and offsets are in bytes, buffer relative */ 944 __u16 stride_Y; /* stride for packed formats */ 945 __u16 stride_UV; 946 __u32 offset_Y; /* offset for packet formats */ 947 __u32 offset_U; 948 __u32 offset_V; 949 /* in pixels */ 950 __u16 src_width; 951 __u16 src_height; 952 /* to compensate the scaling factors for partially covered surfaces */ 953 __u16 src_scan_width; 954 __u16 src_scan_height; 955 /* output crtc description */ 956 __u32 crtc_id; 957 __u16 dst_x; 958 __u16 dst_y; 959 __u16 dst_width; 960 __u16 dst_height; 961}; 962 963/* flags */ 964#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 965#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 966struct drm_intel_overlay_attrs { 967 __u32 flags; 968 __u32 color_key; 969 __s32 brightness; 970 __u32 contrast; 971 __u32 saturation; 972 __u32 gamma0; 973 __u32 gamma1; 974 __u32 gamma2; 975 __u32 gamma3; 976 __u32 gamma4; 977 __u32 gamma5; 978}; 979 980/* 981 * Intel sprite handling 982 * 983 * Color keying works with a min/mask/max tuple. Both source and destination 984 * color keying is allowed. 985 * 986 * Source keying: 987 * Sprite pixels within the min & max values, masked against the color channels 988 * specified in the mask field, will be transparent. All other pixels will 989 * be displayed on top of the primary plane. For RGB surfaces, only the min 990 * and mask fields will be used; ranged compares are not allowed. 991 * 992 * Destination keying: 993 * Primary plane pixels that match the min value, masked against the color 994 * channels specified in the mask field, will be replaced by corresponding 995 * pixels from the sprite plane. 996 * 997 * Note that source & destination keying are exclusive; only one can be 998 * active on a given plane. 999 */ 1000 1001#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1002#define I915_SET_COLORKEY_DESTINATION (1<<1) 1003#define I915_SET_COLORKEY_SOURCE (1<<2) 1004struct drm_intel_sprite_colorkey { 1005 __u32 plane_id; 1006 __u32 min_value; 1007 __u32 channel_mask; 1008 __u32 max_value; 1009 __u32 flags; 1010}; 1011 1012struct drm_i915_gem_wait { 1013 /** Handle of BO we shall wait on */ 1014 __u32 bo_handle; 1015 __u32 flags; 1016 /** Number of nanoseconds to wait, Returns time remaining. */ 1017 __s64 timeout_ns; 1018}; 1019 1020struct drm_i915_gem_context_create { 1021 /* output: id of new context*/ 1022 __u32 ctx_id; 1023 __u32 pad; 1024}; 1025 1026struct drm_i915_gem_context_destroy { 1027 __u32 ctx_id; 1028 __u32 pad; 1029}; 1030 1031struct drm_i915_reg_read { 1032 __u64 offset; 1033 __u64 val; /* Return value */ 1034}; 1035 1036struct drm_i915_reset_stats { 1037 __u32 ctx_id; 1038 __u32 flags; 1039 1040 /* All resets since boot/module reload, for all contexts */ 1041 __u32 reset_count; 1042 1043 /* Number of batches lost when active in GPU, for this context */ 1044 __u32 batch_active; 1045 1046 /* Number of batches lost pending for execution, for this context */ 1047 __u32 batch_pending; 1048 1049 __u32 pad; 1050}; 1051 1052#endif /* _UAPI_I915_DRM_H_ */ 1053