1; RUN: llc -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s 2; RUN: llc -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s 3 4target triple = "powerpc64-unknown-linux-gnu" 5; Test correct assembly code generation for thread-local storage using 6; the local dynamic model. 7 8@a = hidden thread_local global i32 0, align 4 9 10define signext i32 @main() nounwind { 11entry: 12 %retval = alloca i32, align 4 13 store i32 0, i32* %retval 14 %0 = load i32* @a, align 4 15 ret i32 %0 16} 17 18; OPT0-LABEL: main: 19; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha 20; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l 21; OPT0: bl __tls_get_addr(a@tlsld) 22; OPT0-NEXT: nop 23; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha 24; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l 25 26; Test peephole optimization for thread-local storage using the 27; local dynamic model. 28 29; OPT1-LABEL: main: 30; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha 31; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l 32; OPT1: bl __tls_get_addr(a@tlsld) 33; OPT1-NEXT: nop 34; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha 35; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) 36 37; Test correct assembly code generation for thread-local storage using 38; the general dynamic model. 39 40@a2 = thread_local global i32 0, align 4 41 42define signext i32 @main2() nounwind { 43entry: 44 %retval = alloca i32, align 4 45 store i32 0, i32* %retval 46 %0 = load i32* @a2, align 4 47 ret i32 %0 48} 49 50; OPT1-LABEL: main2 51; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha 52; OPT1-NEXT: addi 3, [[REG]], a2@got@tlsgd@l 53; OPT1: bl __tls_get_addr(a2@tlsgd) 54; OPT1-NEXT: nop 55 56