r600_state.c revision 231bf886dae9c7df0ae3e16acee904024a08824f
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24/* TODO: 25 * - fix mask for depth control & cull for query 26 */ 27#include <stdio.h> 28#include <errno.h> 29#include <pipe/p_defines.h> 30#include <pipe/p_state.h> 31#include <pipe/p_context.h> 32#include <tgsi/tgsi_scan.h> 33#include <tgsi/tgsi_parse.h> 34#include <tgsi/tgsi_util.h> 35#include <util/u_double_list.h> 36#include <util/u_pack_color.h> 37#include <util/u_memory.h> 38#include <util/u_inlines.h> 39#include <util/u_framebuffer.h> 40#include "util/u_transfer.h" 41#include <pipebuffer/pb_buffer.h> 42#include "r600.h" 43#include "r600d.h" 44#include "r600_resource.h" 45#include "r600_shader.h" 46#include "r600_pipe.h" 47#include "r600_state_inlines.h" 48 49void r600_polygon_offset_update(struct r600_pipe_context *rctx) 50{ 51 struct r600_pipe_state state; 52 53 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 54 state.nregs = 0; 55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 56 float offset_units = rctx->rasterizer->offset_units; 57 unsigned offset_db_fmt_cntl = 0, depth; 58 59 switch (rctx->framebuffer.zsbuf->texture->format) { 60 case PIPE_FORMAT_Z24X8_UNORM: 61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED: 62 depth = -24; 63 offset_units *= 2.0f; 64 break; 65 case PIPE_FORMAT_Z32_FLOAT: 66 depth = -23; 67 offset_units *= 1.0f; 68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 69 break; 70 case PIPE_FORMAT_Z16_UNORM: 71 depth = -16; 72 offset_units *= 4.0f; 73 break; 74 default: 75 return; 76 } 77 /* FIXME some of those reg can be computed with cso */ 78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 79 r600_pipe_state_add_reg(&state, 80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL); 82 r600_pipe_state_add_reg(&state, 83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 84 fui(offset_units), 0xFFFFFFFF, NULL); 85 r600_pipe_state_add_reg(&state, 86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL); 88 r600_pipe_state_add_reg(&state, 89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 90 fui(offset_units), 0xFFFFFFFF, NULL); 91 r600_pipe_state_add_reg(&state, 92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL); 94 r600_context_pipe_state_set(&rctx->ctx, &state); 95 } 96} 97 98static void r600_set_blend_color(struct pipe_context *ctx, 99 const struct pipe_blend_color *state) 100{ 101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 103 104 if (rstate == NULL) 105 return; 106 107 rstate->id = R600_PIPE_STATE_BLEND_COLOR; 108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL); 109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL); 110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL); 111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL); 112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); 113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; 114 r600_context_pipe_state_set(&rctx->ctx, rstate); 115} 116 117static void *r600_create_blend_state(struct pipe_context *ctx, 118 const struct pipe_blend_state *state) 119{ 120 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 121 struct r600_pipe_state *rstate; 122 u32 color_control, target_mask; 123 124 if (blend == NULL) { 125 return NULL; 126 } 127 rstate = &blend->rstate; 128 129 rstate->id = R600_PIPE_STATE_BLEND; 130 131 target_mask = 0; 132 color_control = S_028808_PER_MRT_BLEND(1); 133 if (state->logicop_enable) { 134 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 135 } else { 136 color_control |= (0xcc << 16); 137 } 138 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 139 if (state->independent_blend_enable) { 140 for (int i = 0; i < 8; i++) { 141 if (state->rt[i].blend_enable) { 142 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 143 } 144 target_mask |= (state->rt[i].colormask << (4 * i)); 145 } 146 } else { 147 for (int i = 0; i < 8; i++) { 148 if (state->rt[0].blend_enable) { 149 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 150 } 151 target_mask |= (state->rt[0].colormask << (4 * i)); 152 } 153 } 154 blend->cb_target_mask = target_mask; 155 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, 156 color_control, 0xFFFFFFFF, NULL); 157 158 for (int i = 0; i < 8; i++) { 159 unsigned eqRGB = state->rt[i].rgb_func; 160 unsigned srcRGB = state->rt[i].rgb_src_factor; 161 unsigned dstRGB = state->rt[i].rgb_dst_factor; 162 163 unsigned eqA = state->rt[i].alpha_func; 164 unsigned srcA = state->rt[i].alpha_src_factor; 165 unsigned dstA = state->rt[i].alpha_dst_factor; 166 uint32_t bc = 0; 167 168 if (!state->rt[i].blend_enable) 169 continue; 170 171 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 172 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 173 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 174 175 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 176 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 177 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 178 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 179 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 180 } 181 182 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL); 183 if (i == 0) { 184 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL); 185 } 186 } 187 return rstate; 188} 189 190static void *r600_create_dsa_state(struct pipe_context *ctx, 191 const struct pipe_depth_stencil_alpha_state *state) 192{ 193 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 194 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control; 195 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control; 196 197 if (rstate == NULL) { 198 return NULL; 199 } 200 201 rstate->id = R600_PIPE_STATE_DSA; 202 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */ 203 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be 204 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will 205 * be set if shader use texkill instruction 206 */ 207 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 208 stencil_ref_mask = 0; 209 stencil_ref_mask_bf = 0; 210 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 211 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 212 S_028800_ZFUNC(state->depth.func); 213 214 /* stencil */ 215 if (state->stencil[0].enabled) { 216 db_depth_control |= S_028800_STENCIL_ENABLE(1); 217 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); 218 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 219 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 220 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 221 222 223 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | 224 S_028430_STENCILWRITEMASK(state->stencil[0].writemask); 225 if (state->stencil[1].enabled) { 226 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 227 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); 228 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 229 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 230 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 231 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | 232 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); 233 } 234 } 235 236 /* alpha */ 237 alpha_test_control = 0; 238 alpha_ref = 0; 239 if (state->alpha.enabled) { 240 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 241 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 242 alpha_ref = fui(state->alpha.ref_value); 243 } 244 245 /* misc */ 246 db_render_control = 0; 247 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | 248 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 249 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 250 /* TODO db_render_override depends on query */ 251 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL); 252 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL); 253 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL); 254 r600_pipe_state_add_reg(rstate, 255 R_028430_DB_STENCILREFMASK, stencil_ref_mask, 256 0xFFFFFFFF & C_028430_STENCILREF, NULL); 257 r600_pipe_state_add_reg(rstate, 258 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf, 259 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL); 260 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL); 261 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL); 262 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL); 263 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 264 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL); 265 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL); 266 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL); 267 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL); 268 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL); 269 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL); 270 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL); 271 272 return rstate; 273} 274 275static void *r600_create_rs_state(struct pipe_context *ctx, 276 const struct pipe_rasterizer_state *state) 277{ 278 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 279 struct r600_pipe_state *rstate; 280 unsigned tmp; 281 unsigned prov_vtx = 1, polygon_dual_mode; 282 unsigned clip_rule; 283 284 if (rs == NULL) { 285 return NULL; 286 } 287 288 rstate = &rs->rstate; 289 rs->flatshade = state->flatshade; 290 rs->sprite_coord_enable = state->sprite_coord_enable; 291 292 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 293 /* offset */ 294 rs->offset_units = state->offset_units; 295 rs->offset_scale = state->offset_scale * 12.0f; 296 297 rstate->id = R600_PIPE_STATE_RASTERIZER; 298 if (state->flatshade_first) 299 prov_vtx = 0; 300 tmp = S_0286D4_FLAT_SHADE_ENA(1); 301 if (state->sprite_coord_enable) { 302 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 303 S_0286D4_PNT_SPRITE_OVRD_X(2) | 304 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 305 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 306 S_0286D4_PNT_SPRITE_OVRD_W(1); 307 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 308 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 309 } 310 } 311 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL); 312 313 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 314 state->fill_back != PIPE_POLYGON_MODE_FILL); 315 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 316 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 317 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 318 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 319 S_028814_FACE(!state->front_ccw) | 320 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 321 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 322 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 323 S_028814_POLY_MODE(polygon_dual_mode) | 324 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 325 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL); 326 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL, 327 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | 328 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL); 329 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 330 /* point size 12.4 fixed point */ 331 tmp = (unsigned)(state->point_size * 8.0); 332 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL); 333 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL); 334 335 tmp = (unsigned)state->line_width * 8; 336 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL); 337 338 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL); 339 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 340 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL); 341 342 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 343 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), 344 0xFFFFFFFF, NULL); 345 346 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 347 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 348 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 349 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 350 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL); 351 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL); 352 353 return rstate; 354} 355 356static void *r600_create_sampler_state(struct pipe_context *ctx, 357 const struct pipe_sampler_state *state) 358{ 359 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 360 union util_color uc; 361 362 if (rstate == NULL) { 363 return NULL; 364 } 365 366 rstate->id = R600_PIPE_STATE_SAMPLER; 367 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 368 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 369 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 370 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 371 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 372 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | 373 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | 374 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 375 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 376 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL); 377 /* FIXME LOD it depends on texture base level ... */ 378 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 379 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 380 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 381 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL); 382 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL); 383 if (uc.ui) { 384 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL); 385 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL); 386 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL); 387 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL); 388 } 389 return rstate; 390} 391 392static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 393 struct pipe_resource *texture, 394 const struct pipe_sampler_view *state) 395{ 396 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view); 397 struct r600_pipe_state *rstate; 398 const struct util_format_description *desc; 399 struct r600_resource_texture *tmp; 400 struct r600_resource *rbuffer; 401 unsigned format; 402 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 403 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 404 struct r600_bo *bo[2]; 405 406 if (resource == NULL) 407 return NULL; 408 rstate = &resource->state; 409 410 /* initialize base object */ 411 resource->base = *state; 412 resource->base.texture = NULL; 413 pipe_reference(NULL, &texture->reference); 414 resource->base.texture = texture; 415 resource->base.reference.count = 1; 416 resource->base.context = ctx; 417 418 swizzle[0] = state->swizzle_r; 419 swizzle[1] = state->swizzle_g; 420 swizzle[2] = state->swizzle_b; 421 swizzle[3] = state->swizzle_a; 422 format = r600_translate_texformat(state->format, 423 swizzle, 424 &word4, &yuv_format); 425 if (format == ~0) { 426 format = 0; 427 } 428 desc = util_format_description(state->format); 429 if (desc == NULL) { 430 R600_ERR("unknow format %d\n", state->format); 431 } 432 tmp = (struct r600_resource_texture *)texture; 433 if (tmp->depth && !tmp->is_flushing_texture) { 434 r600_texture_depth_flush(ctx, texture, TRUE); 435 tmp = tmp->flushed_depth_texture; 436 } 437 438 if (tmp->force_int_type) { 439 word4 &= C_038010_NUM_FORMAT_ALL; 440 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 441 } 442 rbuffer = &tmp->resource; 443 bo[0] = rbuffer->bo; 444 bo[1] = rbuffer->bo; 445 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8); 446 array_mode = tmp->array_mode[0]; 447 tile_type = tmp->tile_type; 448 449 /* FIXME properly handle first level != 0 */ 450 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, 451 S_038000_DIM(r600_tex_dim(texture->target)) | 452 S_038000_TILE_MODE(array_mode) | 453 S_038000_TILE_TYPE(tile_type) | 454 S_038000_PITCH((pitch / 8) - 1) | 455 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL); 456 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, 457 S_038004_TEX_HEIGHT(texture->height0 - 1) | 458 S_038004_TEX_DEPTH(texture->depth0 - 1) | 459 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL); 460 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, 461 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); 462 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 463 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]); 464 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 465 word4 | 466 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) | 467 S_038010_REQUEST_SIZE(1) | 468 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL); 469 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 470 S_038014_LAST_LEVEL(state->u.tex.last_level) | 471 S_038014_BASE_ARRAY(0) | 472 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL); 473 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 474 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL); 475 476 return &resource->base; 477} 478 479static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, 480 struct pipe_sampler_view **views) 481{ 482 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 483 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views; 484 485 for (int i = 0; i < count; i++) { 486 if (resource[i]) { 487 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i); 488 } 489 } 490} 491 492static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, 493 struct pipe_sampler_view **views) 494{ 495 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 496 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views; 497 int i; 498 499 for (i = 0; i < count; i++) { 500 if (&rctx->ps_samplers.views[i]->base != views[i]) { 501 if (resource[i]) 502 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, 503 i + R600_MAX_CONST_BUFFERS); 504 else 505 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, 506 i + R600_MAX_CONST_BUFFERS); 507 508 pipe_sampler_view_reference( 509 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i], 510 views[i]); 511 512 } 513 } 514 for (i = count; i < NUM_TEX_UNITS; i++) { 515 if (rctx->ps_samplers.views[i]) { 516 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, 517 i + R600_MAX_CONST_BUFFERS); 518 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL); 519 } 520 } 521 rctx->ps_samplers.n_views = count; 522} 523 524static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) 525{ 526 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 527 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states; 528 529 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count); 530 rctx->ps_samplers.n_samplers = count; 531 532 for (int i = 0; i < count; i++) { 533 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i); 534 } 535} 536 537static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) 538{ 539 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 540 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states; 541 542 for (int i = 0; i < count; i++) { 543 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i); 544 } 545} 546 547static void r600_set_clip_state(struct pipe_context *ctx, 548 const struct pipe_clip_state *state) 549{ 550 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 551 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 552 553 if (rstate == NULL) 554 return; 555 556 rctx->clip = *state; 557 rstate->id = R600_PIPE_STATE_CLIP; 558 for (int i = 0; i < state->nr; i++) { 559 r600_pipe_state_add_reg(rstate, 560 R_028E20_PA_CL_UCP0_X + i * 16, 561 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL); 562 r600_pipe_state_add_reg(rstate, 563 R_028E24_PA_CL_UCP0_Y + i * 16, 564 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL); 565 r600_pipe_state_add_reg(rstate, 566 R_028E28_PA_CL_UCP0_Z + i * 16, 567 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL); 568 r600_pipe_state_add_reg(rstate, 569 R_028E2C_PA_CL_UCP0_W + i * 16, 570 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL); 571 } 572 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 573 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) | 574 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) | 575 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL); 576 577 free(rctx->states[R600_PIPE_STATE_CLIP]); 578 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 579 r600_context_pipe_state_set(&rctx->ctx, rstate); 580} 581 582static void r600_set_polygon_stipple(struct pipe_context *ctx, 583 const struct pipe_poly_stipple *state) 584{ 585} 586 587static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 588{ 589} 590 591static void r600_set_scissor_state(struct pipe_context *ctx, 592 const struct pipe_scissor_state *state) 593{ 594 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 595 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 596 u32 tl, br; 597 598 if (rstate == NULL) 599 return; 600 601 rstate->id = R600_PIPE_STATE_SCISSOR; 602 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 603 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 604 r600_pipe_state_add_reg(rstate, 605 R_028210_PA_SC_CLIPRECT_0_TL, tl, 606 0xFFFFFFFF, NULL); 607 r600_pipe_state_add_reg(rstate, 608 R_028214_PA_SC_CLIPRECT_0_BR, br, 609 0xFFFFFFFF, NULL); 610 r600_pipe_state_add_reg(rstate, 611 R_028218_PA_SC_CLIPRECT_1_TL, tl, 612 0xFFFFFFFF, NULL); 613 r600_pipe_state_add_reg(rstate, 614 R_02821C_PA_SC_CLIPRECT_1_BR, br, 615 0xFFFFFFFF, NULL); 616 r600_pipe_state_add_reg(rstate, 617 R_028220_PA_SC_CLIPRECT_2_TL, tl, 618 0xFFFFFFFF, NULL); 619 r600_pipe_state_add_reg(rstate, 620 R_028224_PA_SC_CLIPRECT_2_BR, br, 621 0xFFFFFFFF, NULL); 622 r600_pipe_state_add_reg(rstate, 623 R_028228_PA_SC_CLIPRECT_3_TL, tl, 624 0xFFFFFFFF, NULL); 625 r600_pipe_state_add_reg(rstate, 626 R_02822C_PA_SC_CLIPRECT_3_BR, br, 627 0xFFFFFFFF, NULL); 628 629 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 630 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 631 r600_context_pipe_state_set(&rctx->ctx, rstate); 632} 633 634static void r600_set_stencil_ref(struct pipe_context *ctx, 635 const struct pipe_stencil_ref *state) 636{ 637 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 638 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 639 u32 tmp; 640 641 if (rstate == NULL) 642 return; 643 644 rctx->stencil_ref = *state; 645 rstate->id = R600_PIPE_STATE_STENCIL_REF; 646 tmp = S_028430_STENCILREF(state->ref_value[0]); 647 r600_pipe_state_add_reg(rstate, 648 R_028430_DB_STENCILREFMASK, tmp, 649 ~C_028430_STENCILREF, NULL); 650 tmp = S_028434_STENCILREF_BF(state->ref_value[1]); 651 r600_pipe_state_add_reg(rstate, 652 R_028434_DB_STENCILREFMASK_BF, tmp, 653 ~C_028434_STENCILREF_BF, NULL); 654 655 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); 656 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; 657 r600_context_pipe_state_set(&rctx->ctx, rstate); 658} 659 660static void r600_set_viewport_state(struct pipe_context *ctx, 661 const struct pipe_viewport_state *state) 662{ 663 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 664 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 665 666 if (rstate == NULL) 667 return; 668 669 rctx->viewport = *state; 670 rstate->id = R600_PIPE_STATE_VIEWPORT; 671 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL); 672 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL); 673 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL); 674 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL); 675 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL); 676 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL); 677 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL); 678 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL); 679 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL); 680 681 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 682 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 683 r600_context_pipe_state_set(&rctx->ctx, rstate); 684} 685 686static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate, 687 const struct pipe_framebuffer_state *state, int cb) 688{ 689 struct r600_resource_texture *rtex; 690 struct r600_resource *rbuffer; 691 struct r600_surface *surf; 692 unsigned level = state->cbufs[cb]->u.tex.level; 693 unsigned pitch, slice; 694 unsigned color_info; 695 unsigned format, swap, ntype; 696 unsigned offset; 697 const struct util_format_description *desc; 698 struct r600_bo *bo[3]; 699 int i; 700 701 surf = (struct r600_surface *)state->cbufs[cb]; 702 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 703 704 if (rtex->depth && !rtex->is_flushing_texture) { 705 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); 706 rtex = rtex->flushed_depth_texture; 707 } 708 709 rbuffer = &rtex->resource; 710 bo[0] = rbuffer->bo; 711 bo[1] = rbuffer->bo; 712 bo[2] = rbuffer->bo; 713 714 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 715 offset = r600_texture_get_offset(rtex, 716 level, state->cbufs[cb]->u.tex.first_layer); 717 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 718 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; 719 ntype = 0; 720 desc = util_format_description(surf->base.format); 721 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 722 ntype = V_0280A0_NUMBER_SRGB; 723 724 for (i = 0; i < 4; i++) { 725 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 726 break; 727 } 728 } 729 730 format = r600_translate_colorformat(surf->base.format); 731 swap = r600_translate_colorswap(surf->base.format); 732 733 /* disable when gallium grows int textures */ 734 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type) 735 ntype = 4; 736 737 color_info = S_0280A0_FORMAT(format) | 738 S_0280A0_COMP_SWAP(swap) | 739 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) | 740 S_0280A0_BLEND_CLAMP(1) | 741 S_0280A0_NUMBER_TYPE(ntype); 742 743 /* on R600 this can't be set if BLEND_CLAMP isn't set, 744 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */ 745 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 746 desc->channel[i].size < 12) 747 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 748 749 r600_pipe_state_add_reg(rstate, 750 R_028040_CB_COLOR0_BASE + cb * 4, 751 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); 752 r600_pipe_state_add_reg(rstate, 753 R_0280A0_CB_COLOR0_INFO + cb * 4, 754 color_info, 0xFFFFFFFF, bo[0]); 755 r600_pipe_state_add_reg(rstate, 756 R_028060_CB_COLOR0_SIZE + cb * 4, 757 S_028060_PITCH_TILE_MAX(pitch) | 758 S_028060_SLICE_TILE_MAX(slice), 759 0xFFFFFFFF, NULL); 760 r600_pipe_state_add_reg(rstate, 761 R_028080_CB_COLOR0_VIEW + cb * 4, 762 0x00000000, 0xFFFFFFFF, NULL); 763 r600_pipe_state_add_reg(rstate, 764 R_0280E0_CB_COLOR0_FRAG + cb * 4, 765 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]); 766 r600_pipe_state_add_reg(rstate, 767 R_0280C0_CB_COLOR0_TILE + cb * 4, 768 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]); 769 r600_pipe_state_add_reg(rstate, 770 R_028100_CB_COLOR0_MASK + cb * 4, 771 0x00000000, 0xFFFFFFFF, NULL); 772} 773 774static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate, 775 const struct pipe_framebuffer_state *state) 776{ 777 struct r600_resource_texture *rtex; 778 struct r600_resource *rbuffer; 779 struct r600_surface *surf; 780 unsigned level; 781 unsigned pitch, slice, format; 782 unsigned offset; 783 784 if (state->zsbuf == NULL) 785 return; 786 787 level = state->zsbuf->u.tex.level; 788 789 surf = (struct r600_surface *)state->zsbuf; 790 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 791 792 rbuffer = &rtex->resource; 793 794 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 795 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture, 796 level, state->zsbuf->u.tex.first_layer); 797 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 798 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; 799 format = r600_translate_dbformat(state->zsbuf->texture->format); 800 801 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE, 802 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 803 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, 804 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice), 805 0xFFFFFFFF, NULL); 806 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL); 807 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO, 808 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format), 809 0xFFFFFFFF, rbuffer->bo); 810 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, 811 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL); 812} 813 814static void r600_set_framebuffer_state(struct pipe_context *ctx, 815 const struct pipe_framebuffer_state *state) 816{ 817 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 818 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 819 u32 shader_mask, tl, br, shader_control, target_mask; 820 821 if (rstate == NULL) 822 return; 823 824 /* unreference old buffer and reference new one */ 825 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 826 827 util_copy_framebuffer_state(&rctx->framebuffer, state); 828 829 /* build states */ 830 for (int i = 0; i < state->nr_cbufs; i++) { 831 r600_cb(rctx, rstate, state, i); 832 } 833 if (state->zsbuf) { 834 r600_db(rctx, rstate, state); 835 } 836 837 target_mask = 0x00000000; 838 target_mask = 0xFFFFFFFF; 839 shader_mask = 0; 840 shader_control = 0; 841 for (int i = 0; i < state->nr_cbufs; i++) { 842 target_mask ^= 0xf << (i * 4); 843 shader_mask |= 0xf << (i * 4); 844 shader_control |= 1 << i; 845 } 846 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1); 847 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 848 849 r600_pipe_state_add_reg(rstate, 850 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl, 851 0xFFFFFFFF, NULL); 852 r600_pipe_state_add_reg(rstate, 853 R_028034_PA_SC_SCREEN_SCISSOR_BR, br, 854 0xFFFFFFFF, NULL); 855 r600_pipe_state_add_reg(rstate, 856 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, 857 0xFFFFFFFF, NULL); 858 r600_pipe_state_add_reg(rstate, 859 R_028208_PA_SC_WINDOW_SCISSOR_BR, br, 860 0xFFFFFFFF, NULL); 861 r600_pipe_state_add_reg(rstate, 862 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl, 863 0xFFFFFFFF, NULL); 864 r600_pipe_state_add_reg(rstate, 865 R_028244_PA_SC_GENERIC_SCISSOR_BR, br, 866 0xFFFFFFFF, NULL); 867 r600_pipe_state_add_reg(rstate, 868 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, 869 0xFFFFFFFF, NULL); 870 r600_pipe_state_add_reg(rstate, 871 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, 872 0xFFFFFFFF, NULL); 873 r600_pipe_state_add_reg(rstate, 874 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000, 875 0xFFFFFFFF, NULL); 876 if (rctx->family >= CHIP_RV770) { 877 r600_pipe_state_add_reg(rstate, 878 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA, 879 0xFFFFFFFF, NULL); 880 } 881 882 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 883 shader_control, 0xFFFFFFFF, NULL); 884 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK, 885 0x00000000, target_mask, NULL); 886 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, 887 shader_mask, 0xFFFFFFFF, NULL); 888 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 889 0x00000000, 0xFFFFFFFF, NULL); 890 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 891 0x00000000, 0xFFFFFFFF, NULL); 892 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 893 0x00000000, 0xFFFFFFFF, NULL); 894 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL, 895 0x01000000, 0xFFFFFFFF, NULL); 896 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC, 897 0x00000000, 0xFFFFFFFF, NULL); 898 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST, 899 0x000000FF, 0xFFFFFFFF, NULL); 900 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK, 901 0xFFFFFFFF, 0xFFFFFFFF, NULL); 902 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK, 903 0xFFFFFFFF, 0xFFFFFFFF, NULL); 904 905 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 906 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 907 r600_context_pipe_state_set(&rctx->ctx, rstate); 908 909 if (state->zsbuf) { 910 r600_polygon_offset_update(rctx); 911 } 912} 913 914void r600_init_state_functions(struct r600_pipe_context *rctx) 915{ 916 rctx->context.create_blend_state = r600_create_blend_state; 917 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 918 rctx->context.create_fs_state = r600_create_shader_state; 919 rctx->context.create_rasterizer_state = r600_create_rs_state; 920 rctx->context.create_sampler_state = r600_create_sampler_state; 921 rctx->context.create_sampler_view = r600_create_sampler_view; 922 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 923 rctx->context.create_vs_state = r600_create_shader_state; 924 rctx->context.bind_blend_state = r600_bind_blend_state; 925 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state; 926 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler; 927 rctx->context.bind_fs_state = r600_bind_ps_shader; 928 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 929 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 930 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler; 931 rctx->context.bind_vs_state = r600_bind_vs_shader; 932 rctx->context.delete_blend_state = r600_delete_state; 933 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 934 rctx->context.delete_fs_state = r600_delete_ps_shader; 935 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 936 rctx->context.delete_sampler_state = r600_delete_state; 937 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 938 rctx->context.delete_vs_state = r600_delete_vs_shader; 939 rctx->context.set_blend_color = r600_set_blend_color; 940 rctx->context.set_clip_state = r600_set_clip_state; 941 rctx->context.set_constant_buffer = r600_set_constant_buffer; 942 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view; 943 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 944 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 945 rctx->context.set_sample_mask = r600_set_sample_mask; 946 rctx->context.set_scissor_state = r600_set_scissor_state; 947 rctx->context.set_stencil_ref = r600_set_stencil_ref; 948 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 949 rctx->context.set_index_buffer = r600_set_index_buffer; 950 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view; 951 rctx->context.set_viewport_state = r600_set_viewport_state; 952 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 953 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer; 954} 955 956void r600_init_config(struct r600_pipe_context *rctx) 957{ 958 int ps_prio; 959 int vs_prio; 960 int gs_prio; 961 int es_prio; 962 int num_ps_gprs; 963 int num_vs_gprs; 964 int num_gs_gprs; 965 int num_es_gprs; 966 int num_temp_gprs; 967 int num_ps_threads; 968 int num_vs_threads; 969 int num_gs_threads; 970 int num_es_threads; 971 int num_ps_stack_entries; 972 int num_vs_stack_entries; 973 int num_gs_stack_entries; 974 int num_es_stack_entries; 975 enum radeon_family family; 976 struct r600_pipe_state *rstate = &rctx->config; 977 u32 tmp; 978 979 family = r600_get_family(rctx->radeon); 980 ps_prio = 0; 981 vs_prio = 1; 982 gs_prio = 2; 983 es_prio = 3; 984 switch (family) { 985 case CHIP_R600: 986 num_ps_gprs = 192; 987 num_vs_gprs = 56; 988 num_temp_gprs = 4; 989 num_gs_gprs = 0; 990 num_es_gprs = 0; 991 num_ps_threads = 136; 992 num_vs_threads = 48; 993 num_gs_threads = 4; 994 num_es_threads = 4; 995 num_ps_stack_entries = 128; 996 num_vs_stack_entries = 128; 997 num_gs_stack_entries = 0; 998 num_es_stack_entries = 0; 999 break; 1000 case CHIP_RV630: 1001 case CHIP_RV635: 1002 num_ps_gprs = 84; 1003 num_vs_gprs = 36; 1004 num_temp_gprs = 4; 1005 num_gs_gprs = 0; 1006 num_es_gprs = 0; 1007 num_ps_threads = 144; 1008 num_vs_threads = 40; 1009 num_gs_threads = 4; 1010 num_es_threads = 4; 1011 num_ps_stack_entries = 40; 1012 num_vs_stack_entries = 40; 1013 num_gs_stack_entries = 32; 1014 num_es_stack_entries = 16; 1015 break; 1016 case CHIP_RV610: 1017 case CHIP_RV620: 1018 case CHIP_RS780: 1019 case CHIP_RS880: 1020 default: 1021 num_ps_gprs = 84; 1022 num_vs_gprs = 36; 1023 num_temp_gprs = 4; 1024 num_gs_gprs = 0; 1025 num_es_gprs = 0; 1026 num_ps_threads = 136; 1027 num_vs_threads = 48; 1028 num_gs_threads = 4; 1029 num_es_threads = 4; 1030 num_ps_stack_entries = 40; 1031 num_vs_stack_entries = 40; 1032 num_gs_stack_entries = 32; 1033 num_es_stack_entries = 16; 1034 break; 1035 case CHIP_RV670: 1036 num_ps_gprs = 144; 1037 num_vs_gprs = 40; 1038 num_temp_gprs = 4; 1039 num_gs_gprs = 0; 1040 num_es_gprs = 0; 1041 num_ps_threads = 136; 1042 num_vs_threads = 48; 1043 num_gs_threads = 4; 1044 num_es_threads = 4; 1045 num_ps_stack_entries = 40; 1046 num_vs_stack_entries = 40; 1047 num_gs_stack_entries = 32; 1048 num_es_stack_entries = 16; 1049 break; 1050 case CHIP_RV770: 1051 num_ps_gprs = 192; 1052 num_vs_gprs = 56; 1053 num_temp_gprs = 4; 1054 num_gs_gprs = 0; 1055 num_es_gprs = 0; 1056 num_ps_threads = 188; 1057 num_vs_threads = 60; 1058 num_gs_threads = 0; 1059 num_es_threads = 0; 1060 num_ps_stack_entries = 256; 1061 num_vs_stack_entries = 256; 1062 num_gs_stack_entries = 0; 1063 num_es_stack_entries = 0; 1064 break; 1065 case CHIP_RV730: 1066 case CHIP_RV740: 1067 num_ps_gprs = 84; 1068 num_vs_gprs = 36; 1069 num_temp_gprs = 4; 1070 num_gs_gprs = 0; 1071 num_es_gprs = 0; 1072 num_ps_threads = 188; 1073 num_vs_threads = 60; 1074 num_gs_threads = 0; 1075 num_es_threads = 0; 1076 num_ps_stack_entries = 128; 1077 num_vs_stack_entries = 128; 1078 num_gs_stack_entries = 0; 1079 num_es_stack_entries = 0; 1080 break; 1081 case CHIP_RV710: 1082 num_ps_gprs = 192; 1083 num_vs_gprs = 56; 1084 num_temp_gprs = 4; 1085 num_gs_gprs = 0; 1086 num_es_gprs = 0; 1087 num_ps_threads = 144; 1088 num_vs_threads = 48; 1089 num_gs_threads = 0; 1090 num_es_threads = 0; 1091 num_ps_stack_entries = 128; 1092 num_vs_stack_entries = 128; 1093 num_gs_stack_entries = 0; 1094 num_es_stack_entries = 0; 1095 break; 1096 } 1097 1098 rstate->id = R600_PIPE_STATE_CONFIG; 1099 1100 /* SQ_CONFIG */ 1101 tmp = 0; 1102 switch (family) { 1103 case CHIP_RV610: 1104 case CHIP_RV620: 1105 case CHIP_RS780: 1106 case CHIP_RS880: 1107 case CHIP_RV710: 1108 break; 1109 default: 1110 tmp |= S_008C00_VC_ENABLE(1); 1111 break; 1112 } 1113 tmp |= S_008C00_DX9_CONSTS(0); 1114 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 1115 tmp |= S_008C00_PS_PRIO(ps_prio); 1116 tmp |= S_008C00_VS_PRIO(vs_prio); 1117 tmp |= S_008C00_GS_PRIO(gs_prio); 1118 tmp |= S_008C00_ES_PRIO(es_prio); 1119 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL); 1120 1121 /* SQ_GPR_RESOURCE_MGMT_1 */ 1122 tmp = 0; 1123 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1124 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1125 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs); 1126 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1127 1128 /* SQ_GPR_RESOURCE_MGMT_2 */ 1129 tmp = 0; 1130 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs); 1131 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs); 1132 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1133 1134 /* SQ_THREAD_RESOURCE_MGMT */ 1135 tmp = 0; 1136 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads); 1137 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 1138 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 1139 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 1140 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL); 1141 1142 /* SQ_STACK_RESOURCE_MGMT_1 */ 1143 tmp = 0; 1144 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 1145 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 1146 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1147 1148 /* SQ_STACK_RESOURCE_MGMT_2 */ 1149 tmp = 0; 1150 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 1151 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 1152 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1153 1154 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL); 1155 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL); 1156 1157 if (family >= CHIP_RV770) { 1158 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL); 1159 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL); 1160 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL); 1161 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL); 1162 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL); 1163 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL); 1164 } else { 1165 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL); 1166 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL); 1167 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL); 1168 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL); 1169 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL); 1170 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL); 1171 } 1172 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1173 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1174 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1175 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1176 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1177 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1178 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1179 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1180 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL); 1181 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 1182 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 1183 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL); 1184 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL); 1185 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL); 1186 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL); 1187 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL); 1188 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL); 1189 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 1190 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 1191 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 1192 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 1193 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL); 1194 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL); 1195 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL); 1196 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL); 1197 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL); 1198 1199 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL); 1200 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL); 1201 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL); 1202 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL); 1203 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL); 1204 r600_context_pipe_state_set(&rctx->ctx, rstate); 1205} 1206 1207void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx) 1208{ 1209 struct pipe_depth_stencil_alpha_state dsa; 1210 struct r600_pipe_state *rstate; 1211 boolean quirk = false; 1212 1213 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 || 1214 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635) 1215 quirk = true; 1216 1217 memset(&dsa, 0, sizeof(dsa)); 1218 1219 if (quirk) { 1220 dsa.depth.enabled = 1; 1221 dsa.depth.func = PIPE_FUNC_LEQUAL; 1222 dsa.stencil[0].enabled = 1; 1223 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 1224 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 1225 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 1226 dsa.stencil[0].writemask = 0xff; 1227 } 1228 1229 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 1230 r600_pipe_state_add_reg(rstate, 1231 R_02880C_DB_SHADER_CONTROL, 1232 0x0, 1233 S_02880C_DUAL_EXPORT_ENABLE(1), NULL); 1234 r600_pipe_state_add_reg(rstate, 1235 R_028D0C_DB_RENDER_CONTROL, 1236 S_028D0C_DEPTH_COPY_ENABLE(1) | 1237 S_028D0C_STENCIL_COPY_ENABLE(1) | 1238 S_028D0C_COPY_CENTROID(1), 1239 S_028D0C_DEPTH_COPY_ENABLE(1) | 1240 S_028D0C_STENCIL_COPY_ENABLE(1) | 1241 S_028D0C_COPY_CENTROID(1), NULL); 1242 return rstate; 1243} 1244 1245void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx, 1246 struct r600_pipe_state *rstate, 1247 struct r600_resource *rbuffer, 1248 unsigned offset, unsigned stride) 1249{ 1250 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, 1251 offset, 0xFFFFFFFF, rbuffer->bo); 1252 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, 1253 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL); 1254 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, 1255 S_038008_STRIDE(stride), 1256 0xFFFFFFFF, NULL); 1257 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 1258 0x00000000, 0xFFFFFFFF, NULL); 1259 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 1260 0x00000000, 0xFFFFFFFF, NULL); 1261 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 1262 0x00000000, 0xFFFFFFFF, NULL); 1263 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 1264 0xC0000000, 0xFFFFFFFF, NULL); 1265} 1266