r600_state.c revision 330b6c85c961b32f704ce8ec7dbf8cb7fc0b80a8
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_formats.h" 24#include "r600d.h" 25 26#include "pipe/p_shader_tokens.h" 27#include "util/u_pack_color.h" 28#include "util/u_memory.h" 29#include "util/u_framebuffer.h" 30 31static uint32_t r600_translate_blend_function(int blend_func) 32{ 33 switch (blend_func) { 34 case PIPE_BLEND_ADD: 35 return V_028804_COMB_DST_PLUS_SRC; 36 case PIPE_BLEND_SUBTRACT: 37 return V_028804_COMB_SRC_MINUS_DST; 38 case PIPE_BLEND_REVERSE_SUBTRACT: 39 return V_028804_COMB_DST_MINUS_SRC; 40 case PIPE_BLEND_MIN: 41 return V_028804_COMB_MIN_DST_SRC; 42 case PIPE_BLEND_MAX: 43 return V_028804_COMB_MAX_DST_SRC; 44 default: 45 R600_ERR("Unknown blend function %d\n", blend_func); 46 assert(0); 47 break; 48 } 49 return 0; 50} 51 52static uint32_t r600_translate_blend_factor(int blend_fact) 53{ 54 switch (blend_fact) { 55 case PIPE_BLENDFACTOR_ONE: 56 return V_028804_BLEND_ONE; 57 case PIPE_BLENDFACTOR_SRC_COLOR: 58 return V_028804_BLEND_SRC_COLOR; 59 case PIPE_BLENDFACTOR_SRC_ALPHA: 60 return V_028804_BLEND_SRC_ALPHA; 61 case PIPE_BLENDFACTOR_DST_ALPHA: 62 return V_028804_BLEND_DST_ALPHA; 63 case PIPE_BLENDFACTOR_DST_COLOR: 64 return V_028804_BLEND_DST_COLOR; 65 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 66 return V_028804_BLEND_SRC_ALPHA_SATURATE; 67 case PIPE_BLENDFACTOR_CONST_COLOR: 68 return V_028804_BLEND_CONST_COLOR; 69 case PIPE_BLENDFACTOR_CONST_ALPHA: 70 return V_028804_BLEND_CONST_ALPHA; 71 case PIPE_BLENDFACTOR_ZERO: 72 return V_028804_BLEND_ZERO; 73 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 74 return V_028804_BLEND_ONE_MINUS_SRC_COLOR; 75 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 76 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; 77 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 78 return V_028804_BLEND_ONE_MINUS_DST_ALPHA; 79 case PIPE_BLENDFACTOR_INV_DST_COLOR: 80 return V_028804_BLEND_ONE_MINUS_DST_COLOR; 81 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 82 return V_028804_BLEND_ONE_MINUS_CONST_COLOR; 83 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 84 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; 85 case PIPE_BLENDFACTOR_SRC1_COLOR: 86 return V_028804_BLEND_SRC1_COLOR; 87 case PIPE_BLENDFACTOR_SRC1_ALPHA: 88 return V_028804_BLEND_SRC1_ALPHA; 89 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 90 return V_028804_BLEND_INV_SRC1_COLOR; 91 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 92 return V_028804_BLEND_INV_SRC1_ALPHA; 93 default: 94 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 95 assert(0); 96 break; 97 } 98 return 0; 99} 100 101static unsigned r600_tex_dim(unsigned dim) 102{ 103 switch (dim) { 104 default: 105 case PIPE_TEXTURE_1D: 106 return V_038000_SQ_TEX_DIM_1D; 107 case PIPE_TEXTURE_1D_ARRAY: 108 return V_038000_SQ_TEX_DIM_1D_ARRAY; 109 case PIPE_TEXTURE_2D: 110 case PIPE_TEXTURE_RECT: 111 return V_038000_SQ_TEX_DIM_2D; 112 case PIPE_TEXTURE_2D_ARRAY: 113 return V_038000_SQ_TEX_DIM_2D_ARRAY; 114 case PIPE_TEXTURE_3D: 115 return V_038000_SQ_TEX_DIM_3D; 116 case PIPE_TEXTURE_CUBE: 117 return V_038000_SQ_TEX_DIM_CUBEMAP; 118 } 119} 120 121static uint32_t r600_translate_dbformat(enum pipe_format format) 122{ 123 switch (format) { 124 case PIPE_FORMAT_Z16_UNORM: 125 return V_028010_DEPTH_16; 126 case PIPE_FORMAT_Z24X8_UNORM: 127 return V_028010_DEPTH_X8_24; 128 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 129 return V_028010_DEPTH_8_24; 130 case PIPE_FORMAT_Z32_FLOAT: 131 return V_028010_DEPTH_32_FLOAT; 132 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 133 return V_028010_DEPTH_X24_8_32_FLOAT; 134 default: 135 return ~0U; 136 } 137} 138 139static uint32_t r600_translate_colorswap(enum pipe_format format) 140{ 141 switch (format) { 142 /* 8-bit buffers. */ 143 case PIPE_FORMAT_A8_UNORM: 144 case PIPE_FORMAT_A8_SNORM: 145 case PIPE_FORMAT_A8_UINT: 146 case PIPE_FORMAT_A8_SINT: 147 case PIPE_FORMAT_A16_UNORM: 148 case PIPE_FORMAT_A16_SNORM: 149 case PIPE_FORMAT_A16_UINT: 150 case PIPE_FORMAT_A16_SINT: 151 case PIPE_FORMAT_A16_FLOAT: 152 case PIPE_FORMAT_A32_UINT: 153 case PIPE_FORMAT_A32_SINT: 154 case PIPE_FORMAT_A32_FLOAT: 155 case PIPE_FORMAT_R4A4_UNORM: 156 return V_0280A0_SWAP_ALT_REV; 157 case PIPE_FORMAT_I8_UNORM: 158 case PIPE_FORMAT_I8_SNORM: 159 case PIPE_FORMAT_I8_UINT: 160 case PIPE_FORMAT_I8_SINT: 161 case PIPE_FORMAT_L8_UNORM: 162 case PIPE_FORMAT_L8_SNORM: 163 case PIPE_FORMAT_L8_UINT: 164 case PIPE_FORMAT_L8_SINT: 165 case PIPE_FORMAT_L8_SRGB: 166 case PIPE_FORMAT_L16_UNORM: 167 case PIPE_FORMAT_L16_SNORM: 168 case PIPE_FORMAT_L16_UINT: 169 case PIPE_FORMAT_L16_SINT: 170 case PIPE_FORMAT_L16_FLOAT: 171 case PIPE_FORMAT_L32_UINT: 172 case PIPE_FORMAT_L32_SINT: 173 case PIPE_FORMAT_L32_FLOAT: 174 case PIPE_FORMAT_I16_UNORM: 175 case PIPE_FORMAT_I16_SNORM: 176 case PIPE_FORMAT_I16_UINT: 177 case PIPE_FORMAT_I16_SINT: 178 case PIPE_FORMAT_I16_FLOAT: 179 case PIPE_FORMAT_I32_UINT: 180 case PIPE_FORMAT_I32_SINT: 181 case PIPE_FORMAT_I32_FLOAT: 182 case PIPE_FORMAT_R8_UNORM: 183 case PIPE_FORMAT_R8_SNORM: 184 case PIPE_FORMAT_R8_UINT: 185 case PIPE_FORMAT_R8_SINT: 186 return V_0280A0_SWAP_STD; 187 188 case PIPE_FORMAT_L4A4_UNORM: 189 case PIPE_FORMAT_A4R4_UNORM: 190 return V_0280A0_SWAP_ALT; 191 192 /* 16-bit buffers. */ 193 case PIPE_FORMAT_B5G6R5_UNORM: 194 return V_0280A0_SWAP_STD_REV; 195 196 case PIPE_FORMAT_B5G5R5A1_UNORM: 197 case PIPE_FORMAT_B5G5R5X1_UNORM: 198 return V_0280A0_SWAP_ALT; 199 200 case PIPE_FORMAT_B4G4R4A4_UNORM: 201 case PIPE_FORMAT_B4G4R4X4_UNORM: 202 return V_0280A0_SWAP_ALT; 203 204 case PIPE_FORMAT_Z16_UNORM: 205 return V_0280A0_SWAP_STD; 206 207 case PIPE_FORMAT_L8A8_UNORM: 208 case PIPE_FORMAT_L8A8_SNORM: 209 case PIPE_FORMAT_L8A8_UINT: 210 case PIPE_FORMAT_L8A8_SINT: 211 case PIPE_FORMAT_L8A8_SRGB: 212 case PIPE_FORMAT_L16A16_UNORM: 213 case PIPE_FORMAT_L16A16_SNORM: 214 case PIPE_FORMAT_L16A16_UINT: 215 case PIPE_FORMAT_L16A16_SINT: 216 case PIPE_FORMAT_L16A16_FLOAT: 217 case PIPE_FORMAT_L32A32_UINT: 218 case PIPE_FORMAT_L32A32_SINT: 219 case PIPE_FORMAT_L32A32_FLOAT: 220 return V_0280A0_SWAP_ALT; 221 case PIPE_FORMAT_R8G8_UNORM: 222 case PIPE_FORMAT_R8G8_SNORM: 223 case PIPE_FORMAT_R8G8_UINT: 224 case PIPE_FORMAT_R8G8_SINT: 225 return V_0280A0_SWAP_STD; 226 227 case PIPE_FORMAT_R16_UNORM: 228 case PIPE_FORMAT_R16_SNORM: 229 case PIPE_FORMAT_R16_UINT: 230 case PIPE_FORMAT_R16_SINT: 231 case PIPE_FORMAT_R16_FLOAT: 232 return V_0280A0_SWAP_STD; 233 234 /* 32-bit buffers. */ 235 236 case PIPE_FORMAT_A8B8G8R8_SRGB: 237 return V_0280A0_SWAP_STD_REV; 238 case PIPE_FORMAT_B8G8R8A8_SRGB: 239 return V_0280A0_SWAP_ALT; 240 241 case PIPE_FORMAT_B8G8R8A8_UNORM: 242 case PIPE_FORMAT_B8G8R8X8_UNORM: 243 return V_0280A0_SWAP_ALT; 244 245 case PIPE_FORMAT_A8R8G8B8_UNORM: 246 case PIPE_FORMAT_X8R8G8B8_UNORM: 247 return V_0280A0_SWAP_ALT_REV; 248 case PIPE_FORMAT_R8G8B8A8_SNORM: 249 case PIPE_FORMAT_R8G8B8A8_UNORM: 250 case PIPE_FORMAT_R8G8B8X8_UNORM: 251 case PIPE_FORMAT_R8G8B8A8_SINT: 252 case PIPE_FORMAT_R8G8B8A8_UINT: 253 return V_0280A0_SWAP_STD; 254 255 case PIPE_FORMAT_A8B8G8R8_UNORM: 256 case PIPE_FORMAT_X8B8G8R8_UNORM: 257 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 258 return V_0280A0_SWAP_STD_REV; 259 260 case PIPE_FORMAT_Z24X8_UNORM: 261 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 262 return V_0280A0_SWAP_STD; 263 264 case PIPE_FORMAT_X8Z24_UNORM: 265 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 266 return V_0280A0_SWAP_STD; 267 268 case PIPE_FORMAT_R10G10B10A2_UNORM: 269 case PIPE_FORMAT_R10G10B10X2_SNORM: 270 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 271 return V_0280A0_SWAP_STD; 272 273 case PIPE_FORMAT_B10G10R10A2_UNORM: 274 case PIPE_FORMAT_B10G10R10A2_UINT: 275 return V_0280A0_SWAP_ALT; 276 277 case PIPE_FORMAT_R11G11B10_FLOAT: 278 case PIPE_FORMAT_R16G16_UNORM: 279 case PIPE_FORMAT_R16G16_SNORM: 280 case PIPE_FORMAT_R16G16_FLOAT: 281 case PIPE_FORMAT_R16G16_UINT: 282 case PIPE_FORMAT_R16G16_SINT: 283 case PIPE_FORMAT_R32_UINT: 284 case PIPE_FORMAT_R32_SINT: 285 case PIPE_FORMAT_R32_FLOAT: 286 case PIPE_FORMAT_Z32_FLOAT: 287 return V_0280A0_SWAP_STD; 288 289 /* 64-bit buffers. */ 290 case PIPE_FORMAT_R32G32_FLOAT: 291 case PIPE_FORMAT_R32G32_UINT: 292 case PIPE_FORMAT_R32G32_SINT: 293 case PIPE_FORMAT_R16G16B16A16_UNORM: 294 case PIPE_FORMAT_R16G16B16A16_SNORM: 295 case PIPE_FORMAT_R16G16B16A16_UINT: 296 case PIPE_FORMAT_R16G16B16A16_SINT: 297 case PIPE_FORMAT_R16G16B16A16_FLOAT: 298 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 299 300 /* 128-bit buffers. */ 301 case PIPE_FORMAT_R32G32B32A32_FLOAT: 302 case PIPE_FORMAT_R32G32B32A32_SNORM: 303 case PIPE_FORMAT_R32G32B32A32_UNORM: 304 case PIPE_FORMAT_R32G32B32A32_SINT: 305 case PIPE_FORMAT_R32G32B32A32_UINT: 306 return V_0280A0_SWAP_STD; 307 default: 308 R600_ERR("unsupported colorswap format %d\n", format); 309 return ~0U; 310 } 311 return ~0U; 312} 313 314static uint32_t r600_translate_colorformat(enum pipe_format format) 315{ 316 switch (format) { 317 case PIPE_FORMAT_L4A4_UNORM: 318 case PIPE_FORMAT_R4A4_UNORM: 319 case PIPE_FORMAT_A4R4_UNORM: 320 return V_0280A0_COLOR_4_4; 321 322 /* 8-bit buffers. */ 323 case PIPE_FORMAT_A8_UNORM: 324 case PIPE_FORMAT_A8_SNORM: 325 case PIPE_FORMAT_A8_UINT: 326 case PIPE_FORMAT_A8_SINT: 327 case PIPE_FORMAT_I8_UNORM: 328 case PIPE_FORMAT_I8_SNORM: 329 case PIPE_FORMAT_I8_UINT: 330 case PIPE_FORMAT_I8_SINT: 331 case PIPE_FORMAT_L8_UNORM: 332 case PIPE_FORMAT_L8_SNORM: 333 case PIPE_FORMAT_L8_UINT: 334 case PIPE_FORMAT_L8_SINT: 335 case PIPE_FORMAT_L8_SRGB: 336 case PIPE_FORMAT_R8_UNORM: 337 case PIPE_FORMAT_R8_SNORM: 338 case PIPE_FORMAT_R8_UINT: 339 case PIPE_FORMAT_R8_SINT: 340 return V_0280A0_COLOR_8; 341 342 /* 16-bit buffers. */ 343 case PIPE_FORMAT_B5G6R5_UNORM: 344 return V_0280A0_COLOR_5_6_5; 345 346 case PIPE_FORMAT_B5G5R5A1_UNORM: 347 case PIPE_FORMAT_B5G5R5X1_UNORM: 348 return V_0280A0_COLOR_1_5_5_5; 349 350 case PIPE_FORMAT_B4G4R4A4_UNORM: 351 case PIPE_FORMAT_B4G4R4X4_UNORM: 352 return V_0280A0_COLOR_4_4_4_4; 353 354 case PIPE_FORMAT_Z16_UNORM: 355 return V_0280A0_COLOR_16; 356 357 case PIPE_FORMAT_L8A8_UNORM: 358 case PIPE_FORMAT_L8A8_SNORM: 359 case PIPE_FORMAT_L8A8_UINT: 360 case PIPE_FORMAT_L8A8_SINT: 361 case PIPE_FORMAT_L8A8_SRGB: 362 case PIPE_FORMAT_R8G8_UNORM: 363 case PIPE_FORMAT_R8G8_SNORM: 364 case PIPE_FORMAT_R8G8_UINT: 365 case PIPE_FORMAT_R8G8_SINT: 366 return V_0280A0_COLOR_8_8; 367 368 case PIPE_FORMAT_R16_UNORM: 369 case PIPE_FORMAT_R16_SNORM: 370 case PIPE_FORMAT_R16_UINT: 371 case PIPE_FORMAT_R16_SINT: 372 case PIPE_FORMAT_A16_UNORM: 373 case PIPE_FORMAT_A16_SNORM: 374 case PIPE_FORMAT_A16_UINT: 375 case PIPE_FORMAT_A16_SINT: 376 case PIPE_FORMAT_L16_UNORM: 377 case PIPE_FORMAT_L16_SNORM: 378 case PIPE_FORMAT_L16_UINT: 379 case PIPE_FORMAT_L16_SINT: 380 case PIPE_FORMAT_I16_UNORM: 381 case PIPE_FORMAT_I16_SNORM: 382 case PIPE_FORMAT_I16_UINT: 383 case PIPE_FORMAT_I16_SINT: 384 return V_0280A0_COLOR_16; 385 386 case PIPE_FORMAT_R16_FLOAT: 387 case PIPE_FORMAT_A16_FLOAT: 388 case PIPE_FORMAT_L16_FLOAT: 389 case PIPE_FORMAT_I16_FLOAT: 390 return V_0280A0_COLOR_16_FLOAT; 391 392 /* 32-bit buffers. */ 393 case PIPE_FORMAT_A8B8G8R8_SRGB: 394 case PIPE_FORMAT_A8B8G8R8_UNORM: 395 case PIPE_FORMAT_A8R8G8B8_UNORM: 396 case PIPE_FORMAT_B8G8R8A8_SRGB: 397 case PIPE_FORMAT_B8G8R8A8_UNORM: 398 case PIPE_FORMAT_B8G8R8X8_UNORM: 399 case PIPE_FORMAT_R8G8B8A8_SNORM: 400 case PIPE_FORMAT_R8G8B8A8_UNORM: 401 case PIPE_FORMAT_R8G8B8X8_UNORM: 402 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 403 case PIPE_FORMAT_X8B8G8R8_UNORM: 404 case PIPE_FORMAT_X8R8G8B8_UNORM: 405 case PIPE_FORMAT_R8G8B8_UNORM: 406 case PIPE_FORMAT_R8G8B8A8_SINT: 407 case PIPE_FORMAT_R8G8B8A8_UINT: 408 return V_0280A0_COLOR_8_8_8_8; 409 410 case PIPE_FORMAT_R10G10B10A2_UNORM: 411 case PIPE_FORMAT_R10G10B10X2_SNORM: 412 case PIPE_FORMAT_B10G10R10A2_UNORM: 413 case PIPE_FORMAT_B10G10R10A2_UINT: 414 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 415 return V_0280A0_COLOR_2_10_10_10; 416 417 case PIPE_FORMAT_Z24X8_UNORM: 418 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 419 return V_0280A0_COLOR_8_24; 420 421 case PIPE_FORMAT_X8Z24_UNORM: 422 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 423 return V_0280A0_COLOR_24_8; 424 425 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 426 return V_0280A0_COLOR_X24_8_32_FLOAT; 427 428 case PIPE_FORMAT_R32_UINT: 429 case PIPE_FORMAT_R32_SINT: 430 case PIPE_FORMAT_A32_UINT: 431 case PIPE_FORMAT_A32_SINT: 432 case PIPE_FORMAT_L32_UINT: 433 case PIPE_FORMAT_L32_SINT: 434 case PIPE_FORMAT_I32_UINT: 435 case PIPE_FORMAT_I32_SINT: 436 return V_0280A0_COLOR_32; 437 438 case PIPE_FORMAT_R32_FLOAT: 439 case PIPE_FORMAT_A32_FLOAT: 440 case PIPE_FORMAT_L32_FLOAT: 441 case PIPE_FORMAT_I32_FLOAT: 442 case PIPE_FORMAT_Z32_FLOAT: 443 return V_0280A0_COLOR_32_FLOAT; 444 445 case PIPE_FORMAT_R16G16_FLOAT: 446 case PIPE_FORMAT_L16A16_FLOAT: 447 return V_0280A0_COLOR_16_16_FLOAT; 448 449 case PIPE_FORMAT_R16G16_UNORM: 450 case PIPE_FORMAT_R16G16_SNORM: 451 case PIPE_FORMAT_R16G16_UINT: 452 case PIPE_FORMAT_R16G16_SINT: 453 case PIPE_FORMAT_L16A16_UNORM: 454 case PIPE_FORMAT_L16A16_SNORM: 455 case PIPE_FORMAT_L16A16_UINT: 456 case PIPE_FORMAT_L16A16_SINT: 457 return V_0280A0_COLOR_16_16; 458 459 case PIPE_FORMAT_R11G11B10_FLOAT: 460 return V_0280A0_COLOR_10_11_11_FLOAT; 461 462 /* 64-bit buffers. */ 463 case PIPE_FORMAT_R16G16B16A16_UINT: 464 case PIPE_FORMAT_R16G16B16A16_SINT: 465 case PIPE_FORMAT_R16G16B16A16_UNORM: 466 case PIPE_FORMAT_R16G16B16A16_SNORM: 467 return V_0280A0_COLOR_16_16_16_16; 468 469 case PIPE_FORMAT_R16G16B16_FLOAT: 470 case PIPE_FORMAT_R16G16B16A16_FLOAT: 471 return V_0280A0_COLOR_16_16_16_16_FLOAT; 472 473 case PIPE_FORMAT_R32G32_FLOAT: 474 case PIPE_FORMAT_L32A32_FLOAT: 475 return V_0280A0_COLOR_32_32_FLOAT; 476 477 case PIPE_FORMAT_R32G32_SINT: 478 case PIPE_FORMAT_R32G32_UINT: 479 case PIPE_FORMAT_L32A32_UINT: 480 case PIPE_FORMAT_L32A32_SINT: 481 return V_0280A0_COLOR_32_32; 482 483 /* 96-bit buffers. */ 484 case PIPE_FORMAT_R32G32B32_FLOAT: 485 return V_0280A0_COLOR_32_32_32_FLOAT; 486 487 /* 128-bit buffers. */ 488 case PIPE_FORMAT_R32G32B32A32_FLOAT: 489 return V_0280A0_COLOR_32_32_32_32_FLOAT; 490 case PIPE_FORMAT_R32G32B32A32_SNORM: 491 case PIPE_FORMAT_R32G32B32A32_UNORM: 492 case PIPE_FORMAT_R32G32B32A32_SINT: 493 case PIPE_FORMAT_R32G32B32A32_UINT: 494 return V_0280A0_COLOR_32_32_32_32; 495 496 /* YUV buffers. */ 497 case PIPE_FORMAT_UYVY: 498 case PIPE_FORMAT_YUYV: 499 default: 500 return ~0U; /* Unsupported. */ 501 } 502} 503 504static uint32_t r600_colorformat_endian_swap(uint32_t colorformat) 505{ 506 if (R600_BIG_ENDIAN) { 507 switch(colorformat) { 508 case V_0280A0_COLOR_4_4: 509 return ENDIAN_NONE; 510 511 /* 8-bit buffers. */ 512 case V_0280A0_COLOR_8: 513 return ENDIAN_NONE; 514 515 /* 16-bit buffers. */ 516 case V_0280A0_COLOR_5_6_5: 517 case V_0280A0_COLOR_1_5_5_5: 518 case V_0280A0_COLOR_4_4_4_4: 519 case V_0280A0_COLOR_16: 520 case V_0280A0_COLOR_8_8: 521 return ENDIAN_8IN16; 522 523 /* 32-bit buffers. */ 524 case V_0280A0_COLOR_8_8_8_8: 525 case V_0280A0_COLOR_2_10_10_10: 526 case V_0280A0_COLOR_8_24: 527 case V_0280A0_COLOR_24_8: 528 case V_0280A0_COLOR_32_FLOAT: 529 case V_0280A0_COLOR_16_16_FLOAT: 530 case V_0280A0_COLOR_16_16: 531 return ENDIAN_8IN32; 532 533 /* 64-bit buffers. */ 534 case V_0280A0_COLOR_16_16_16_16: 535 case V_0280A0_COLOR_16_16_16_16_FLOAT: 536 return ENDIAN_8IN16; 537 538 case V_0280A0_COLOR_32_32_FLOAT: 539 case V_0280A0_COLOR_32_32: 540 case V_0280A0_COLOR_X24_8_32_FLOAT: 541 return ENDIAN_8IN32; 542 543 /* 128-bit buffers. */ 544 case V_0280A0_COLOR_32_32_32_FLOAT: 545 case V_0280A0_COLOR_32_32_32_32_FLOAT: 546 case V_0280A0_COLOR_32_32_32_32: 547 return ENDIAN_8IN32; 548 default: 549 return ENDIAN_NONE; /* Unsupported. */ 550 } 551 } else { 552 return ENDIAN_NONE; 553 } 554} 555 556static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 557{ 558 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; 559} 560 561static bool r600_is_colorbuffer_format_supported(enum pipe_format format) 562{ 563 return r600_translate_colorformat(format) != ~0U && 564 r600_translate_colorswap(format) != ~0U; 565} 566 567static bool r600_is_zs_format_supported(enum pipe_format format) 568{ 569 return r600_translate_dbformat(format) != ~0U; 570} 571 572boolean r600_is_format_supported(struct pipe_screen *screen, 573 enum pipe_format format, 574 enum pipe_texture_target target, 575 unsigned sample_count, 576 unsigned usage) 577{ 578 unsigned retval = 0; 579 580 if (target >= PIPE_MAX_TEXTURE_TYPES) { 581 R600_ERR("r600: unsupported texture type %d\n", target); 582 return FALSE; 583 } 584 585 if (!util_format_is_supported(format, usage)) 586 return FALSE; 587 588 /* Multisample */ 589 if (sample_count > 1) 590 return FALSE; 591 592 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 593 r600_is_sampler_format_supported(screen, format)) { 594 retval |= PIPE_BIND_SAMPLER_VIEW; 595 } 596 597 if ((usage & (PIPE_BIND_RENDER_TARGET | 598 PIPE_BIND_DISPLAY_TARGET | 599 PIPE_BIND_SCANOUT | 600 PIPE_BIND_SHARED)) && 601 r600_is_colorbuffer_format_supported(format)) { 602 retval |= usage & 603 (PIPE_BIND_RENDER_TARGET | 604 PIPE_BIND_DISPLAY_TARGET | 605 PIPE_BIND_SCANOUT | 606 PIPE_BIND_SHARED); 607 } 608 609 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 610 r600_is_zs_format_supported(format)) { 611 retval |= PIPE_BIND_DEPTH_STENCIL; 612 } 613 614 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 615 r600_is_vertex_format_supported(format)) { 616 retval |= PIPE_BIND_VERTEX_BUFFER; 617 } 618 619 if (usage & PIPE_BIND_TRANSFER_READ) 620 retval |= PIPE_BIND_TRANSFER_READ; 621 if (usage & PIPE_BIND_TRANSFER_WRITE) 622 retval |= PIPE_BIND_TRANSFER_WRITE; 623 624 return retval == usage; 625} 626 627void r600_polygon_offset_update(struct r600_context *rctx) 628{ 629 struct r600_pipe_state state; 630 631 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 632 state.nregs = 0; 633 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 634 float offset_units = rctx->rasterizer->offset_units; 635 unsigned offset_db_fmt_cntl = 0, depth; 636 637 switch (rctx->framebuffer.zsbuf->texture->format) { 638 case PIPE_FORMAT_Z24X8_UNORM: 639 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 640 depth = -24; 641 offset_units *= 2.0f; 642 break; 643 case PIPE_FORMAT_Z32_FLOAT: 644 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 645 depth = -23; 646 offset_units *= 1.0f; 647 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 648 break; 649 case PIPE_FORMAT_Z16_UNORM: 650 depth = -16; 651 offset_units *= 4.0f; 652 break; 653 default: 654 return; 655 } 656 /* XXX some of those reg can be computed with cso */ 657 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 658 r600_pipe_state_add_reg(&state, 659 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 660 fui(rctx->rasterizer->offset_scale), NULL, 0); 661 r600_pipe_state_add_reg(&state, 662 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 663 fui(offset_units), NULL, 0); 664 r600_pipe_state_add_reg(&state, 665 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 666 fui(rctx->rasterizer->offset_scale), NULL, 0); 667 r600_pipe_state_add_reg(&state, 668 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 669 fui(offset_units), NULL, 0); 670 r600_pipe_state_add_reg(&state, 671 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 672 offset_db_fmt_cntl, NULL, 0); 673 r600_context_pipe_state_set(rctx, &state); 674 } 675} 676 677static void *r600_create_blend_state(struct pipe_context *ctx, 678 const struct pipe_blend_state *state) 679{ 680 struct r600_context *rctx = (struct r600_context *)ctx; 681 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 682 struct r600_pipe_state *rstate; 683 uint32_t color_control = 0, target_mask; 684 685 if (blend == NULL) { 686 return NULL; 687 } 688 rstate = &blend->rstate; 689 690 rstate->id = R600_PIPE_STATE_BLEND; 691 692 target_mask = 0; 693 694 /* R600 does not support per-MRT blends */ 695 if (rctx->family > CHIP_R600) 696 color_control |= S_028808_PER_MRT_BLEND(1); 697 if (state->logicop_enable) { 698 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 699 } else { 700 color_control |= (0xcc << 16); 701 } 702 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 703 if (state->independent_blend_enable) { 704 for (int i = 0; i < 8; i++) { 705 if (state->rt[i].blend_enable) { 706 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 707 } 708 target_mask |= (state->rt[i].colormask << (4 * i)); 709 } 710 } else { 711 for (int i = 0; i < 8; i++) { 712 if (state->rt[0].blend_enable) { 713 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 714 } 715 target_mask |= (state->rt[0].colormask << (4 * i)); 716 } 717 } 718 blend->cb_target_mask = target_mask; 719 blend->cb_color_control = color_control; 720 721 for (int i = 0; i < 8; i++) { 722 /* state->rt entries > 0 only written if independent blending */ 723 const int j = state->independent_blend_enable ? i : 0; 724 725 unsigned eqRGB = state->rt[j].rgb_func; 726 unsigned srcRGB = state->rt[j].rgb_src_factor; 727 unsigned dstRGB = state->rt[j].rgb_dst_factor; 728 729 unsigned eqA = state->rt[j].alpha_func; 730 unsigned srcA = state->rt[j].alpha_src_factor; 731 unsigned dstA = state->rt[j].alpha_dst_factor; 732 uint32_t bc = 0; 733 734 if (!state->rt[j].blend_enable) 735 continue; 736 737 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 738 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 739 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 740 741 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 742 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 743 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 744 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 745 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 746 } 747 748 /* R600 does not support per-MRT blends */ 749 if (rctx->family > CHIP_R600) 750 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, NULL, 0); 751 if (i == 0) 752 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, NULL, 0); 753 } 754 return rstate; 755} 756 757static void *r600_create_dsa_state(struct pipe_context *ctx, 758 const struct pipe_depth_stencil_alpha_state *state) 759{ 760 struct r600_context *rctx = (struct r600_context *)ctx; 761 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); 762 unsigned db_depth_control, alpha_test_control, alpha_ref; 763 struct r600_pipe_state *rstate; 764 765 if (dsa == NULL) { 766 return NULL; 767 } 768 769 dsa->valuemask[0] = state->stencil[0].valuemask; 770 dsa->valuemask[1] = state->stencil[1].valuemask; 771 dsa->writemask[0] = state->stencil[0].writemask; 772 dsa->writemask[1] = state->stencil[1].writemask; 773 774 rstate = &dsa->rstate; 775 776 rstate->id = R600_PIPE_STATE_DSA; 777 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 778 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 779 S_028800_ZFUNC(state->depth.func); 780 781 /* stencil */ 782 if (state->stencil[0].enabled) { 783 db_depth_control |= S_028800_STENCIL_ENABLE(1); 784 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 785 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 786 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 787 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 788 789 if (state->stencil[1].enabled) { 790 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 791 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 792 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 793 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 794 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 795 } 796 } 797 798 /* alpha */ 799 alpha_test_control = 0; 800 alpha_ref = 0; 801 if (state->alpha.enabled) { 802 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 803 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 804 alpha_ref = fui(state->alpha.ref_value); 805 } 806 dsa->alpha_ref = alpha_ref; 807 808 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0); 809 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0); 810 return rstate; 811} 812 813static void *r600_create_rs_state(struct pipe_context *ctx, 814 const struct pipe_rasterizer_state *state) 815{ 816 struct r600_context *rctx = (struct r600_context *)ctx; 817 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 818 struct r600_pipe_state *rstate; 819 unsigned tmp; 820 unsigned prov_vtx = 1, polygon_dual_mode; 821 unsigned sc_mode_cntl; 822 float psize_min, psize_max; 823 824 if (rs == NULL) { 825 return NULL; 826 } 827 828 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 829 state->fill_back != PIPE_POLYGON_MODE_FILL); 830 831 if (state->flatshade_first) 832 prov_vtx = 0; 833 834 rstate = &rs->rstate; 835 rs->flatshade = state->flatshade; 836 rs->sprite_coord_enable = state->sprite_coord_enable; 837 rs->two_side = state->light_twoside; 838 rs->clip_plane_enable = state->clip_plane_enable; 839 rs->pa_sc_line_stipple = state->line_stipple_enable ? 840 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 841 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 842 rs->pa_cl_clip_cntl = 843 S_028810_PS_UCP_MODE(3) | 844 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 845 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 846 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 847 848 /* offset */ 849 rs->offset_units = state->offset_units; 850 rs->offset_scale = state->offset_scale * 12.0f; 851 852 rstate->id = R600_PIPE_STATE_RASTERIZER; 853 tmp = S_0286D4_FLAT_SHADE_ENA(1); 854 if (state->sprite_coord_enable) { 855 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 856 S_0286D4_PNT_SPRITE_OVRD_X(2) | 857 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 858 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 859 S_0286D4_PNT_SPRITE_OVRD_W(1); 860 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 861 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 862 } 863 } 864 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0); 865 866 /* point size 12.4 fixed point */ 867 /* For rasterizer discard, disable point rendering by forcing the point size to be 0. */ 868 tmp = state->rasterizer_discard ? 0 : r600_pack_float_12p4(state->point_size/2); 869 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0); 870 871 if (state->rasterizer_discard) { 872 /* For rasterizer discard, disable point rendering by forcing the point size to be 0. */ 873 psize_min = 0; 874 psize_max = 0; 875 } else if (state->point_size_per_vertex) { 876 psize_min = util_get_min_point_size(state); 877 psize_max = 8192; 878 } else { 879 /* Force the point size to be as if the vertex output was disabled. */ 880 psize_min = state->point_size; 881 psize_max = state->point_size; 882 } 883 /* Divide by two, because 0.5 = 1 pixel. */ 884 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 885 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 886 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)), 887 NULL, 0); 888 889 /* For rasterizer discard, disable line rendering by forcing the line width to be 0. */ 890 tmp = state->rasterizer_discard ? 0 : r600_pack_float_12p4(state->line_width/2); 891 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0); 892 893 if (rctx->chip_class >= R700) { 894 sc_mode_cntl = 895 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 896 S_028A4C_FORCE_EOV_REZ_ENABLE(1) | 897 S_028A4C_R700_ZMM_LINE_OFFSET(1) | 898 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); 899 } else { 900 sc_mode_cntl = 901 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | 902 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); 903 rs->scissor_enable = state->scissor; 904 } 905 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); 906 907 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl, 908 NULL, 0); 909 910 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 911 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), 912 NULL, 0); 913 914 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0); 915 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 916 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 917 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 918 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 919 S_028814_FACE(!state->front_ccw) | 920 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 921 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 922 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 923 S_028814_POLY_MODE(polygon_dual_mode) | 924 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 925 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 926 NULL, 0); 927 928 r600_pipe_state_add_reg(rstate, R_028034_PA_SC_SCREEN_SCISSOR_BR, 929 state->rasterizer_discard ? 0 : (S_028034_BR_X(8192) | S_028034_BR_Y(8192)), 930 NULL, 0); 931 return rstate; 932} 933 934static void *r600_create_sampler_state(struct pipe_context *ctx, 935 const struct pipe_sampler_state *state) 936{ 937 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 938 struct r600_pipe_state *rstate; 939 union util_color uc; 940 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; 941 942 if (ss == NULL) { 943 return NULL; 944 } 945 946 ss->seamless_cube_map = state->seamless_cube_map; 947 rstate = &ss->rstate; 948 rstate->id = R600_PIPE_STATE_SAMPLER; 949 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 950 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 951 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 952 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 953 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 954 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | 955 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | 956 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 957 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | 958 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 959 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0); 960 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 961 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 962 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 963 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0); 964 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0); 965 if (uc.ui) { 966 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0); 967 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0); 968 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0); 969 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0); 970 } 971 return rstate; 972} 973 974static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 975 struct pipe_resource *texture, 976 const struct pipe_sampler_view *state) 977{ 978 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen; 979 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 980 struct r600_pipe_resource_state *rstate; 981 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 982 unsigned format, endian; 983 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 984 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 985 unsigned width, height, depth, offset_level, last_level; 986 987 if (view == NULL) 988 return NULL; 989 rstate = &view->state; 990 991 /* initialize base object */ 992 view->base = *state; 993 view->base.texture = NULL; 994 pipe_reference(NULL, &texture->reference); 995 view->base.texture = texture; 996 view->base.reference.count = 1; 997 view->base.context = ctx; 998 999 swizzle[0] = state->swizzle_r; 1000 swizzle[1] = state->swizzle_g; 1001 swizzle[2] = state->swizzle_b; 1002 swizzle[3] = state->swizzle_a; 1003 1004 format = r600_translate_texformat(ctx->screen, state->format, 1005 swizzle, 1006 &word4, &yuv_format); 1007 if (format == ~0) { 1008 format = 0; 1009 } 1010 1011 if (tmp->is_depth && !tmp->is_flushing_texture) { 1012 r600_texture_depth_flush(ctx, texture, TRUE); 1013 tmp = tmp->flushed_depth_texture; 1014 } 1015 1016 endian = r600_colorformat_endian_swap(format); 1017 1018 offset_level = state->u.tex.first_level; 1019 last_level = state->u.tex.last_level - offset_level; 1020 if (!rscreen->use_surface_alloc) { 1021 width = u_minify(texture->width0, offset_level); 1022 height = u_minify(texture->height0, offset_level); 1023 depth = u_minify(texture->depth0, offset_level); 1024 1025 pitch = align(tmp->pitch_in_blocks[offset_level] * 1026 util_format_get_blockwidth(state->format), 8); 1027 array_mode = tmp->array_mode[offset_level]; 1028 tile_type = tmp->tile_type; 1029 1030 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1031 height = 1; 1032 depth = texture->array_size; 1033 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1034 depth = texture->array_size; 1035 } 1036 1037 rstate->bo[0] = &tmp->resource; 1038 rstate->bo[1] = &tmp->resource; 1039 rstate->bo_usage[0] = RADEON_USAGE_READ; 1040 rstate->bo_usage[1] = RADEON_USAGE_READ; 1041 1042 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1043 S_038000_TILE_MODE(array_mode) | 1044 S_038000_TILE_TYPE(tile_type) | 1045 S_038000_PITCH((pitch / 8) - 1) | 1046 S_038000_TEX_WIDTH(width - 1)); 1047 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) | 1048 S_038004_TEX_DEPTH(depth - 1) | 1049 S_038004_DATA_FORMAT(format)); 1050 rstate->val[2] = tmp->offset[offset_level] >> 8; 1051 rstate->val[3] = tmp->offset[offset_level+1] >> 8; 1052 rstate->val[4] = (word4 | 1053 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1054 S_038010_REQUEST_SIZE(1) | 1055 S_038010_ENDIAN_SWAP(endian) | 1056 S_038010_BASE_LEVEL(0)); 1057 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) | 1058 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1059 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1060 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1061 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1062 } else { 1063 width = tmp->surface.level[offset_level].npix_x; 1064 height = tmp->surface.level[offset_level].npix_y; 1065 depth = tmp->surface.level[offset_level].npix_z; 1066 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 1067 tile_type = tmp->tile_type; 1068 1069 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1070 height = 1; 1071 depth = texture->array_size; 1072 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1073 depth = texture->array_size; 1074 } 1075 switch (tmp->surface.level[offset_level].mode) { 1076 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1077 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 1078 break; 1079 case RADEON_SURF_MODE_1D: 1080 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 1081 break; 1082 case RADEON_SURF_MODE_2D: 1083 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 1084 break; 1085 case RADEON_SURF_MODE_LINEAR: 1086 default: 1087 array_mode = V_038000_ARRAY_LINEAR_GENERAL; 1088 break; 1089 } 1090 1091 rstate->bo[0] = &tmp->resource; 1092 rstate->bo[1] = &tmp->resource; 1093 rstate->bo_usage[0] = RADEON_USAGE_READ; 1094 rstate->bo_usage[1] = RADEON_USAGE_READ; 1095 1096 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1097 S_038000_TILE_MODE(array_mode) | 1098 S_038000_TILE_TYPE(tile_type) | 1099 S_038000_PITCH((pitch / 8) - 1) | 1100 S_038000_TEX_WIDTH(width - 1)); 1101 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) | 1102 S_038004_TEX_DEPTH(depth - 1) | 1103 S_038004_DATA_FORMAT(format)); 1104 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8; 1105 if (offset_level >= tmp->surface.last_level) { 1106 rstate->val[3] = tmp->surface.level[offset_level].offset >> 8; 1107 } else { 1108 rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8; 1109 } 1110 rstate->val[4] = (word4 | 1111 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1112 S_038010_REQUEST_SIZE(1) | 1113 S_038010_ENDIAN_SWAP(endian) | 1114 S_038010_BASE_LEVEL(0)); 1115 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) | 1116 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1117 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1118 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1119 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1120 } 1121 return &view->base; 1122} 1123 1124static void r600_set_sampler_views(struct r600_context *rctx, 1125 struct r600_textures_info *dst, 1126 unsigned count, 1127 struct pipe_sampler_view **views, 1128 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned)) 1129{ 1130 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views; 1131 unsigned i; 1132 1133 if (count) 1134 r600_inval_texture_cache(rctx); 1135 1136 for (i = 0; i < count; i++) { 1137 if (rviews[i]) { 1138 if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth) 1139 rctx->have_depth_texture = true; 1140 1141 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */ 1142 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1143 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) 1144 dst->samplers_dirty = true; 1145 1146 set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS); 1147 } else { 1148 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS); 1149 } 1150 1151 pipe_sampler_view_reference( 1152 (struct pipe_sampler_view **)&dst->views[i], 1153 views[i]); 1154 } 1155 1156 for (i = count; i < dst->n_views; i++) { 1157 if (dst->views[i]) { 1158 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS); 1159 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL); 1160 } 1161 } 1162 1163 dst->n_views = count; 1164} 1165 1166static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count, 1167 struct pipe_sampler_view **views) 1168{ 1169 struct r600_context *rctx = (struct r600_context *)ctx; 1170 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views, 1171 r600_context_pipe_state_set_vs_resource); 1172} 1173 1174static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count, 1175 struct pipe_sampler_view **views) 1176{ 1177 struct r600_context *rctx = (struct r600_context *)ctx; 1178 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views, 1179 r600_context_pipe_state_set_ps_resource); 1180} 1181 1182static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable) 1183{ 1184 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1185 if (rstate == NULL) 1186 return; 1187 1188 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP; 1189 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 1190 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) | 1191 S_009508_DISABLE_CUBE_ANISO(1) | 1192 S_009508_SYNC_GRADIENT(1) | 1193 S_009508_SYNC_WALKER(1) | 1194 S_009508_SYNC_ALIGNER(1), 1195 NULL, 0); 1196 1197 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]); 1198 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate; 1199 r600_context_pipe_state_set(rctx, rstate); 1200} 1201 1202static void r600_bind_samplers(struct r600_context *rctx, 1203 struct r600_textures_info *dst, 1204 unsigned count, void **states) 1205{ 1206 memcpy(dst->samplers, states, sizeof(void*) * count); 1207 dst->n_samplers = count; 1208 dst->samplers_dirty = true; 1209} 1210 1211static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states) 1212{ 1213 struct r600_context *rctx = (struct r600_context *)ctx; 1214 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states); 1215} 1216 1217static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states) 1218{ 1219 struct r600_context *rctx = (struct r600_context *)ctx; 1220 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states); 1221} 1222 1223static void r600_update_samplers(struct r600_context *rctx, 1224 struct r600_textures_info *tex, 1225 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned)) 1226{ 1227 unsigned i; 1228 1229 if (tex->samplers_dirty) { 1230 int seamless = -1; 1231 for (i = 0; i < tex->n_samplers; i++) { 1232 if (!tex->samplers[i]) 1233 continue; 1234 1235 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable 1236 * filtering between layers. 1237 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */ 1238 if (tex->views[i]) { 1239 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1240 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) { 1241 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1); 1242 tex->is_array_sampler[i] = true; 1243 } else { 1244 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE; 1245 tex->is_array_sampler[i] = false; 1246 } 1247 } 1248 1249 set_sampler(rctx, &tex->samplers[i]->rstate, i); 1250 1251 if (tex->samplers[i]) 1252 seamless = tex->samplers[i]->seamless_cube_map; 1253 } 1254 1255 if (seamless != -1) 1256 r600_set_seamless_cubemap(rctx, seamless); 1257 1258 tex->samplers_dirty = false; 1259 } 1260} 1261 1262void r600_update_sampler_states(struct r600_context *rctx) 1263{ 1264 r600_update_samplers(rctx, &rctx->vs_samplers, 1265 r600_context_pipe_state_set_vs_sampler); 1266 r600_update_samplers(rctx, &rctx->ps_samplers, 1267 r600_context_pipe_state_set_ps_sampler); 1268} 1269 1270static void r600_set_clip_state(struct pipe_context *ctx, 1271 const struct pipe_clip_state *state) 1272{ 1273 struct r600_context *rctx = (struct r600_context *)ctx; 1274 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1275 struct pipe_resource * cbuf; 1276 1277 if (rstate == NULL) 1278 return; 1279 1280 rctx->clip = *state; 1281 rstate->id = R600_PIPE_STATE_CLIP; 1282 for (int i = 0; i < 6; i++) { 1283 r600_pipe_state_add_reg(rstate, 1284 R_028E20_PA_CL_UCP0_X + i * 16, 1285 fui(state->ucp[i][0]), NULL, 0); 1286 r600_pipe_state_add_reg(rstate, 1287 R_028E24_PA_CL_UCP0_Y + i * 16, 1288 fui(state->ucp[i][1]) , NULL, 0); 1289 r600_pipe_state_add_reg(rstate, 1290 R_028E28_PA_CL_UCP0_Z + i * 16, 1291 fui(state->ucp[i][2]), NULL, 0); 1292 r600_pipe_state_add_reg(rstate, 1293 R_028E2C_PA_CL_UCP0_W + i * 16, 1294 fui(state->ucp[i][3]), NULL, 0); 1295 } 1296 1297 free(rctx->states[R600_PIPE_STATE_CLIP]); 1298 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 1299 r600_context_pipe_state_set(rctx, rstate); 1300 1301 cbuf = pipe_user_buffer_create(ctx->screen, 1302 state->ucp, 1303 4*4*8, /* 8*4 floats */ 1304 PIPE_BIND_CONSTANT_BUFFER); 1305 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf); 1306 pipe_resource_reference(&cbuf, NULL); 1307} 1308 1309static void r600_set_polygon_stipple(struct pipe_context *ctx, 1310 const struct pipe_poly_stipple *state) 1311{ 1312} 1313 1314static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 1315{ 1316} 1317 1318void r600_set_scissor_state(struct r600_context *rctx, 1319 const struct pipe_scissor_state *state) 1320{ 1321 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1322 uint32_t tl, br; 1323 1324 if (rstate == NULL) 1325 return; 1326 1327 rstate->id = R600_PIPE_STATE_SCISSOR; 1328 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 1329 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 1330 r600_pipe_state_add_reg(rstate, 1331 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, 1332 NULL, 0); 1333 r600_pipe_state_add_reg(rstate, 1334 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, 1335 NULL, 0); 1336 1337 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 1338 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 1339 r600_context_pipe_state_set(rctx, rstate); 1340} 1341 1342static void r600_pipe_set_scissor_state(struct pipe_context *ctx, 1343 const struct pipe_scissor_state *state) 1344{ 1345 struct r600_context *rctx = (struct r600_context *)ctx; 1346 1347 if (rctx->chip_class == R600) { 1348 rctx->scissor_state = *state; 1349 1350 if (!rctx->scissor_enable) 1351 return; 1352 } 1353 1354 r600_set_scissor_state(rctx, state); 1355} 1356 1357static void r600_set_viewport_state(struct pipe_context *ctx, 1358 const struct pipe_viewport_state *state) 1359{ 1360 struct r600_context *rctx = (struct r600_context *)ctx; 1361 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1362 1363 if (rstate == NULL) 1364 return; 1365 1366 rctx->viewport = *state; 1367 rstate->id = R600_PIPE_STATE_VIEWPORT; 1368 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0); 1369 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0); 1370 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0); 1371 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0); 1372 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0); 1373 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0); 1374 1375 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 1376 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 1377 r600_context_pipe_state_set(rctx, rstate); 1378} 1379 1380static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate, 1381 const struct pipe_framebuffer_state *state, int cb) 1382{ 1383 struct r600_screen *rscreen = rctx->screen; 1384 struct r600_resource_texture *rtex; 1385 struct r600_surface *surf; 1386 unsigned level = state->cbufs[cb]->u.tex.level; 1387 unsigned pitch, slice; 1388 unsigned color_info; 1389 unsigned format, swap, ntype, endian; 1390 unsigned offset; 1391 const struct util_format_description *desc; 1392 int i; 1393 unsigned blend_bypass = 0, blend_clamp = 1; 1394 1395 surf = (struct r600_surface *)state->cbufs[cb]; 1396 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 1397 1398 if (rtex->is_depth) 1399 rctx->have_depth_fb = TRUE; 1400 1401 if (rtex->is_depth && !rtex->is_flushing_texture) { 1402 rtex = rtex->flushed_depth_texture; 1403 } 1404 1405 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 1406 if (!rscreen->use_surface_alloc) { 1407 offset = r600_texture_get_offset(rtex, 1408 level, state->cbufs[cb]->u.tex.first_layer); 1409 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 1410 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64; 1411 if (slice) { 1412 slice = slice - 1; 1413 } 1414 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]); 1415 } else { 1416 offset = rtex->surface.level[level].offset; 1417 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1418 offset += rtex->surface.level[level].slice_size * 1419 state->cbufs[cb]->u.tex.first_layer; 1420 } 1421 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1422 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1423 if (slice) { 1424 slice = slice - 1; 1425 } 1426 color_info = 0; 1427 switch (rtex->surface.level[level].mode) { 1428 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1429 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); 1430 break; 1431 case RADEON_SURF_MODE_1D: 1432 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1433 break; 1434 case RADEON_SURF_MODE_2D: 1435 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1436 break; 1437 case RADEON_SURF_MODE_LINEAR: 1438 default: 1439 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); 1440 break; 1441 } 1442 } 1443 desc = util_format_description(surf->base.format); 1444 1445 for (i = 0; i < 4; i++) { 1446 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1447 break; 1448 } 1449 } 1450 1451 ntype = V_0280A0_NUMBER_UNORM; 1452 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1453 ntype = V_0280A0_NUMBER_SRGB; 1454 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1455 if (desc->channel[i].normalized) 1456 ntype = V_0280A0_NUMBER_SNORM; 1457 else if (desc->channel[i].pure_integer) 1458 ntype = V_0280A0_NUMBER_SINT; 1459 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1460 if (desc->channel[i].normalized) 1461 ntype = V_0280A0_NUMBER_UNORM; 1462 else if (desc->channel[i].pure_integer) 1463 ntype = V_0280A0_NUMBER_UINT; 1464 } 1465 1466 format = r600_translate_colorformat(surf->base.format); 1467 swap = r600_translate_colorswap(surf->base.format); 1468 if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) { 1469 endian = ENDIAN_NONE; 1470 } else { 1471 endian = r600_colorformat_endian_swap(format); 1472 } 1473 1474 /* set blend bypass according to docs if SINT/UINT or 1475 8/24 COLOR variants */ 1476 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || 1477 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || 1478 format == V_0280A0_COLOR_X24_8_32_FLOAT) { 1479 blend_clamp = 0; 1480 blend_bypass = 1; 1481 } 1482 1483 color_info |= S_0280A0_FORMAT(format) | 1484 S_0280A0_COMP_SWAP(swap) | 1485 S_0280A0_BLEND_BYPASS(blend_bypass) | 1486 S_0280A0_BLEND_CLAMP(blend_clamp) | 1487 S_0280A0_NUMBER_TYPE(ntype) | 1488 S_0280A0_ENDIAN(endian); 1489 1490 /* EXPORT_NORM is an optimzation that can be enabled for better 1491 * performance in certain cases 1492 */ 1493 if (rctx->chip_class == R600) { 1494 /* EXPORT_NORM can be enabled if: 1495 * - 11-bit or smaller UNORM/SNORM/SRGB 1496 * - BLEND_CLAMP is enabled 1497 * - BLEND_FLOAT32 is disabled 1498 */ 1499 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1500 (desc->channel[i].size < 12 && 1501 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1502 ntype != V_0280A0_NUMBER_UINT && 1503 ntype != V_0280A0_NUMBER_SINT) && 1504 G_0280A0_BLEND_CLAMP(color_info) && 1505 !G_0280A0_BLEND_FLOAT32(color_info)) 1506 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1507 } else { 1508 /* EXPORT_NORM can be enabled if: 1509 * - 11-bit or smaller UNORM/SNORM/SRGB 1510 * - 16-bit or smaller FLOAT 1511 */ 1512 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1513 ((desc->channel[i].size < 12 && 1514 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1515 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || 1516 (desc->channel[i].size < 17 && 1517 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) 1518 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1519 } 1520 1521 r600_pipe_state_add_reg(rstate, 1522 R_028040_CB_COLOR0_BASE + cb * 4, 1523 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE); 1524 r600_pipe_state_add_reg(rstate, 1525 R_0280A0_CB_COLOR0_INFO + cb * 4, 1526 color_info, &rtex->resource, RADEON_USAGE_READWRITE); 1527 r600_pipe_state_add_reg(rstate, 1528 R_028060_CB_COLOR0_SIZE + cb * 4, 1529 S_028060_PITCH_TILE_MAX(pitch) | 1530 S_028060_SLICE_TILE_MAX(slice), 1531 NULL, 0); 1532 if (!rscreen->use_surface_alloc) { 1533 r600_pipe_state_add_reg(rstate, 1534 R_028080_CB_COLOR0_VIEW + cb * 4, 1535 0x00000000, NULL, 0); 1536 } else { 1537 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1538 r600_pipe_state_add_reg(rstate, 1539 R_028080_CB_COLOR0_VIEW + cb * 4, 1540 0x00000000, NULL, 0); 1541 } else { 1542 r600_pipe_state_add_reg(rstate, 1543 R_028080_CB_COLOR0_VIEW + cb * 4, 1544 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1545 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer), 1546 NULL, 0); 1547 } 1548 } 1549 r600_pipe_state_add_reg(rstate, 1550 R_0280E0_CB_COLOR0_FRAG + cb * 4, 1551 0, &rtex->resource, RADEON_USAGE_READWRITE); 1552 r600_pipe_state_add_reg(rstate, 1553 R_0280C0_CB_COLOR0_TILE + cb * 4, 1554 0, &rtex->resource, RADEON_USAGE_READWRITE); 1555} 1556 1557static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate, 1558 const struct pipe_framebuffer_state *state) 1559{ 1560 struct r600_screen *rscreen = rctx->screen; 1561 struct r600_resource_texture *rtex; 1562 struct r600_surface *surf; 1563 unsigned level, pitch, slice, format, offset, array_mode; 1564 1565 if (state->zsbuf == NULL) 1566 return; 1567 1568 level = state->zsbuf->u.tex.level; 1569 1570 surf = (struct r600_surface *)state->zsbuf; 1571 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 1572 1573 if (!rscreen->use_surface_alloc) { 1574 /* XXX remove this once tiling is properly supported */ 1575 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] : 1576 V_0280A0_ARRAY_1D_TILED_THIN1; 1577 1578 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 1579 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture, 1580 level, state->zsbuf->u.tex.first_layer); 1581 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 1582 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64; 1583 if (slice) { 1584 slice = slice - 1; 1585 } 1586 } else { 1587 offset = rtex->surface.level[level].offset; 1588 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1589 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1590 if (slice) { 1591 slice = slice - 1; 1592 } 1593 switch (rtex->surface.level[level].mode) { 1594 case RADEON_SURF_MODE_2D: 1595 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1596 break; 1597 case RADEON_SURF_MODE_1D: 1598 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1599 case RADEON_SURF_MODE_LINEAR: 1600 default: 1601 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1602 break; 1603 } 1604 } 1605 1606 format = r600_translate_dbformat(state->zsbuf->texture->format); 1607 1608 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE, 1609 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE); 1610 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, 1611 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice), 1612 NULL, 0); 1613 if (!rscreen->use_surface_alloc) { 1614 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, NULL, 0); 1615 } else { 1616 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 1617 S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) | 1618 S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer), 1619 NULL, 0); 1620 } 1621 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO, 1622 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format), 1623 &rtex->resource, RADEON_USAGE_READWRITE); 1624 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, 1625 (surf->aligned_height / 8) - 1, NULL, 0); 1626} 1627 1628static void r600_set_framebuffer_state(struct pipe_context *ctx, 1629 const struct pipe_framebuffer_state *state) 1630{ 1631 struct r600_context *rctx = (struct r600_context *)ctx; 1632 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1633 uint32_t shader_mask, tl, br, shader_control; 1634 1635 if (rstate == NULL) 1636 return; 1637 1638 r600_flush_framebuffer(rctx, false); 1639 1640 /* unreference old buffer and reference new one */ 1641 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 1642 1643 util_copy_framebuffer_state(&rctx->framebuffer, state); 1644 1645 /* build states */ 1646 rctx->have_depth_fb = 0; 1647 for (int i = 0; i < state->nr_cbufs; i++) { 1648 r600_cb(rctx, rstate, state, i); 1649 } 1650 if (state->zsbuf) { 1651 r600_db(rctx, rstate, state); 1652 } 1653 1654 shader_mask = 0; 1655 shader_control = 0; 1656 for (int i = 0; i < state->nr_cbufs; i++) { 1657 shader_mask |= 0xf << (i * 4); 1658 shader_control |= 1 << i; 1659 } 1660 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1); 1661 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 1662 1663 r600_pipe_state_add_reg(rstate, 1664 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, 1665 NULL, 0); 1666 r600_pipe_state_add_reg(rstate, 1667 R_028208_PA_SC_WINDOW_SCISSOR_BR, br, 1668 NULL, 0); 1669 1670 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1671 shader_control, NULL, 0); 1672 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, 1673 shader_mask, NULL, 0); 1674 1675 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 1676 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 1677 r600_context_pipe_state_set(rctx, rstate); 1678 1679 if (state->zsbuf) { 1680 r600_polygon_offset_update(rctx); 1681 } 1682} 1683 1684static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1685{ 1686 struct radeon_winsys_cs *cs = rctx->cs; 1687 struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom; 1688 unsigned db_render_control = 0; 1689 unsigned db_render_override = 1690 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | 1691 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 1692 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 1693 1694 if (a->occlusion_query_enabled) { 1695 if (rctx->chip_class >= R700) { 1696 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); 1697 } 1698 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1699 } 1700 if (a->flush_depthstencil_enabled) { 1701 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) | 1702 S_028D0C_STENCIL_COPY_ENABLE(1) | 1703 S_028D0C_COPY_CENTROID(1); 1704 } 1705 1706 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); 1707 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ 1708 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ 1709} 1710 1711void r600_init_state_functions(struct r600_context *rctx) 1712{ 1713 r600_init_atom(&rctx->atom_db_misc_state.atom, r600_emit_db_misc_state, 4, 0); 1714 r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom); 1715 1716 rctx->context.create_blend_state = r600_create_blend_state; 1717 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 1718 rctx->context.create_fs_state = r600_create_shader_state; 1719 rctx->context.create_rasterizer_state = r600_create_rs_state; 1720 rctx->context.create_sampler_state = r600_create_sampler_state; 1721 rctx->context.create_sampler_view = r600_create_sampler_view; 1722 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 1723 rctx->context.create_vs_state = r600_create_shader_state; 1724 rctx->context.bind_blend_state = r600_bind_blend_state; 1725 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 1726 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers; 1727 rctx->context.bind_fs_state = r600_bind_ps_shader; 1728 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 1729 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 1730 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers; 1731 rctx->context.bind_vs_state = r600_bind_vs_shader; 1732 rctx->context.delete_blend_state = r600_delete_state; 1733 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 1734 rctx->context.delete_fs_state = r600_delete_ps_shader; 1735 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 1736 rctx->context.delete_sampler_state = r600_delete_state; 1737 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 1738 rctx->context.delete_vs_state = r600_delete_vs_shader; 1739 rctx->context.set_blend_color = r600_set_blend_color; 1740 rctx->context.set_clip_state = r600_set_clip_state; 1741 rctx->context.set_constant_buffer = r600_set_constant_buffer; 1742 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views; 1743 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 1744 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 1745 rctx->context.set_sample_mask = r600_set_sample_mask; 1746 rctx->context.set_scissor_state = r600_pipe_set_scissor_state; 1747 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; 1748 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 1749 rctx->context.set_index_buffer = r600_set_index_buffer; 1750 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views; 1751 rctx->context.set_viewport_state = r600_set_viewport_state; 1752 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 1753 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer; 1754 rctx->context.texture_barrier = r600_texture_barrier; 1755 rctx->context.create_stream_output_target = r600_create_so_target; 1756 rctx->context.stream_output_target_destroy = r600_so_target_destroy; 1757 rctx->context.set_stream_output_targets = r600_set_so_targets; 1758} 1759 1760void r600_adjust_gprs(struct r600_context *rctx) 1761{ 1762 struct r600_pipe_state rstate; 1763 unsigned num_ps_gprs = rctx->default_ps_gprs; 1764 unsigned num_vs_gprs = rctx->default_vs_gprs; 1765 unsigned tmp; 1766 int diff; 1767 1768 if (rctx->chip_class >= EVERGREEN) 1769 return; 1770 1771 if (!rctx->ps_shader || !rctx->vs_shader) 1772 return; 1773 1774 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs) 1775 { 1776 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs; 1777 num_vs_gprs -= diff; 1778 num_ps_gprs += diff; 1779 } 1780 1781 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs) 1782 { 1783 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs; 1784 num_ps_gprs -= diff; 1785 num_vs_gprs += diff; 1786 } 1787 1788 tmp = 0; 1789 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1790 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1791 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs); 1792 rstate.nregs = 0; 1793 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0); 1794 1795 r600_context_pipe_state_set(rctx, &rstate); 1796} 1797 1798void r600_init_atom_start_cs(struct r600_context *rctx) 1799{ 1800 int ps_prio; 1801 int vs_prio; 1802 int gs_prio; 1803 int es_prio; 1804 int num_ps_gprs; 1805 int num_vs_gprs; 1806 int num_gs_gprs; 1807 int num_es_gprs; 1808 int num_temp_gprs; 1809 int num_ps_threads; 1810 int num_vs_threads; 1811 int num_gs_threads; 1812 int num_es_threads; 1813 int num_ps_stack_entries; 1814 int num_vs_stack_entries; 1815 int num_gs_stack_entries; 1816 int num_es_stack_entries; 1817 enum radeon_family family; 1818 struct r600_command_buffer *cb = &rctx->atom_start_cs; 1819 uint32_t tmp; 1820 unsigned i; 1821 1822 r600_init_command_buffer(cb, 256, EMIT_EARLY); 1823 1824 /* R6xx requires this packet at the start of each command buffer */ 1825 if (rctx->chip_class == R600) { 1826 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); 1827 r600_store_value(cb, 0); 1828 } 1829 /* All asics require this one */ 1830 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 1831 r600_store_value(cb, 0x80000000); 1832 r600_store_value(cb, 0x80000000); 1833 1834 family = rctx->family; 1835 ps_prio = 0; 1836 vs_prio = 1; 1837 gs_prio = 2; 1838 es_prio = 3; 1839 switch (family) { 1840 case CHIP_R600: 1841 num_ps_gprs = 192; 1842 num_vs_gprs = 56; 1843 num_temp_gprs = 4; 1844 num_gs_gprs = 0; 1845 num_es_gprs = 0; 1846 num_ps_threads = 136; 1847 num_vs_threads = 48; 1848 num_gs_threads = 4; 1849 num_es_threads = 4; 1850 num_ps_stack_entries = 128; 1851 num_vs_stack_entries = 128; 1852 num_gs_stack_entries = 0; 1853 num_es_stack_entries = 0; 1854 break; 1855 case CHIP_RV630: 1856 case CHIP_RV635: 1857 num_ps_gprs = 84; 1858 num_vs_gprs = 36; 1859 num_temp_gprs = 4; 1860 num_gs_gprs = 0; 1861 num_es_gprs = 0; 1862 num_ps_threads = 144; 1863 num_vs_threads = 40; 1864 num_gs_threads = 4; 1865 num_es_threads = 4; 1866 num_ps_stack_entries = 40; 1867 num_vs_stack_entries = 40; 1868 num_gs_stack_entries = 32; 1869 num_es_stack_entries = 16; 1870 break; 1871 case CHIP_RV610: 1872 case CHIP_RV620: 1873 case CHIP_RS780: 1874 case CHIP_RS880: 1875 default: 1876 num_ps_gprs = 84; 1877 num_vs_gprs = 36; 1878 num_temp_gprs = 4; 1879 num_gs_gprs = 0; 1880 num_es_gprs = 0; 1881 num_ps_threads = 136; 1882 num_vs_threads = 48; 1883 num_gs_threads = 4; 1884 num_es_threads = 4; 1885 num_ps_stack_entries = 40; 1886 num_vs_stack_entries = 40; 1887 num_gs_stack_entries = 32; 1888 num_es_stack_entries = 16; 1889 break; 1890 case CHIP_RV670: 1891 num_ps_gprs = 144; 1892 num_vs_gprs = 40; 1893 num_temp_gprs = 4; 1894 num_gs_gprs = 0; 1895 num_es_gprs = 0; 1896 num_ps_threads = 136; 1897 num_vs_threads = 48; 1898 num_gs_threads = 4; 1899 num_es_threads = 4; 1900 num_ps_stack_entries = 40; 1901 num_vs_stack_entries = 40; 1902 num_gs_stack_entries = 32; 1903 num_es_stack_entries = 16; 1904 break; 1905 case CHIP_RV770: 1906 num_ps_gprs = 192; 1907 num_vs_gprs = 56; 1908 num_temp_gprs = 4; 1909 num_gs_gprs = 0; 1910 num_es_gprs = 0; 1911 num_ps_threads = 188; 1912 num_vs_threads = 60; 1913 num_gs_threads = 0; 1914 num_es_threads = 0; 1915 num_ps_stack_entries = 256; 1916 num_vs_stack_entries = 256; 1917 num_gs_stack_entries = 0; 1918 num_es_stack_entries = 0; 1919 break; 1920 case CHIP_RV730: 1921 case CHIP_RV740: 1922 num_ps_gprs = 84; 1923 num_vs_gprs = 36; 1924 num_temp_gprs = 4; 1925 num_gs_gprs = 0; 1926 num_es_gprs = 0; 1927 num_ps_threads = 188; 1928 num_vs_threads = 60; 1929 num_gs_threads = 0; 1930 num_es_threads = 0; 1931 num_ps_stack_entries = 128; 1932 num_vs_stack_entries = 128; 1933 num_gs_stack_entries = 0; 1934 num_es_stack_entries = 0; 1935 break; 1936 case CHIP_RV710: 1937 num_ps_gprs = 192; 1938 num_vs_gprs = 56; 1939 num_temp_gprs = 4; 1940 num_gs_gprs = 0; 1941 num_es_gprs = 0; 1942 num_ps_threads = 144; 1943 num_vs_threads = 48; 1944 num_gs_threads = 0; 1945 num_es_threads = 0; 1946 num_ps_stack_entries = 128; 1947 num_vs_stack_entries = 128; 1948 num_gs_stack_entries = 0; 1949 num_es_stack_entries = 0; 1950 break; 1951 } 1952 1953 rctx->default_ps_gprs = num_ps_gprs; 1954 rctx->default_vs_gprs = num_vs_gprs; 1955 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; 1956 1957 /* SQ_CONFIG */ 1958 tmp = 0; 1959 switch (family) { 1960 case CHIP_RV610: 1961 case CHIP_RV620: 1962 case CHIP_RS780: 1963 case CHIP_RS880: 1964 case CHIP_RV710: 1965 break; 1966 default: 1967 tmp |= S_008C00_VC_ENABLE(1); 1968 break; 1969 } 1970 tmp |= S_008C00_DX9_CONSTS(0); 1971 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 1972 tmp |= S_008C00_PS_PRIO(ps_prio); 1973 tmp |= S_008C00_VS_PRIO(vs_prio); 1974 tmp |= S_008C00_GS_PRIO(gs_prio); 1975 tmp |= S_008C00_ES_PRIO(es_prio); 1976 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); 1977 1978 /* SQ_GPR_RESOURCE_MGMT_2 */ 1979 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); 1980 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 1981 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); 1982 r600_store_value(cb, tmp); 1983 1984 /* SQ_THREAD_RESOURCE_MGMT */ 1985 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); 1986 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 1987 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 1988 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 1989 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ 1990 1991 /* SQ_STACK_RESOURCE_MGMT_1 */ 1992 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 1993 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 1994 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ 1995 1996 /* SQ_STACK_RESOURCE_MGMT_2 */ 1997 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 1998 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 1999 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ 2000 2001 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); 2002 2003 r600_store_context_reg(cb, R_028350_SX_MISC, 0); 2004 2005 if (rctx->chip_class >= R700) { 2006 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); 2007 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); 2008 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); 2009 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2010 } else { 2011 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2012 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); 2013 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); 2014 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); 2015 } 2016 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); 2017 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ 2018 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ 2019 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ 2020 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ 2021 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ 2022 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ 2023 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ 2024 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ 2025 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ 2026 2027 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2028 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2029 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2030 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2031 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2032 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2033 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2034 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2035 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2036 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2037 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2038 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2039 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2040 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ 2041 2042 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); 2043 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); 2044 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); 2045 2046 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3); 2047 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */ 2048 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ 2049 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ 2050 2051 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); 2052 2053 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 2054 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 2055 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 2056 2057 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 2058 2059 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2); 2060 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */ 2061 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */ 2062 2063 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); 2064 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ 2065 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ 2066 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ 2067 2068 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2); 2069 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ 2070 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ 2071 2072 r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00); 2073 2074 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 2075 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); 2076 2077 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2); 2078 r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */ 2079 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */ 2080 2081 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6); 2082 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */ 2083 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */ 2084 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */ 2085 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */ 2086 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 2087 r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */ 2088 2089 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2); 2090 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ 2091 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ 2092 2093 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F); 2094 2095 r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8); 2096 for (i = 0; i < 8; i++) { 2097 r600_store_value(cb, 0); 2098 } 2099 2100 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 2101 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 2102 2103 if (rctx->chip_class >= R700) { 2104 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 2105 } 2106 2107 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); 2108 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ 2109 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ 2110 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ 2111 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ 2112 2113 r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF); 2114 2115 r600_store_context_reg(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); 2116 2117 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 2118 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 2119 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 2120 2121 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2); 2122 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ 2123 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ 2124 2125 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); 2126 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0); 2127 2128 if (rctx->chip_class == R700) 2129 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); 2130 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2131 2132 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); 2133 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); 2134} 2135 2136void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2137{ 2138 struct r600_context *rctx = (struct r600_context *)ctx; 2139 struct r600_pipe_state *rstate = &shader->rstate; 2140 struct r600_shader *rshader = &shader->shader; 2141 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 2142 int pos_index = -1, face_index = -1; 2143 unsigned tmp, sid, ufi = 0; 2144 int need_linear = 0; 2145 2146 rstate->nregs = 0; 2147 2148 for (i = 0; i < rshader->ninput; i++) { 2149 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 2150 pos_index = i; 2151 if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 2152 face_index = i; 2153 2154 sid = rshader->input[i].spi_sid; 2155 2156 tmp = S_028644_SEMANTIC(sid); 2157 2158 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 2159 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 2160 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 2161 rctx->rasterizer && rctx->rasterizer->flatshade)) 2162 tmp |= S_028644_FLAT_SHADE(1); 2163 2164 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && 2165 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { 2166 tmp |= S_028644_PT_SPRITE_TEX(1); 2167 } 2168 2169 if (rshader->input[i].centroid) 2170 tmp |= S_028644_SEL_CENTROID(1); 2171 2172 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { 2173 need_linear = 1; 2174 tmp |= S_028644_SEL_LINEAR(1); 2175 } 2176 2177 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 2178 tmp, NULL, 0); 2179 } 2180 2181 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2182 for (i = 0; i < rshader->noutput; i++) { 2183 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 2184 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); 2185 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2186 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1); 2187 } 2188 if (rshader->uses_kill) 2189 db_shader_control |= S_02880C_KILL_ENABLE(1); 2190 2191 exports_ps = 0; 2192 num_cout = 0; 2193 for (i = 0; i < rshader->noutput; i++) { 2194 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 2195 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2196 exports_ps |= 1; 2197 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { 2198 num_cout++; 2199 } 2200 } 2201 exports_ps |= S_028854_EXPORT_COLORS(num_cout); 2202 if (!exports_ps) { 2203 /* always at least export 1 component per pixel */ 2204 exports_ps = 2; 2205 } 2206 2207 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | 2208 S_0286CC_PERSP_GRADIENT_ENA(1)| 2209 S_0286CC_LINEAR_GRADIENT_ENA(need_linear); 2210 spi_input_z = 0; 2211 if (pos_index != -1) { 2212 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | 2213 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 2214 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | 2215 S_0286CC_BARYC_SAMPLE_CNTL(1)); 2216 spi_input_z |= 1; 2217 } 2218 2219 spi_ps_in_control_1 = 0; 2220 if (face_index != -1) { 2221 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 2222 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 2223 } 2224 2225 /* HW bug in original R600 */ 2226 if (rctx->family == CHIP_R600) 2227 ufi = 1; 2228 2229 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, NULL, 0); 2230 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, NULL, 0); 2231 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0); 2232 r600_pipe_state_add_reg(rstate, 2233 R_028840_SQ_PGM_START_PS, 2234 0, shader->bo, RADEON_USAGE_READ); 2235 r600_pipe_state_add_reg(rstate, 2236 R_028850_SQ_PGM_RESOURCES_PS, 2237 S_028850_NUM_GPRS(rshader->bc.ngpr) | 2238 S_028850_STACK_SIZE(rshader->bc.nstack) | 2239 S_028850_UNCACHED_FIRST_INST(ufi), 2240 NULL, 0); 2241 r600_pipe_state_add_reg(rstate, 2242 R_028854_SQ_PGM_EXPORTS_PS, 2243 exports_ps, NULL, 0); 2244 /* only set some bits here, the other bits are set in the dsa state */ 2245 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, 2246 db_shader_control, 2247 NULL, 0); 2248 2249 shader->sprite_coord_enable = rctx->sprite_coord_enable; 2250 if (rctx->rasterizer) 2251 shader->flatshade = rctx->rasterizer->flatshade; 2252} 2253 2254void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2255{ 2256 struct r600_context *rctx = (struct r600_context *)ctx; 2257 struct r600_pipe_state *rstate = &shader->rstate; 2258 struct r600_shader *rshader = &shader->shader; 2259 unsigned spi_vs_out_id[10] = {}; 2260 unsigned i, tmp, nparams = 0; 2261 2262 /* clear previous register */ 2263 rstate->nregs = 0; 2264 2265 for (i = 0; i < rshader->noutput; i++) { 2266 if (rshader->output[i].spi_sid) { 2267 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 2268 spi_vs_out_id[nparams / 4] |= tmp; 2269 nparams++; 2270 } 2271 } 2272 2273 for (i = 0; i < 10; i++) { 2274 r600_pipe_state_add_reg(rstate, 2275 R_028614_SPI_VS_OUT_ID_0 + i * 4, 2276 spi_vs_out_id[i], NULL, 0); 2277 } 2278 2279 /* Certain attributes (position, psize, etc.) don't count as params. 2280 * VS is required to export at least one param and r600_shader_from_tgsi() 2281 * takes care of adding a dummy export. 2282 */ 2283 if (nparams < 1) 2284 nparams = 1; 2285 2286 r600_pipe_state_add_reg(rstate, 2287 R_0286C4_SPI_VS_OUT_CONFIG, 2288 S_0286C4_VS_EXPORT_COUNT(nparams - 1), 2289 NULL, 0); 2290 r600_pipe_state_add_reg(rstate, 2291 R_028868_SQ_PGM_RESOURCES_VS, 2292 S_028868_NUM_GPRS(rshader->bc.ngpr) | 2293 S_028868_STACK_SIZE(rshader->bc.nstack), 2294 NULL, 0); 2295 r600_pipe_state_add_reg(rstate, 2296 R_028858_SQ_PGM_START_VS, 2297 0, shader->bo, RADEON_USAGE_READ); 2298 2299 shader->pa_cl_vs_out_cntl = 2300 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | 2301 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | 2302 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 2303 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size); 2304} 2305 2306void r600_fetch_shader(struct pipe_context *ctx, 2307 struct r600_vertex_element *ve) 2308{ 2309 struct r600_pipe_state *rstate; 2310 struct r600_context *rctx = (struct r600_context *)ctx; 2311 2312 rstate = &ve->rstate; 2313 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 2314 rstate->nregs = 0; 2315 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS, 2316 0, 2317 ve->fetch_shader, RADEON_USAGE_READ); 2318} 2319 2320void *r600_create_db_flush_dsa(struct r600_context *rctx) 2321{ 2322 struct pipe_depth_stencil_alpha_state dsa; 2323 struct r600_pipe_state *rstate; 2324 struct r600_pipe_dsa *dsa_state; 2325 boolean quirk = false; 2326 2327 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 || 2328 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635) 2329 quirk = true; 2330 2331 memset(&dsa, 0, sizeof(dsa)); 2332 2333 if (quirk) { 2334 dsa.depth.enabled = 1; 2335 dsa.depth.func = PIPE_FUNC_LEQUAL; 2336 dsa.stencil[0].enabled = 1; 2337 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 2338 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 2339 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 2340 dsa.stencil[0].writemask = 0xff; 2341 } 2342 2343 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 2344 dsa_state = (struct r600_pipe_dsa*)rstate; 2345 dsa_state->is_flush = true; 2346 return rstate; 2347} 2348 2349void r600_pipe_init_buffer_resource(struct r600_context *rctx, 2350 struct r600_pipe_resource_state *rstate) 2351{ 2352 rstate->id = R600_PIPE_STATE_RESOURCE; 2353 2354 rstate->bo[0] = NULL; 2355 rstate->val[0] = 0; 2356 rstate->val[1] = 0; 2357 rstate->val[2] = 0; 2358 rstate->val[3] = 0; 2359 rstate->val[4] = 0; 2360 rstate->val[5] = 0; 2361 rstate->val[6] = 0xc0000000; 2362} 2363 2364void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate, 2365 struct r600_resource *rbuffer, 2366 unsigned offset, unsigned stride, 2367 enum radeon_bo_usage usage) 2368{ 2369 rstate->val[0] = offset; 2370 rstate->bo[0] = rbuffer; 2371 rstate->bo_usage[0] = usage; 2372 rstate->val[1] = rbuffer->buf->size - offset - 1; 2373 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 2374 S_038008_STRIDE(stride); 2375} 2376