r600_state.c revision b8de7788a4b20c702b06402e2e6eed60467e2522
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#include <stdio.h> 27#include <errno.h> 28#include "util/u_inlines.h" 29#include "util/u_format.h" 30#include "util/u_memory.h" 31#include "r600_screen.h" 32#include "r600_context.h" 33#include "r600_resource.h" 34#include "r600d.h" 35#include "r600_state_inlines.h" 36 37static void *r600_create_blend_state(struct pipe_context *ctx, 38 const struct pipe_blend_state *state) 39{ 40 struct r600_context *rctx = r600_context(ctx); 41 42 return r600_context_state(rctx, pipe_blend_type, state); 43} 44 45static void *r600_create_dsa_state(struct pipe_context *ctx, 46 const struct pipe_depth_stencil_alpha_state *state) 47{ 48 struct r600_context *rctx = r600_context(ctx); 49 50 return r600_context_state(rctx, pipe_dsa_type, state); 51} 52 53static void *r600_create_rs_state(struct pipe_context *ctx, 54 const struct pipe_rasterizer_state *state) 55{ 56 struct r600_context *rctx = r600_context(ctx); 57 58 return r600_context_state(rctx, pipe_rasterizer_type, state); 59} 60 61static void *r600_create_sampler_state(struct pipe_context *ctx, 62 const struct pipe_sampler_state *state) 63{ 64 struct r600_context *rctx = r600_context(ctx); 65 66 return r600_context_state(rctx, pipe_sampler_type, state); 67} 68 69static void r600_sampler_view_destroy(struct pipe_context *ctx, 70 struct pipe_sampler_view *state) 71{ 72 struct r600_context_state *rstate = (struct r600_context_state *)state; 73 74 r600_context_state_decref(rstate); 75} 76 77static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 78 struct pipe_resource *texture, 79 const struct pipe_sampler_view *state) 80{ 81 struct r600_context *rctx = r600_context(ctx); 82 struct r600_context_state *rstate; 83 84 rstate = r600_context_state(rctx, pipe_sampler_type, state); 85 pipe_reference(NULL, &texture->reference); 86 rstate->state.sampler_view.texture = texture; 87 rstate->state.sampler_view.reference.count = 1; 88 rstate->state.sampler_view.context = ctx; 89 return &rstate->state.sampler_view; 90} 91 92static void *r600_create_shader_state(struct pipe_context *ctx, 93 const struct pipe_shader_state *state) 94{ 95 struct r600_context *rctx = r600_context(ctx); 96 97 return r600_context_state(rctx, pipe_shader_type, state); 98} 99 100static void *r600_create_vertex_elements(struct pipe_context *ctx, 101 unsigned count, 102 const struct pipe_vertex_element *elements) 103{ 104 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element); 105 106 assert(count < 32); 107 v->count = count; 108 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element)); 109 v->refcount = 1; 110 return v; 111} 112 113static void r600_bind_state(struct pipe_context *ctx, void *state) 114{ 115 struct r600_context *rctx = r600_context(ctx); 116 struct r600_context_state *rstate = (struct r600_context_state *)state; 117 118 if (state == NULL) 119 return; 120 switch (rstate->type) { 121 case pipe_rasterizer_type: 122 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer); 123 rctx->rasterizer = r600_context_state_incref(rstate); 124 break; 125 case pipe_poly_stipple_type: 126 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple); 127 rctx->poly_stipple = r600_context_state_incref(rstate); 128 break; 129 case pipe_scissor_type: 130 rctx->scissor = r600_context_state_decref(rctx->scissor); 131 rctx->scissor = r600_context_state_incref(rstate); 132 break; 133 case pipe_clip_type: 134 rctx->clip = r600_context_state_decref(rctx->clip); 135 rctx->clip = r600_context_state_incref(rstate); 136 break; 137 case pipe_depth_type: 138 rctx->depth = r600_context_state_decref(rctx->depth); 139 rctx->depth = r600_context_state_incref(rstate); 140 break; 141 case pipe_stencil_type: 142 rctx->stencil = r600_context_state_decref(rctx->stencil); 143 rctx->stencil = r600_context_state_incref(rstate); 144 break; 145 case pipe_alpha_type: 146 rctx->alpha = r600_context_state_decref(rctx->alpha); 147 rctx->alpha = r600_context_state_incref(rstate); 148 break; 149 case pipe_dsa_type: 150 rctx->dsa = r600_context_state_decref(rctx->dsa); 151 rctx->dsa = r600_context_state_incref(rstate); 152 break; 153 case pipe_blend_type: 154 rctx->blend = r600_context_state_decref(rctx->blend); 155 rctx->blend = r600_context_state_incref(rstate); 156 break; 157 case pipe_framebuffer_type: 158 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer); 159 rctx->framebuffer = r600_context_state_incref(rstate); 160 break; 161 case pipe_stencil_ref_type: 162 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref); 163 rctx->stencil_ref = r600_context_state_incref(rstate); 164 break; 165 case pipe_viewport_type: 166 rctx->viewport = r600_context_state_decref(rctx->viewport); 167 rctx->viewport = r600_context_state_incref(rstate); 168 break; 169 case pipe_shader_type: 170 case pipe_sampler_type: 171 case pipe_sampler_view_type: 172 default: 173 R600_ERR("invalid type %d\n", rstate->type); 174 return; 175 } 176} 177 178static void r600_bind_ps_shader(struct pipe_context *ctx, void *state) 179{ 180 struct r600_context *rctx = r600_context(ctx); 181 struct r600_context_state *rstate = (struct r600_context_state *)state; 182 183 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader); 184 rctx->ps_shader = r600_context_state_incref(rstate); 185} 186 187static void r600_bind_vs_shader(struct pipe_context *ctx, void *state) 188{ 189 struct r600_context *rctx = r600_context(ctx); 190 struct r600_context_state *rstate = (struct r600_context_state *)state; 191 192 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader); 193 rctx->vs_shader = r600_context_state_incref(rstate); 194} 195 196static void r600_delete_vertex_element(struct pipe_context *ctx, void *state) 197{ 198 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 199 200 if (v == NULL) 201 return; 202 if (--v->refcount) 203 return; 204 free(v); 205} 206 207static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) 208{ 209 struct r600_context *rctx = r600_context(ctx); 210 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 211 212 r600_delete_vertex_element(ctx, rctx->vertex_elements); 213 rctx->vertex_elements = v; 214 if (v) { 215 v->refcount++; 216 } 217} 218 219static void r600_bind_ps_sampler(struct pipe_context *ctx, 220 unsigned count, void **states) 221{ 222 struct r600_context *rctx = r600_context(ctx); 223 struct r600_context_state *rstate; 224 unsigned i; 225 226 for (i = 0; i < rctx->ps_nsampler; i++) { 227 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]); 228 } 229 for (i = 0; i < count; i++) { 230 rstate = (struct r600_context_state *)states[i]; 231 rctx->ps_sampler[i] = r600_context_state_incref(rstate); 232 } 233 rctx->ps_nsampler = count; 234} 235 236static void r600_bind_vs_sampler(struct pipe_context *ctx, 237 unsigned count, void **states) 238{ 239 struct r600_context *rctx = r600_context(ctx); 240 struct r600_context_state *rstate; 241 unsigned i; 242 243 for (i = 0; i < rctx->vs_nsampler; i++) { 244 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]); 245 } 246 for (i = 0; i < count; i++) { 247 rstate = (struct r600_context_state *)states[i]; 248 rctx->vs_sampler[i] = r600_context_state_incref(rstate); 249 } 250 rctx->vs_nsampler = count; 251} 252 253static void r600_delete_state(struct pipe_context *ctx, void *state) 254{ 255 struct r600_context_state *rstate = (struct r600_context_state *)state; 256 257 r600_context_state_decref(rstate); 258} 259 260static void r600_set_blend_color(struct pipe_context *ctx, 261 const struct pipe_blend_color *color) 262{ 263 struct r600_context *rctx = r600_context(ctx); 264 265 rctx->blend_color = *color; 266} 267 268static void r600_set_clip_state(struct pipe_context *ctx, 269 const struct pipe_clip_state *state) 270{ 271} 272 273static void r600_set_constant_buffer(struct pipe_context *ctx, 274 uint shader, uint index, 275 struct pipe_resource *buffer) 276{ 277 struct r600_screen *rscreen = r600_screen(ctx->screen); 278 struct r600_context *rctx = r600_context(ctx); 279 unsigned nconstant = 0, i, type, id; 280 struct radeon_state rstate; 281 struct pipe_transfer *transfer; 282 u32 *ptr; 283 int r; 284 285 switch (shader) { 286 case PIPE_SHADER_VERTEX: 287 id = R600_VS_CONSTANT; 288 type = R600_VS_CONSTANT_TYPE; 289 break; 290 case PIPE_SHADER_FRAGMENT: 291 id = R600_PS_CONSTANT; 292 type = R600_PS_CONSTANT_TYPE; 293 break; 294 default: 295 R600_ERR("unsupported %d\n", shader); 296 return; 297 } 298 if (buffer && buffer->width0 > 0) { 299 nconstant = buffer->width0 / 16; 300 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer); 301 if (ptr == NULL) 302 return; 303 for (i = 0; i < nconstant; i++) { 304 r = radeon_state_init(&rstate, rscreen->rw, type, id + i); 305 if (r) 306 return; 307 rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0]; 308 rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1]; 309 rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2]; 310 rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3]; 311 if (radeon_state_pm4(&rstate)) 312 return; 313 if (radeon_draw_set(&rctx->draw, &rstate)) 314 return; 315 } 316 pipe_buffer_unmap(ctx, buffer, transfer); 317 } 318} 319 320static void r600_set_ps_sampler_view(struct pipe_context *ctx, 321 unsigned count, 322 struct pipe_sampler_view **views) 323{ 324 struct r600_context *rctx = r600_context(ctx); 325 struct r600_context_state *rstate; 326 unsigned i; 327 328 for (i = 0; i < rctx->ps_nsampler_view; i++) { 329 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]); 330 } 331 for (i = 0; i < count; i++) { 332 rstate = (struct r600_context_state *)views[i]; 333 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate); 334 } 335 rctx->ps_nsampler_view = count; 336} 337 338static void r600_set_vs_sampler_view(struct pipe_context *ctx, 339 unsigned count, 340 struct pipe_sampler_view **views) 341{ 342 struct r600_context *rctx = r600_context(ctx); 343 struct r600_context_state *rstate; 344 unsigned i; 345 346 for (i = 0; i < rctx->vs_nsampler_view; i++) { 347 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]); 348 } 349 for (i = 0; i < count; i++) { 350 rstate = (struct r600_context_state *)views[i]; 351 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate); 352 } 353 rctx->vs_nsampler_view = count; 354} 355 356static void r600_set_framebuffer_state(struct pipe_context *ctx, 357 const struct pipe_framebuffer_state *state) 358{ 359 struct r600_context *rctx = r600_context(ctx); 360 struct r600_context_state *rstate; 361 362 rstate = r600_context_state(rctx, pipe_framebuffer_type, state); 363 r600_bind_state(ctx, rstate); 364} 365 366static void r600_set_polygon_stipple(struct pipe_context *ctx, 367 const struct pipe_poly_stipple *state) 368{ 369} 370 371static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 372{ 373} 374 375static void r600_set_scissor_state(struct pipe_context *ctx, 376 const struct pipe_scissor_state *state) 377{ 378 struct r600_context *rctx = r600_context(ctx); 379 struct r600_context_state *rstate; 380 381 rstate = r600_context_state(rctx, pipe_scissor_type, state); 382 r600_bind_state(ctx, rstate); 383} 384 385static void r600_set_stencil_ref(struct pipe_context *ctx, 386 const struct pipe_stencil_ref *state) 387{ 388 struct r600_context *rctx = r600_context(ctx); 389 struct r600_context_state *rstate; 390 391 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state); 392 r600_bind_state(ctx, rstate); 393} 394 395static void r600_set_vertex_buffers(struct pipe_context *ctx, 396 unsigned count, 397 const struct pipe_vertex_buffer *buffers) 398{ 399 struct r600_context *rctx = r600_context(ctx); 400 unsigned i; 401 402 for (i = 0; i < rctx->nvertex_buffer; i++) { 403 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL); 404 } 405 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count); 406 for (i = 0; i < count; i++) { 407 rctx->vertex_buffer[i].buffer = NULL; 408 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer); 409 } 410 rctx->nvertex_buffer = count; 411} 412 413static void r600_set_index_buffer(struct pipe_context *ctx, 414 const struct pipe_index_buffer *ib) 415{ 416 struct r600_context *rctx = r600_context(ctx); 417 418 if (ib) { 419 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 420 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer)); 421 } else { 422 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 423 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer)); 424 } 425 426 /* TODO make this more like a state */ 427} 428 429static void r600_set_viewport_state(struct pipe_context *ctx, 430 const struct pipe_viewport_state *state) 431{ 432 struct r600_context *rctx = r600_context(ctx); 433 struct r600_context_state *rstate; 434 435 rstate = r600_context_state(rctx, pipe_viewport_type, state); 436 r600_bind_state(ctx, rstate); 437} 438 439void r600_init_state_functions(struct r600_context *rctx) 440{ 441 rctx->context.create_blend_state = r600_create_blend_state; 442 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 443 rctx->context.create_fs_state = r600_create_shader_state; 444 rctx->context.create_rasterizer_state = r600_create_rs_state; 445 rctx->context.create_sampler_state = r600_create_sampler_state; 446 rctx->context.create_sampler_view = r600_create_sampler_view; 447 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 448 rctx->context.create_vs_state = r600_create_shader_state; 449 rctx->context.bind_blend_state = r600_bind_state; 450 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state; 451 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler; 452 rctx->context.bind_fs_state = r600_bind_ps_shader; 453 rctx->context.bind_rasterizer_state = r600_bind_state; 454 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 455 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler; 456 rctx->context.bind_vs_state = r600_bind_vs_shader; 457 rctx->context.delete_blend_state = r600_delete_state; 458 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 459 rctx->context.delete_fs_state = r600_delete_state; 460 rctx->context.delete_rasterizer_state = r600_delete_state; 461 rctx->context.delete_sampler_state = r600_delete_state; 462 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 463 rctx->context.delete_vs_state = r600_delete_state; 464 rctx->context.set_blend_color = r600_set_blend_color; 465 rctx->context.set_clip_state = r600_set_clip_state; 466 rctx->context.set_constant_buffer = r600_set_constant_buffer; 467 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view; 468 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 469 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 470 rctx->context.set_sample_mask = r600_set_sample_mask; 471 rctx->context.set_scissor_state = r600_set_scissor_state; 472 rctx->context.set_stencil_ref = r600_set_stencil_ref; 473 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 474 rctx->context.set_index_buffer = r600_set_index_buffer; 475 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view; 476 rctx->context.set_viewport_state = r600_set_viewport_state; 477 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 478} 479 480struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate) 481{ 482 if (rstate == NULL) 483 return NULL; 484 rstate->refcount++; 485 return rstate; 486} 487 488struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate) 489{ 490 unsigned i; 491 492 if (rstate == NULL) 493 return NULL; 494 if (--rstate->refcount) 495 return NULL; 496 switch (rstate->type) { 497 case pipe_sampler_view_type: 498 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL); 499 break; 500 case pipe_framebuffer_type: 501 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) { 502 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL); 503 } 504 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL); 505 break; 506 case pipe_viewport_type: 507 case pipe_depth_type: 508 case pipe_rasterizer_type: 509 case pipe_poly_stipple_type: 510 case pipe_scissor_type: 511 case pipe_clip_type: 512 case pipe_stencil_type: 513 case pipe_alpha_type: 514 case pipe_dsa_type: 515 case pipe_blend_type: 516 case pipe_stencil_ref_type: 517 case pipe_shader_type: 518 case pipe_sampler_type: 519 break; 520 default: 521 R600_ERR("invalid type %d\n", rstate->type); 522 return NULL; 523 } 524 FREE(rstate); 525 return NULL; 526} 527 528struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state) 529{ 530 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state); 531 const union pipe_states *states = state; 532 unsigned i; 533 int r; 534 535 if (rstate == NULL) 536 return NULL; 537 rstate->type = type; 538 rstate->refcount = 1; 539 540 switch (rstate->type) { 541 case pipe_sampler_view_type: 542 rstate->state.sampler_view = (*states).sampler_view; 543 rstate->state.sampler_view.texture = NULL; 544 break; 545 case pipe_framebuffer_type: 546 rstate->state.framebuffer = (*states).framebuffer; 547 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) { 548 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], 549 (*states).framebuffer.cbufs[i]); 550 } 551 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, 552 (*states).framebuffer.zsbuf); 553 break; 554 case pipe_viewport_type: 555 rstate->state.viewport = (*states).viewport; 556 break; 557 case pipe_depth_type: 558 rstate->state.depth = (*states).depth; 559 break; 560 case pipe_rasterizer_type: 561 rstate->state.rasterizer = (*states).rasterizer; 562 break; 563 case pipe_poly_stipple_type: 564 rstate->state.poly_stipple = (*states).poly_stipple; 565 break; 566 case pipe_scissor_type: 567 rstate->state.scissor = (*states).scissor; 568 break; 569 case pipe_clip_type: 570 rstate->state.clip = (*states).clip; 571 break; 572 case pipe_stencil_type: 573 rstate->state.stencil = (*states).stencil; 574 break; 575 case pipe_alpha_type: 576 rstate->state.alpha = (*states).alpha; 577 break; 578 case pipe_dsa_type: 579 rstate->state.dsa = (*states).dsa; 580 break; 581 case pipe_blend_type: 582 rstate->state.blend = (*states).blend; 583 break; 584 case pipe_stencil_ref_type: 585 rstate->state.stencil_ref = (*states).stencil_ref; 586 break; 587 case pipe_shader_type: 588 rstate->state.shader = (*states).shader; 589 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens); 590 if (r) { 591 r600_context_state_decref(rstate); 592 return NULL; 593 } 594 break; 595 case pipe_sampler_type: 596 rstate->state.sampler = (*states).sampler; 597 break; 598 default: 599 R600_ERR("invalid type %d\n", rstate->type); 600 FREE(rstate); 601 return NULL; 602 } 603 return rstate; 604} 605 606static int r600_blend(struct r600_context *rctx, struct radeon_state *rstate) 607{ 608 struct r600_screen *rscreen = rctx->screen; 609 const struct pipe_blend_state *state = &rctx->blend->state.blend; 610 int i; 611 int r; 612 613 r = radeon_state_init(rstate, rscreen->rw, R600_BLEND_TYPE, R600_BLEND); 614 if (r) 615 return r; 616 617 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]); 618 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]); 619 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]); 620 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]); 621 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000; 622 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000; 623 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000; 624 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000; 625 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000; 626 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000; 627 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000; 628 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000; 629 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000; 630 631 for (i = 0; i < 8; i++) { 632 unsigned eqRGB = state->rt[i].rgb_func; 633 unsigned srcRGB = state->rt[i].rgb_src_factor; 634 unsigned dstRGB = state->rt[i].rgb_dst_factor; 635 636 unsigned eqA = state->rt[i].alpha_func; 637 unsigned srcA = state->rt[i].alpha_src_factor; 638 unsigned dstA = state->rt[i].alpha_dst_factor; 639 uint32_t bc = 0; 640 641 if (!state->rt[i].blend_enable) 642 continue; 643 644 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 645 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 646 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 647 648 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 649 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 650 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 651 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 652 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 653 } 654 655 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc; 656 if (i == 0) 657 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc; 658 } 659 660 return radeon_state_pm4(rstate); 661} 662 663static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate) 664{ 665 struct r600_screen *rscreen = rctx->screen; 666 struct r600_resource_texture *rtex; 667 struct r600_resource *rbuffer; 668 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer; 669 unsigned level = state->cbufs[0]->level; 670 unsigned pitch, slice; 671 unsigned color_info; 672 unsigned format, swap; 673 int r; 674 675 r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, R600_CB0); 676 if (r) 677 return r; 678 679 rtex = (struct r600_resource_texture*)state->cbufs[0]->texture; 680 rbuffer = &rtex->resource; 681 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 682 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 683 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 684 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 685 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; 686 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT; 687 rstate->nbo = 3; 688 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; 689 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1; 690 691 format = r600_translate_colorformat(rtex->resource.base.b.format); 692 swap = r600_translate_colorswap(rtex->resource.base.b.format); 693 color_info = S_0280A0_FORMAT(format) | 694 S_0280A0_COMP_SWAP(swap) | 695 S_0280A0_BLEND_CLAMP(1) | 696 S_0280A0_SOURCE_FORMAT(1); 697 698 rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000; 699 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info; 700 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | 701 S_028060_SLICE_TILE_MAX(slice); 702 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000; 703 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000; 704 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000; 705 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000; 706 return radeon_state_pm4(rstate); 707} 708 709static int r600_db_format(unsigned pformat, unsigned *format) 710{ 711 switch (pformat) { 712 case PIPE_FORMAT_Z24X8_UNORM: 713 *format = V_028010_DEPTH_X8_24; 714 return 0; 715 case PIPE_FORMAT_Z24_UNORM_S8_USCALED: 716 *format = V_028010_DEPTH_8_24; 717 return 0; 718 default: 719 *format = V_028010_DEPTH_INVALID; 720 R600_ERR("unsupported %d\n", pformat); 721 return -EINVAL; 722 } 723} 724 725static int r600_db(struct r600_context *rctx, struct radeon_state *rstate) 726{ 727 struct r600_screen *rscreen = rctx->screen; 728 struct r600_resource_texture *rtex; 729 struct r600_resource *rbuffer; 730 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer; 731 unsigned level = state->cbufs[0]->level; 732 unsigned pitch, slice, format; 733 int r; 734 735 r = radeon_state_init(rstate, rscreen->rw, R600_DB_TYPE, R600_DB); 736 if (r) 737 return r; 738 739 if (state->zsbuf == NULL) 740 return 0; 741 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 742 rbuffer = &rtex->resource; 743 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 744 rstate->nbo = 1; 745 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; 746 level = state->zsbuf->level; 747 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; 748 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1; 749 if (r600_db_format(state->zsbuf->texture->format, &format)) { 750 return -EINVAL; 751 } 752 rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000; 753 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 | 754 S_028010_FORMAT(format); 755 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000; 756 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1; 757 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) | 758 S_028000_SLICE_TILE_MAX(slice); 759 return radeon_state_pm4(rstate); 760} 761 762static int r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate) 763{ 764 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer; 765 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; 766 struct r600_screen *rscreen = rctx->screen; 767 float offset_units = 0, offset_scale = 0; 768 char depth = 0; 769 unsigned offset_db_fmt_cntl = 0; 770 int r; 771 772 r = radeon_state_init(rstate, rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER); 773 if (r) 774 return r; 775 if (fb->zsbuf) { 776 offset_units = state->offset_units; 777 offset_scale = state->offset_scale * 12.0f; 778 switch (fb->zsbuf->texture->format) { 779 case PIPE_FORMAT_Z24X8_UNORM: 780 case PIPE_FORMAT_Z24_UNORM_S8_USCALED: 781 depth = -24; 782 offset_units *= 2.0f; 783 break; 784 case PIPE_FORMAT_Z32_FLOAT: 785 depth = -23; 786 offset_units *= 1.0f; 787 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 788 break; 789 case PIPE_FORMAT_Z16_UNORM: 790 depth = -16; 791 offset_units *= 4.0f; 792 break; 793 default: 794 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format); 795 return -EINVAL; 796 } 797 } 798 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 799 800 rctx->flat_shade = state->flatshade; 801 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; 802 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000; 803 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 | 804 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 805 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 806 S_028814_FACE(!state->front_ccw) | 807 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 808 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 809 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri); 810 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000; 811 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000; 812 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008; 813 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000; 814 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; 815 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; 816 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000; 817 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; 818 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; 819 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; 820 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; 821 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; 822 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl; 823 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000; 824 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale); 825 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units); 826 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale); 827 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units); 828 return radeon_state_pm4(rstate); 829} 830 831static int r600_scissor(struct r600_context *rctx, struct radeon_state *rstate) 832{ 833 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor; 834 struct r600_screen *rscreen = rctx->screen; 835 u32 tl, br; 836 int r; 837 838 r = radeon_state_init(rstate, rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR); 839 if (r) 840 return r; 841 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 842 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 843 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; 844 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br; 845 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000; 846 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl; 847 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br; 848 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF; 849 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl; 850 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br; 851 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl; 852 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br; 853 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl; 854 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br; 855 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl; 856 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br; 857 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA; 858 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl; 859 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br; 860 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl; 861 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br; 862 return radeon_state_pm4(rstate); 863} 864 865static int r600_viewport(struct r600_context *rctx, struct radeon_state *rstate) 866{ 867 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport; 868 struct r600_screen *rscreen = rctx->screen; 869 int r; 870 871 r = radeon_state_init(rstate, rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT); 872 if (r) 873 return r; 874 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; 875 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000; 876 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]); 877 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]); 878 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]); 879 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]); 880 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]); 881 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]); 882 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F; 883 return radeon_state_pm4(rstate); 884} 885 886static int r600_dsa(struct r600_context *rctx, struct radeon_state *rstate) 887{ 888 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa; 889 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref; 890 struct r600_screen *rscreen = rctx->screen; 891 unsigned db_depth_control, alpha_test_control, alpha_ref; 892 unsigned stencil_ref_mask, stencil_ref_mask_bf; 893 int r; 894 895 r = radeon_state_init(rstate, rscreen->rw, R600_DSA_TYPE, R600_DSA); 896 if (r) 897 return r; 898 899 stencil_ref_mask = 0; 900 stencil_ref_mask_bf = 0; 901 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 902 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 903 S_028800_ZFUNC(state->depth.func); 904 905 /* set stencil enable */ 906 if (state->stencil[0].enabled) { 907 db_depth_control |= S_028800_STENCIL_ENABLE(1); 908 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); 909 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 910 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 911 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 912 913 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | 914 S_028430_STENCILWRITEMASK(state->stencil[0].writemask); 915 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]); 916 if (state->stencil[1].enabled) { 917 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 918 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); 919 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 920 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 921 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 922 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | 923 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); 924 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]); 925 } 926 } 927 928 alpha_test_control = 0; 929 alpha_ref = 0; 930 if (state->alpha.enabled) { 931 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 932 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 933 alpha_ref = fui(state->alpha.ref_value); 934 } 935 936 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000; 937 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; 938 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control; 939 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask; 940 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf; 941 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref; 942 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000; 943 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000; 944 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000; 945 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control; 946 rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210; 947 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060; 948 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A; 949 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000; 950 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000; 951 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; 952 return radeon_state_pm4(rstate); 953} 954 955static inline unsigned r600_tex_wrap(unsigned wrap) 956{ 957 switch (wrap) { 958 default: 959 case PIPE_TEX_WRAP_REPEAT: 960 return V_03C000_SQ_TEX_WRAP; 961 case PIPE_TEX_WRAP_CLAMP: 962 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; 963 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 964 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; 965 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 966 return V_03C000_SQ_TEX_CLAMP_BORDER; 967 case PIPE_TEX_WRAP_MIRROR_REPEAT: 968 return V_03C000_SQ_TEX_MIRROR; 969 case PIPE_TEX_WRAP_MIRROR_CLAMP: 970 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 971 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 972 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 973 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 974 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; 975 } 976} 977 978static inline unsigned r600_tex_filter(unsigned filter) 979{ 980 switch (filter) { 981 default: 982 case PIPE_TEX_FILTER_NEAREST: 983 return V_03C000_SQ_TEX_XY_FILTER_POINT; 984 case PIPE_TEX_FILTER_LINEAR: 985 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; 986 } 987} 988 989static inline unsigned r600_tex_mipfilter(unsigned filter) 990{ 991 switch (filter) { 992 case PIPE_TEX_MIPFILTER_NEAREST: 993 return V_03C000_SQ_TEX_Z_FILTER_POINT; 994 case PIPE_TEX_MIPFILTER_LINEAR: 995 return V_03C000_SQ_TEX_Z_FILTER_LINEAR; 996 default: 997 case PIPE_TEX_MIPFILTER_NONE: 998 return V_03C000_SQ_TEX_Z_FILTER_NONE; 999 } 1000} 1001 1002static inline unsigned r600_tex_compare(unsigned compare) 1003{ 1004 switch (compare) { 1005 default: 1006 case PIPE_FUNC_NEVER: 1007 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; 1008 case PIPE_FUNC_LESS: 1009 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; 1010 case PIPE_FUNC_EQUAL: 1011 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; 1012 case PIPE_FUNC_LEQUAL: 1013 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1014 case PIPE_FUNC_GREATER: 1015 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; 1016 case PIPE_FUNC_NOTEQUAL: 1017 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1018 case PIPE_FUNC_GEQUAL: 1019 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1020 case PIPE_FUNC_ALWAYS: 1021 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1022 } 1023} 1024 1025static INLINE u32 S_FIXED(float value, u32 frac_bits) 1026{ 1027 return value * (1 << frac_bits); 1028} 1029 1030static int r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, 1031 const struct pipe_sampler_state *state, unsigned id) 1032{ 1033 struct r600_screen *rscreen = rctx->screen; 1034 int r; 1035 1036 r = radeon_state_init(rstate, rscreen->rw, R600_PS_SAMPLER_TYPE, id); 1037 if (r) 1038 return r; 1039 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] = 1040 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 1041 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 1042 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 1043 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | 1044 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | 1045 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 1046 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)); 1047 /* FIXME LOD it depends on texture base level ... */ 1048 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] = 1049 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 1050 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 1051 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); 1052 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1); 1053 return radeon_state_pm4(rstate); 1054} 1055 1056static inline unsigned r600_tex_swizzle(unsigned swizzle) 1057{ 1058 switch (swizzle) { 1059 case PIPE_SWIZZLE_RED: 1060 return V_038010_SQ_SEL_X; 1061 case PIPE_SWIZZLE_GREEN: 1062 return V_038010_SQ_SEL_Y; 1063 case PIPE_SWIZZLE_BLUE: 1064 return V_038010_SQ_SEL_Z; 1065 case PIPE_SWIZZLE_ALPHA: 1066 return V_038010_SQ_SEL_W; 1067 case PIPE_SWIZZLE_ZERO: 1068 return V_038010_SQ_SEL_0; 1069 default: 1070 case PIPE_SWIZZLE_ONE: 1071 return V_038010_SQ_SEL_1; 1072 } 1073} 1074 1075static inline unsigned r600_format_type(unsigned format_type) 1076{ 1077 switch (format_type) { 1078 default: 1079 case UTIL_FORMAT_TYPE_UNSIGNED: 1080 return V_038010_SQ_FORMAT_COMP_UNSIGNED; 1081 case UTIL_FORMAT_TYPE_SIGNED: 1082 return V_038010_SQ_FORMAT_COMP_SIGNED; 1083 case UTIL_FORMAT_TYPE_FIXED: 1084 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED; 1085 } 1086} 1087 1088static inline unsigned r600_tex_dim(unsigned dim) 1089{ 1090 switch (dim) { 1091 default: 1092 case PIPE_TEXTURE_1D: 1093 return V_038000_SQ_TEX_DIM_1D; 1094 case PIPE_TEXTURE_2D: 1095 return V_038000_SQ_TEX_DIM_2D; 1096 case PIPE_TEXTURE_3D: 1097 return V_038000_SQ_TEX_DIM_3D; 1098 case PIPE_TEXTURE_CUBE: 1099 return V_038000_SQ_TEX_DIM_CUBEMAP; 1100 } 1101} 1102 1103static int r600_resource(struct r600_context *rctx, struct radeon_state *rstate, 1104 const struct pipe_sampler_view *view, unsigned id) 1105{ 1106 struct r600_screen *rscreen = rctx->screen; 1107 const struct util_format_description *desc; 1108 struct r600_resource_texture *tmp; 1109 struct r600_resource *rbuffer; 1110 unsigned format; 1111 int r; 1112 1113 r = radeon_state_init(rstate, rscreen->rw, R600_PS_RESOURCE_TYPE, id); 1114 if (r) 1115 return r; 1116 format = r600_translate_colorformat(view->texture->format); 1117 if (format == ~0) 1118 return -EINVAL; 1119 desc = util_format_description(view->texture->format); 1120 if (desc == NULL) { 1121 R600_ERR("unknow format %d\n", view->texture->format); 1122 return -EINVAL; 1123 } 1124 tmp = (struct r600_resource_texture*)view->texture; 1125 rbuffer = &tmp->resource; 1126 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 1127 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo); 1128 rstate->nbo = 2; 1129 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 1130 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT; 1131 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; 1132 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT; 1133 1134 /* FIXME properly handle first level != 0 */ 1135 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = 1136 S_038000_DIM(r600_tex_dim(view->texture->target)) | 1137 S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) | 1138 S_038000_TEX_WIDTH(view->texture->width0 - 1); 1139 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = 1140 S_038004_TEX_HEIGHT(view->texture->height0 - 1) | 1141 S_038004_TEX_DEPTH(view->texture->depth0 - 1) | 1142 S_038004_DATA_FORMAT(format); 1143 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0; 1144 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8; 1145 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 1146 S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1147 S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1148 S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1149 S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) | 1150 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) | 1151 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) | 1152 S_038010_REQUEST_SIZE(1) | 1153 S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) | 1154 S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) | 1155 S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) | 1156 S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) | 1157 S_038010_BASE_LEVEL(view->first_level); 1158 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 1159 S_038014_LAST_LEVEL(view->last_level) | 1160 S_038014_BASE_ARRAY(0) | 1161 S_038014_LAST_ARRAY(0); 1162 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 1163 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE); 1164 return radeon_state_pm4(rstate); 1165} 1166 1167static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate) 1168{ 1169 struct r600_screen *rscreen = rctx->screen; 1170 const struct pipe_blend_state *pbs = &rctx->blend->state.blend; 1171 uint32_t color_control, target_mask; 1172 int i, r; 1173 1174 target_mask = 0; 1175 color_control = S_028808_PER_MRT_BLEND(1); 1176 1177 if (pbs->logicop_enable) { 1178 color_control |= (pbs->logicop_func) << 16; 1179 } else 1180 color_control |= (0xcc << 16); 1181 1182 for (i = 0; i < 8; i++) { 1183 if (pbs->rt[i].blend_enable) { 1184 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 1185 } 1186 target_mask |= (pbs->rt[i].colormask << (4 * i)); 1187 } 1188 r = radeon_state_init(rstate, rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL); 1189 if (r) 1190 return r; 1191 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F; 1192 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask; 1193 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control; 1194 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000; 1195 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000; 1196 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000; 1197 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000; 1198 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000; 1199 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF; 1200 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF; 1201 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF; 1202 return radeon_state_pm4(rstate); 1203} 1204 1205int r600_context_hw_states(struct r600_context *rctx) 1206{ 1207 unsigned i; 1208 int r; 1209 1210 /* free previous TODO determine what need to be updated, what 1211 * doesn't 1212 */ 1213 memset(&rctx->hw_states, 0, sizeof(struct r600_context_hw_states)); 1214 1215 /* build new states */ 1216 rctx->hw_states.config = rctx->config; 1217 r600_rasterizer(rctx, &rctx->hw_states.rasterizer); 1218 r600_scissor(rctx, &rctx->hw_states.scissor); 1219 r600_dsa(rctx, &rctx->hw_states.dsa); 1220 r600_blend(rctx, &rctx->hw_states.blend); 1221 r600_viewport(rctx, &rctx->hw_states.viewport); 1222 r600_cb0(rctx, &rctx->hw_states.cb0); 1223 r600_db(rctx, &rctx->hw_states.db); 1224 r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl); 1225 1226 for (i = 0; i < rctx->ps_nsampler; i++) { 1227 if (rctx->ps_sampler[i]) { 1228 r600_sampler(rctx, &rctx->hw_states.ps_sampler[i], 1229 &rctx->ps_sampler[i]->state.sampler, 1230 R600_PS_SAMPLER + i); 1231 } 1232 } 1233 rctx->hw_states.ps_nsampler = rctx->ps_nsampler; 1234 for (i = 0; i < rctx->ps_nsampler_view; i++) { 1235 if (rctx->ps_sampler_view[i]) { 1236 r600_resource(rctx, &rctx->hw_states.ps_resource[i], 1237 &rctx->ps_sampler_view[i]->state.sampler_view, 1238 R600_PS_RESOURCE + i); 1239 } 1240 } 1241 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view; 1242 1243 /* bind states */ 1244 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.db); 1245 if (r) 1246 return r; 1247 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.rasterizer); 1248 if (r) 1249 return r; 1250 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.scissor); 1251 if (r) 1252 return r; 1253 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.dsa); 1254 if (r) 1255 return r; 1256 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.blend); 1257 if (r) 1258 return r; 1259 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.viewport); 1260 if (r) 1261 return r; 1262 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb0); 1263 if (r) 1264 return r; 1265 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.config); 1266 if (r) 1267 return r; 1268 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb_cntl); 1269 if (r) 1270 return r; 1271 for (i = 0; i < rctx->hw_states.ps_nresource; i++) { 1272 if (rctx->hw_states.ps_resource[i].valid) { 1273 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.ps_resource[i]); 1274 if (r) 1275 return r; 1276 } 1277 } 1278 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) { 1279 if (rctx->hw_states.ps_sampler[i].valid) { 1280 r = radeon_draw_set(&rctx->draw, &rctx->hw_states.ps_sampler[i]); 1281 if (r) 1282 return r; 1283 } 1284 } 1285 return 0; 1286} 1287