r600_state.c revision bb4c5d72d7c7cb1d9e7016e2c07c36875f30011a 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "r600d.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31
32static uint32_t r600_translate_blend_function(int blend_func)
33{
34	switch (blend_func) {
35	case PIPE_BLEND_ADD:
36		return V_028804_COMB_DST_PLUS_SRC;
37	case PIPE_BLEND_SUBTRACT:
38		return V_028804_COMB_SRC_MINUS_DST;
39	case PIPE_BLEND_REVERSE_SUBTRACT:
40		return V_028804_COMB_DST_MINUS_SRC;
41	case PIPE_BLEND_MIN:
42		return V_028804_COMB_MIN_DST_SRC;
43	case PIPE_BLEND_MAX:
44		return V_028804_COMB_MAX_DST_SRC;
45	default:
46		R600_ERR("Unknown blend function %d\n", blend_func);
47		assert(0);
48		break;
49	}
50	return 0;
51}
52
53static uint32_t r600_translate_blend_factor(int blend_fact)
54{
55	switch (blend_fact) {
56	case PIPE_BLENDFACTOR_ONE:
57		return V_028804_BLEND_ONE;
58	case PIPE_BLENDFACTOR_SRC_COLOR:
59		return V_028804_BLEND_SRC_COLOR;
60	case PIPE_BLENDFACTOR_SRC_ALPHA:
61		return V_028804_BLEND_SRC_ALPHA;
62	case PIPE_BLENDFACTOR_DST_ALPHA:
63		return V_028804_BLEND_DST_ALPHA;
64	case PIPE_BLENDFACTOR_DST_COLOR:
65		return V_028804_BLEND_DST_COLOR;
66	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67		return V_028804_BLEND_SRC_ALPHA_SATURATE;
68	case PIPE_BLENDFACTOR_CONST_COLOR:
69		return V_028804_BLEND_CONST_COLOR;
70	case PIPE_BLENDFACTOR_CONST_ALPHA:
71		return V_028804_BLEND_CONST_ALPHA;
72	case PIPE_BLENDFACTOR_ZERO:
73		return V_028804_BLEND_ZERO;
74	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80	case PIPE_BLENDFACTOR_INV_DST_COLOR:
81		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86	case PIPE_BLENDFACTOR_SRC1_COLOR:
87		return V_028804_BLEND_SRC1_COLOR;
88	case PIPE_BLENDFACTOR_SRC1_ALPHA:
89		return V_028804_BLEND_SRC1_ALPHA;
90	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91		return V_028804_BLEND_INV_SRC1_COLOR;
92	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93		return V_028804_BLEND_INV_SRC1_ALPHA;
94	default:
95		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96		assert(0);
97		break;
98	}
99	return 0;
100}
101
102static unsigned r600_tex_dim(unsigned dim)
103{
104	switch (dim) {
105	default:
106	case PIPE_TEXTURE_1D:
107		return V_038000_SQ_TEX_DIM_1D;
108	case PIPE_TEXTURE_1D_ARRAY:
109		return V_038000_SQ_TEX_DIM_1D_ARRAY;
110	case PIPE_TEXTURE_2D:
111	case PIPE_TEXTURE_RECT:
112		return V_038000_SQ_TEX_DIM_2D;
113	case PIPE_TEXTURE_2D_ARRAY:
114		return V_038000_SQ_TEX_DIM_2D_ARRAY;
115	case PIPE_TEXTURE_3D:
116		return V_038000_SQ_TEX_DIM_3D;
117	case PIPE_TEXTURE_CUBE:
118		return V_038000_SQ_TEX_DIM_CUBEMAP;
119	}
120}
121
122static uint32_t r600_translate_dbformat(enum pipe_format format)
123{
124	switch (format) {
125	case PIPE_FORMAT_Z16_UNORM:
126		return V_028010_DEPTH_16;
127	case PIPE_FORMAT_Z24X8_UNORM:
128		return V_028010_DEPTH_X8_24;
129	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
130		return V_028010_DEPTH_8_24;
131	case PIPE_FORMAT_Z32_FLOAT:
132		return V_028010_DEPTH_32_FLOAT;
133	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
134		return V_028010_DEPTH_X24_8_32_FLOAT;
135	default:
136		return ~0U;
137	}
138}
139
140static uint32_t r600_translate_colorswap(enum pipe_format format)
141{
142	switch (format) {
143	/* 8-bit buffers. */
144	case PIPE_FORMAT_A8_UNORM:
145	case PIPE_FORMAT_A8_SNORM:
146	case PIPE_FORMAT_A8_UINT:
147	case PIPE_FORMAT_A8_SINT:
148	case PIPE_FORMAT_A16_UNORM:
149	case PIPE_FORMAT_A16_SNORM:
150	case PIPE_FORMAT_A16_UINT:
151	case PIPE_FORMAT_A16_SINT:
152	case PIPE_FORMAT_A16_FLOAT:
153	case PIPE_FORMAT_A32_UINT:
154	case PIPE_FORMAT_A32_SINT:
155	case PIPE_FORMAT_A32_FLOAT:
156	case PIPE_FORMAT_R4A4_UNORM:
157		return V_0280A0_SWAP_ALT_REV;
158	case PIPE_FORMAT_I8_UNORM:
159	case PIPE_FORMAT_I8_SNORM:
160	case PIPE_FORMAT_I8_UINT:
161	case PIPE_FORMAT_I8_SINT:
162	case PIPE_FORMAT_L8_UNORM:
163	case PIPE_FORMAT_L8_SNORM:
164	case PIPE_FORMAT_L8_UINT:
165	case PIPE_FORMAT_L8_SINT:
166	case PIPE_FORMAT_L8_SRGB:
167	case PIPE_FORMAT_L16_UNORM:
168	case PIPE_FORMAT_L16_SNORM:
169	case PIPE_FORMAT_L16_UINT:
170	case PIPE_FORMAT_L16_SINT:
171	case PIPE_FORMAT_L16_FLOAT:
172	case PIPE_FORMAT_L32_UINT:
173	case PIPE_FORMAT_L32_SINT:
174	case PIPE_FORMAT_L32_FLOAT:
175	case PIPE_FORMAT_I16_UNORM:
176	case PIPE_FORMAT_I16_SNORM:
177	case PIPE_FORMAT_I16_UINT:
178	case PIPE_FORMAT_I16_SINT:
179	case PIPE_FORMAT_I16_FLOAT:
180	case PIPE_FORMAT_I32_UINT:
181	case PIPE_FORMAT_I32_SINT:
182	case PIPE_FORMAT_I32_FLOAT:
183	case PIPE_FORMAT_R8_UNORM:
184	case PIPE_FORMAT_R8_SNORM:
185	case PIPE_FORMAT_R8_UINT:
186	case PIPE_FORMAT_R8_SINT:
187		return V_0280A0_SWAP_STD;
188
189	case PIPE_FORMAT_L4A4_UNORM:
190	case PIPE_FORMAT_A4R4_UNORM:
191		return V_0280A0_SWAP_ALT;
192
193	/* 16-bit buffers. */
194	case PIPE_FORMAT_B5G6R5_UNORM:
195		return V_0280A0_SWAP_STD_REV;
196
197	case PIPE_FORMAT_B5G5R5A1_UNORM:
198	case PIPE_FORMAT_B5G5R5X1_UNORM:
199		return V_0280A0_SWAP_ALT;
200
201	case PIPE_FORMAT_B4G4R4A4_UNORM:
202	case PIPE_FORMAT_B4G4R4X4_UNORM:
203		return V_0280A0_SWAP_ALT;
204
205	case PIPE_FORMAT_Z16_UNORM:
206		return V_0280A0_SWAP_STD;
207
208	case PIPE_FORMAT_L8A8_UNORM:
209	case PIPE_FORMAT_L8A8_SNORM:
210	case PIPE_FORMAT_L8A8_UINT:
211	case PIPE_FORMAT_L8A8_SINT:
212	case PIPE_FORMAT_L8A8_SRGB:
213	case PIPE_FORMAT_L16A16_UNORM:
214	case PIPE_FORMAT_L16A16_SNORM:
215	case PIPE_FORMAT_L16A16_UINT:
216	case PIPE_FORMAT_L16A16_SINT:
217	case PIPE_FORMAT_L16A16_FLOAT:
218	case PIPE_FORMAT_L32A32_UINT:
219	case PIPE_FORMAT_L32A32_SINT:
220	case PIPE_FORMAT_L32A32_FLOAT:
221		return V_0280A0_SWAP_ALT;
222	case PIPE_FORMAT_R8G8_UNORM:
223	case PIPE_FORMAT_R8G8_SNORM:
224	case PIPE_FORMAT_R8G8_UINT:
225	case PIPE_FORMAT_R8G8_SINT:
226		return V_0280A0_SWAP_STD;
227
228	case PIPE_FORMAT_R16_UNORM:
229	case PIPE_FORMAT_R16_SNORM:
230	case PIPE_FORMAT_R16_UINT:
231	case PIPE_FORMAT_R16_SINT:
232	case PIPE_FORMAT_R16_FLOAT:
233		return V_0280A0_SWAP_STD;
234
235	/* 32-bit buffers. */
236
237	case PIPE_FORMAT_A8B8G8R8_SRGB:
238		return V_0280A0_SWAP_STD_REV;
239	case PIPE_FORMAT_B8G8R8A8_SRGB:
240		return V_0280A0_SWAP_ALT;
241
242	case PIPE_FORMAT_B8G8R8A8_UNORM:
243	case PIPE_FORMAT_B8G8R8X8_UNORM:
244		return V_0280A0_SWAP_ALT;
245
246	case PIPE_FORMAT_A8R8G8B8_UNORM:
247	case PIPE_FORMAT_X8R8G8B8_UNORM:
248		return V_0280A0_SWAP_ALT_REV;
249	case PIPE_FORMAT_R8G8B8A8_SNORM:
250	case PIPE_FORMAT_R8G8B8A8_UNORM:
251	case PIPE_FORMAT_R8G8B8X8_UNORM:
252	case PIPE_FORMAT_R8G8B8A8_SINT:
253	case PIPE_FORMAT_R8G8B8A8_UINT:
254		return V_0280A0_SWAP_STD;
255
256	case PIPE_FORMAT_A8B8G8R8_UNORM:
257	case PIPE_FORMAT_X8B8G8R8_UNORM:
258	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
259		return V_0280A0_SWAP_STD_REV;
260
261	case PIPE_FORMAT_Z24X8_UNORM:
262	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263		return V_0280A0_SWAP_STD;
264
265	case PIPE_FORMAT_X8Z24_UNORM:
266	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
267		return V_0280A0_SWAP_STD;
268
269	case PIPE_FORMAT_R10G10B10A2_UNORM:
270	case PIPE_FORMAT_R10G10B10X2_SNORM:
271	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
272		return V_0280A0_SWAP_STD;
273
274	case PIPE_FORMAT_B10G10R10A2_UNORM:
275	case PIPE_FORMAT_B10G10R10A2_UINT:
276		return V_0280A0_SWAP_ALT;
277
278	case PIPE_FORMAT_R11G11B10_FLOAT:
279	case PIPE_FORMAT_R16G16_UNORM:
280	case PIPE_FORMAT_R16G16_SNORM:
281	case PIPE_FORMAT_R16G16_FLOAT:
282	case PIPE_FORMAT_R16G16_UINT:
283	case PIPE_FORMAT_R16G16_SINT:
284	case PIPE_FORMAT_R32_UINT:
285	case PIPE_FORMAT_R32_SINT:
286	case PIPE_FORMAT_R32_FLOAT:
287	case PIPE_FORMAT_Z32_FLOAT:
288		return V_0280A0_SWAP_STD;
289
290	/* 64-bit buffers. */
291	case PIPE_FORMAT_R32G32_FLOAT:
292	case PIPE_FORMAT_R32G32_UINT:
293	case PIPE_FORMAT_R32G32_SINT:
294	case PIPE_FORMAT_R16G16B16A16_UNORM:
295	case PIPE_FORMAT_R16G16B16A16_SNORM:
296	case PIPE_FORMAT_R16G16B16A16_UINT:
297	case PIPE_FORMAT_R16G16B16A16_SINT:
298	case PIPE_FORMAT_R16G16B16A16_FLOAT:
299	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
300
301	/* 128-bit buffers. */
302	case PIPE_FORMAT_R32G32B32A32_FLOAT:
303	case PIPE_FORMAT_R32G32B32A32_SNORM:
304	case PIPE_FORMAT_R32G32B32A32_UNORM:
305	case PIPE_FORMAT_R32G32B32A32_SINT:
306	case PIPE_FORMAT_R32G32B32A32_UINT:
307		return V_0280A0_SWAP_STD;
308	default:
309		R600_ERR("unsupported colorswap format %d\n", format);
310		return ~0U;
311	}
312	return ~0U;
313}
314
315static uint32_t r600_translate_colorformat(enum pipe_format format)
316{
317	switch (format) {
318	case PIPE_FORMAT_L4A4_UNORM:
319	case PIPE_FORMAT_R4A4_UNORM:
320	case PIPE_FORMAT_A4R4_UNORM:
321		return V_0280A0_COLOR_4_4;
322
323	/* 8-bit buffers. */
324	case PIPE_FORMAT_A8_UNORM:
325	case PIPE_FORMAT_A8_SNORM:
326	case PIPE_FORMAT_A8_UINT:
327	case PIPE_FORMAT_A8_SINT:
328	case PIPE_FORMAT_I8_UNORM:
329	case PIPE_FORMAT_I8_SNORM:
330	case PIPE_FORMAT_I8_UINT:
331	case PIPE_FORMAT_I8_SINT:
332	case PIPE_FORMAT_L8_UNORM:
333	case PIPE_FORMAT_L8_SNORM:
334	case PIPE_FORMAT_L8_UINT:
335	case PIPE_FORMAT_L8_SINT:
336	case PIPE_FORMAT_L8_SRGB:
337	case PIPE_FORMAT_R8_UNORM:
338	case PIPE_FORMAT_R8_SNORM:
339	case PIPE_FORMAT_R8_UINT:
340	case PIPE_FORMAT_R8_SINT:
341		return V_0280A0_COLOR_8;
342
343	/* 16-bit buffers. */
344	case PIPE_FORMAT_B5G6R5_UNORM:
345		return V_0280A0_COLOR_5_6_5;
346
347	case PIPE_FORMAT_B5G5R5A1_UNORM:
348	case PIPE_FORMAT_B5G5R5X1_UNORM:
349		return V_0280A0_COLOR_1_5_5_5;
350
351	case PIPE_FORMAT_B4G4R4A4_UNORM:
352	case PIPE_FORMAT_B4G4R4X4_UNORM:
353		return V_0280A0_COLOR_4_4_4_4;
354
355	case PIPE_FORMAT_Z16_UNORM:
356		return V_0280A0_COLOR_16;
357
358	case PIPE_FORMAT_L8A8_UNORM:
359	case PIPE_FORMAT_L8A8_SNORM:
360	case PIPE_FORMAT_L8A8_UINT:
361	case PIPE_FORMAT_L8A8_SINT:
362	case PIPE_FORMAT_L8A8_SRGB:
363	case PIPE_FORMAT_R8G8_UNORM:
364	case PIPE_FORMAT_R8G8_SNORM:
365	case PIPE_FORMAT_R8G8_UINT:
366	case PIPE_FORMAT_R8G8_SINT:
367		return V_0280A0_COLOR_8_8;
368
369	case PIPE_FORMAT_R16_UNORM:
370	case PIPE_FORMAT_R16_SNORM:
371	case PIPE_FORMAT_R16_UINT:
372	case PIPE_FORMAT_R16_SINT:
373	case PIPE_FORMAT_A16_UNORM:
374	case PIPE_FORMAT_A16_SNORM:
375	case PIPE_FORMAT_A16_UINT:
376	case PIPE_FORMAT_A16_SINT:
377	case PIPE_FORMAT_L16_UNORM:
378	case PIPE_FORMAT_L16_SNORM:
379	case PIPE_FORMAT_L16_UINT:
380	case PIPE_FORMAT_L16_SINT:
381	case PIPE_FORMAT_I16_UNORM:
382	case PIPE_FORMAT_I16_SNORM:
383	case PIPE_FORMAT_I16_UINT:
384	case PIPE_FORMAT_I16_SINT:
385		return V_0280A0_COLOR_16;
386
387	case PIPE_FORMAT_R16_FLOAT:
388	case PIPE_FORMAT_A16_FLOAT:
389	case PIPE_FORMAT_L16_FLOAT:
390	case PIPE_FORMAT_I16_FLOAT:
391		return V_0280A0_COLOR_16_FLOAT;
392
393	/* 32-bit buffers. */
394	case PIPE_FORMAT_A8B8G8R8_SRGB:
395	case PIPE_FORMAT_A8B8G8R8_UNORM:
396	case PIPE_FORMAT_A8R8G8B8_UNORM:
397	case PIPE_FORMAT_B8G8R8A8_SRGB:
398	case PIPE_FORMAT_B8G8R8A8_UNORM:
399	case PIPE_FORMAT_B8G8R8X8_UNORM:
400	case PIPE_FORMAT_R8G8B8A8_SNORM:
401	case PIPE_FORMAT_R8G8B8A8_UNORM:
402	case PIPE_FORMAT_R8G8B8X8_UNORM:
403	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
404	case PIPE_FORMAT_X8B8G8R8_UNORM:
405	case PIPE_FORMAT_X8R8G8B8_UNORM:
406	case PIPE_FORMAT_R8G8B8_UNORM:
407	case PIPE_FORMAT_R8G8B8A8_SINT:
408	case PIPE_FORMAT_R8G8B8A8_UINT:
409		return V_0280A0_COLOR_8_8_8_8;
410
411	case PIPE_FORMAT_R10G10B10A2_UNORM:
412	case PIPE_FORMAT_R10G10B10X2_SNORM:
413	case PIPE_FORMAT_B10G10R10A2_UNORM:
414	case PIPE_FORMAT_B10G10R10A2_UINT:
415	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
416		return V_0280A0_COLOR_2_10_10_10;
417
418	case PIPE_FORMAT_Z24X8_UNORM:
419	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
420		return V_0280A0_COLOR_8_24;
421
422	case PIPE_FORMAT_X8Z24_UNORM:
423	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
424		return V_0280A0_COLOR_24_8;
425
426	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
427		return V_0280A0_COLOR_X24_8_32_FLOAT;
428
429	case PIPE_FORMAT_R32_UINT:
430	case PIPE_FORMAT_R32_SINT:
431	case PIPE_FORMAT_A32_UINT:
432	case PIPE_FORMAT_A32_SINT:
433	case PIPE_FORMAT_L32_UINT:
434	case PIPE_FORMAT_L32_SINT:
435	case PIPE_FORMAT_I32_UINT:
436	case PIPE_FORMAT_I32_SINT:
437		return V_0280A0_COLOR_32;
438
439	case PIPE_FORMAT_R32_FLOAT:
440	case PIPE_FORMAT_A32_FLOAT:
441	case PIPE_FORMAT_L32_FLOAT:
442	case PIPE_FORMAT_I32_FLOAT:
443	case PIPE_FORMAT_Z32_FLOAT:
444		return V_0280A0_COLOR_32_FLOAT;
445
446	case PIPE_FORMAT_R16G16_FLOAT:
447	case PIPE_FORMAT_L16A16_FLOAT:
448		return V_0280A0_COLOR_16_16_FLOAT;
449
450	case PIPE_FORMAT_R16G16_UNORM:
451	case PIPE_FORMAT_R16G16_SNORM:
452	case PIPE_FORMAT_R16G16_UINT:
453	case PIPE_FORMAT_R16G16_SINT:
454	case PIPE_FORMAT_L16A16_UNORM:
455	case PIPE_FORMAT_L16A16_SNORM:
456	case PIPE_FORMAT_L16A16_UINT:
457	case PIPE_FORMAT_L16A16_SINT:
458		return V_0280A0_COLOR_16_16;
459
460	case PIPE_FORMAT_R11G11B10_FLOAT:
461		return V_0280A0_COLOR_10_11_11_FLOAT;
462
463	/* 64-bit buffers. */
464	case PIPE_FORMAT_R16G16B16A16_UINT:
465	case PIPE_FORMAT_R16G16B16A16_SINT:
466	case PIPE_FORMAT_R16G16B16A16_UNORM:
467	case PIPE_FORMAT_R16G16B16A16_SNORM:
468		return V_0280A0_COLOR_16_16_16_16;
469
470	case PIPE_FORMAT_R16G16B16_FLOAT:
471	case PIPE_FORMAT_R16G16B16A16_FLOAT:
472		return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474	case PIPE_FORMAT_R32G32_FLOAT:
475	case PIPE_FORMAT_L32A32_FLOAT:
476		return V_0280A0_COLOR_32_32_FLOAT;
477
478	case PIPE_FORMAT_R32G32_SINT:
479	case PIPE_FORMAT_R32G32_UINT:
480	case PIPE_FORMAT_L32A32_UINT:
481	case PIPE_FORMAT_L32A32_SINT:
482		return V_0280A0_COLOR_32_32;
483
484	/* 96-bit buffers. */
485	case PIPE_FORMAT_R32G32B32_FLOAT:
486		return V_0280A0_COLOR_32_32_32_FLOAT;
487
488	/* 128-bit buffers. */
489	case PIPE_FORMAT_R32G32B32A32_FLOAT:
490		return V_0280A0_COLOR_32_32_32_32_FLOAT;
491	case PIPE_FORMAT_R32G32B32A32_SNORM:
492	case PIPE_FORMAT_R32G32B32A32_UNORM:
493	case PIPE_FORMAT_R32G32B32A32_SINT:
494	case PIPE_FORMAT_R32G32B32A32_UINT:
495		return V_0280A0_COLOR_32_32_32_32;
496
497	/* YUV buffers. */
498	case PIPE_FORMAT_UYVY:
499	case PIPE_FORMAT_YUYV:
500	default:
501		return ~0U; /* Unsupported. */
502	}
503}
504
505static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
506{
507	if (R600_BIG_ENDIAN) {
508		switch(colorformat) {
509		case V_0280A0_COLOR_4_4:
510			return ENDIAN_NONE;
511
512		/* 8-bit buffers. */
513		case V_0280A0_COLOR_8:
514			return ENDIAN_NONE;
515
516		/* 16-bit buffers. */
517		case V_0280A0_COLOR_5_6_5:
518		case V_0280A0_COLOR_1_5_5_5:
519		case V_0280A0_COLOR_4_4_4_4:
520		case V_0280A0_COLOR_16:
521		case V_0280A0_COLOR_8_8:
522			return ENDIAN_8IN16;
523
524		/* 32-bit buffers. */
525		case V_0280A0_COLOR_8_8_8_8:
526		case V_0280A0_COLOR_2_10_10_10:
527		case V_0280A0_COLOR_8_24:
528		case V_0280A0_COLOR_24_8:
529		case V_0280A0_COLOR_32_FLOAT:
530		case V_0280A0_COLOR_16_16_FLOAT:
531		case V_0280A0_COLOR_16_16:
532			return ENDIAN_8IN32;
533
534		/* 64-bit buffers. */
535		case V_0280A0_COLOR_16_16_16_16:
536		case V_0280A0_COLOR_16_16_16_16_FLOAT:
537			return ENDIAN_8IN16;
538
539		case V_0280A0_COLOR_32_32_FLOAT:
540		case V_0280A0_COLOR_32_32:
541		case V_0280A0_COLOR_X24_8_32_FLOAT:
542			return ENDIAN_8IN32;
543
544		/* 128-bit buffers. */
545		case V_0280A0_COLOR_32_32_32_FLOAT:
546		case V_0280A0_COLOR_32_32_32_32_FLOAT:
547		case V_0280A0_COLOR_32_32_32_32:
548			return ENDIAN_8IN32;
549		default:
550			return ENDIAN_NONE; /* Unsupported. */
551		}
552	} else {
553		return ENDIAN_NONE;
554	}
555}
556
557static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
558{
559	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
560}
561
562static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
563{
564	return r600_translate_colorformat(format) != ~0U &&
565	       r600_translate_colorswap(format) != ~0U;
566}
567
568static bool r600_is_zs_format_supported(enum pipe_format format)
569{
570	return r600_translate_dbformat(format) != ~0U;
571}
572
573boolean r600_is_format_supported(struct pipe_screen *screen,
574				 enum pipe_format format,
575				 enum pipe_texture_target target,
576				 unsigned sample_count,
577				 unsigned usage)
578{
579	unsigned retval = 0;
580
581	if (target >= PIPE_MAX_TEXTURE_TYPES) {
582		R600_ERR("r600: unsupported texture type %d\n", target);
583		return FALSE;
584	}
585
586	if (!util_format_is_supported(format, usage))
587		return FALSE;
588
589	/* Multisample */
590	if (sample_count > 1)
591		return FALSE;
592
593	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
594	    r600_is_sampler_format_supported(screen, format)) {
595		retval |= PIPE_BIND_SAMPLER_VIEW;
596	}
597
598	if ((usage & (PIPE_BIND_RENDER_TARGET |
599		      PIPE_BIND_DISPLAY_TARGET |
600		      PIPE_BIND_SCANOUT |
601		      PIPE_BIND_SHARED)) &&
602	    r600_is_colorbuffer_format_supported(format)) {
603		retval |= usage &
604			  (PIPE_BIND_RENDER_TARGET |
605			   PIPE_BIND_DISPLAY_TARGET |
606			   PIPE_BIND_SCANOUT |
607			   PIPE_BIND_SHARED);
608	}
609
610	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
611	    r600_is_zs_format_supported(format)) {
612		retval |= PIPE_BIND_DEPTH_STENCIL;
613	}
614
615	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
616	    r600_is_vertex_format_supported(format)) {
617		retval |= PIPE_BIND_VERTEX_BUFFER;
618	}
619
620	if (usage & PIPE_BIND_TRANSFER_READ)
621		retval |= PIPE_BIND_TRANSFER_READ;
622	if (usage & PIPE_BIND_TRANSFER_WRITE)
623		retval |= PIPE_BIND_TRANSFER_WRITE;
624
625	return retval == usage;
626}
627
628void r600_polygon_offset_update(struct r600_context *rctx)
629{
630	struct r600_pipe_state state;
631
632	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
633	state.nregs = 0;
634	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
635		float offset_units = rctx->rasterizer->offset_units;
636		unsigned offset_db_fmt_cntl = 0, depth;
637
638		switch (rctx->framebuffer.zsbuf->texture->format) {
639		case PIPE_FORMAT_Z24X8_UNORM:
640		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
641			depth = -24;
642			offset_units *= 2.0f;
643			break;
644		case PIPE_FORMAT_Z32_FLOAT:
645		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
646			depth = -23;
647			offset_units *= 1.0f;
648			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
649			break;
650		case PIPE_FORMAT_Z16_UNORM:
651			depth = -16;
652			offset_units *= 4.0f;
653			break;
654		default:
655			return;
656		}
657		/* XXX some of those reg can be computed with cso */
658		offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
659		r600_pipe_state_add_reg(&state,
660				R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
661				fui(rctx->rasterizer->offset_scale));
662		r600_pipe_state_add_reg(&state,
663				R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
664				fui(offset_units));
665		r600_pipe_state_add_reg(&state,
666				R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
667				fui(rctx->rasterizer->offset_scale));
668		r600_pipe_state_add_reg(&state,
669				R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
670				fui(offset_units));
671		r600_pipe_state_add_reg(&state,
672				R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
673				offset_db_fmt_cntl);
674		r600_context_pipe_state_set(rctx, &state);
675	}
676}
677
678static void *r600_create_blend_state(struct pipe_context *ctx,
679					const struct pipe_blend_state *state)
680{
681	struct r600_context *rctx = (struct r600_context *)ctx;
682	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
683	struct r600_pipe_state *rstate;
684	uint32_t color_control = 0, target_mask;
685
686	if (blend == NULL) {
687		return NULL;
688	}
689	rstate = &blend->rstate;
690
691	rstate->id = R600_PIPE_STATE_BLEND;
692
693	target_mask = 0;
694
695	/* R600 does not support per-MRT blends */
696	if (rctx->family > CHIP_R600)
697		color_control |= S_028808_PER_MRT_BLEND(1);
698	if (state->logicop_enable) {
699		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
700	} else {
701		color_control |= (0xcc << 16);
702	}
703	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
704	if (state->independent_blend_enable) {
705		for (int i = 0; i < 8; i++) {
706			if (state->rt[i].blend_enable) {
707				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
708			}
709			target_mask |= (state->rt[i].colormask << (4 * i));
710		}
711	} else {
712		for (int i = 0; i < 8; i++) {
713			if (state->rt[0].blend_enable) {
714				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
715			}
716			target_mask |= (state->rt[0].colormask << (4 * i));
717		}
718	}
719	blend->cb_target_mask = target_mask;
720	blend->cb_color_control = color_control;
721	/* only MRT0 has dual src blend */
722	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
723	for (int i = 0; i < 8; i++) {
724		/* state->rt entries > 0 only written if independent blending */
725		const int j = state->independent_blend_enable ? i : 0;
726
727		unsigned eqRGB = state->rt[j].rgb_func;
728		unsigned srcRGB = state->rt[j].rgb_src_factor;
729		unsigned dstRGB = state->rt[j].rgb_dst_factor;
730
731		unsigned eqA = state->rt[j].alpha_func;
732		unsigned srcA = state->rt[j].alpha_src_factor;
733		unsigned dstA = state->rt[j].alpha_dst_factor;
734		uint32_t bc = 0;
735
736		if (!state->rt[j].blend_enable)
737			continue;
738
739		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
740		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
741		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
742
743		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
744			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
745			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
746			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
747			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
748		}
749
750		/* R600 does not support per-MRT blends */
751		if (rctx->family > CHIP_R600)
752			r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
753		if (i == 0)
754			r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
755	}
756	return rstate;
757}
758
759static void *r600_create_dsa_state(struct pipe_context *ctx,
760				   const struct pipe_depth_stencil_alpha_state *state)
761{
762	struct r600_context *rctx = (struct r600_context *)ctx;
763	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
764	unsigned db_depth_control, alpha_test_control, alpha_ref;
765	struct r600_pipe_state *rstate;
766
767	if (dsa == NULL) {
768		return NULL;
769	}
770
771	dsa->valuemask[0] = state->stencil[0].valuemask;
772	dsa->valuemask[1] = state->stencil[1].valuemask;
773	dsa->writemask[0] = state->stencil[0].writemask;
774	dsa->writemask[1] = state->stencil[1].writemask;
775
776	rstate = &dsa->rstate;
777
778	rstate->id = R600_PIPE_STATE_DSA;
779	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
780		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
781		S_028800_ZFUNC(state->depth.func);
782
783	/* stencil */
784	if (state->stencil[0].enabled) {
785		db_depth_control |= S_028800_STENCIL_ENABLE(1);
786		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
787		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
788		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
789		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
790
791		if (state->stencil[1].enabled) {
792			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
793			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
794			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
795			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
796			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
797		}
798	}
799
800	/* alpha */
801	alpha_test_control = 0;
802	alpha_ref = 0;
803	if (state->alpha.enabled) {
804		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
805		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
806		alpha_ref = fui(state->alpha.ref_value);
807	}
808	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
809	dsa->alpha_ref = alpha_ref;
810
811	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
812	return rstate;
813}
814
815static void *r600_create_rs_state(struct pipe_context *ctx,
816				  const struct pipe_rasterizer_state *state)
817{
818	struct r600_context *rctx = (struct r600_context *)ctx;
819	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
820	struct r600_pipe_state *rstate;
821	unsigned tmp;
822	unsigned prov_vtx = 1, polygon_dual_mode;
823	unsigned sc_mode_cntl;
824	float psize_min, psize_max;
825
826	if (rs == NULL) {
827		return NULL;
828	}
829
830	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
831				state->fill_back != PIPE_POLYGON_MODE_FILL);
832
833	if (state->flatshade_first)
834		prov_vtx = 0;
835
836	rstate = &rs->rstate;
837	rs->flatshade = state->flatshade;
838	rs->sprite_coord_enable = state->sprite_coord_enable;
839	rs->two_side = state->light_twoside;
840	rs->clip_plane_enable = state->clip_plane_enable;
841	rs->pa_sc_line_stipple = state->line_stipple_enable ?
842				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
843				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
844	rs->pa_cl_clip_cntl =
845		S_028810_PS_UCP_MODE(3) |
846		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
847		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
848		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
849
850	/* offset */
851	rs->offset_units = state->offset_units;
852	rs->offset_scale = state->offset_scale * 12.0f;
853
854	rstate->id = R600_PIPE_STATE_RASTERIZER;
855	tmp = S_0286D4_FLAT_SHADE_ENA(1);
856	if (state->sprite_coord_enable) {
857		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
858			S_0286D4_PNT_SPRITE_OVRD_X(2) |
859			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
860			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
861			S_0286D4_PNT_SPRITE_OVRD_W(1);
862		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
863			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
864		}
865	}
866	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
867
868	/* point size 12.4 fixed point */
869	tmp = r600_pack_float_12p4(state->point_size/2);
870	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
871
872	if (state->point_size_per_vertex) {
873		psize_min = util_get_min_point_size(state);
874		psize_max = 8192;
875	} else {
876		/* Force the point size to be as if the vertex output was disabled. */
877		psize_min = state->point_size;
878		psize_max = state->point_size;
879	}
880	/* Divide by two, because 0.5 = 1 pixel. */
881	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
882				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
883				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
884
885	tmp = r600_pack_float_12p4(state->line_width/2);
886	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
887
888	if (rctx->chip_class >= R700) {
889		sc_mode_cntl =
890			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
891			S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
892			S_028A4C_R700_ZMM_LINE_OFFSET(1) |
893			S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
894	} else {
895		sc_mode_cntl =
896			S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
897			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
898		rs->scissor_enable = state->scissor;
899	}
900	sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
901
902	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
903
904	r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
905				S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
906
907	r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
908	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
909				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
910				S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
911				S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
912				S_028814_FACE(!state->front_ccw) |
913				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
914				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
915				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
916				S_028814_POLY_MODE(polygon_dual_mode) |
917				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
918				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
919	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
920	return rstate;
921}
922
923static void *r600_create_sampler_state(struct pipe_context *ctx,
924					const struct pipe_sampler_state *state)
925{
926	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
927	struct r600_pipe_state *rstate;
928	union util_color uc;
929	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
930
931	if (ss == NULL) {
932		return NULL;
933	}
934
935	ss->seamless_cube_map = state->seamless_cube_map;
936	rstate = &ss->rstate;
937	rstate->id = R600_PIPE_STATE_SAMPLER;
938	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
939	r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
940					S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
941					S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
942					S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
943					S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
944					S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
945					S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
946					S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
947					S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
948					S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
949	r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
950					S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
951					S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
952					S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
953	r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
954	if (uc.ui) {
955		r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
956		r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
957		r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
958		r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
959	}
960	return rstate;
961}
962
963static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
964							struct pipe_resource *texture,
965							const struct pipe_sampler_view *state)
966{
967	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
968	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
969	struct r600_pipe_resource_state *rstate;
970	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
971	unsigned format, endian;
972	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
973	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
974	unsigned width, height, depth, offset_level, last_level;
975
976	if (view == NULL)
977		return NULL;
978	rstate = &view->state;
979
980	/* initialize base object */
981	view->base = *state;
982	view->base.texture = NULL;
983	pipe_reference(NULL, &texture->reference);
984	view->base.texture = texture;
985	view->base.reference.count = 1;
986	view->base.context = ctx;
987
988	swizzle[0] = state->swizzle_r;
989	swizzle[1] = state->swizzle_g;
990	swizzle[2] = state->swizzle_b;
991	swizzle[3] = state->swizzle_a;
992
993	format = r600_translate_texformat(ctx->screen, state->format,
994					  swizzle,
995					  &word4, &yuv_format);
996	if (format == ~0) {
997		format = 0;
998	}
999
1000	if (tmp->is_depth && !tmp->is_flushing_texture) {
1001	        r600_texture_depth_flush(ctx, texture, TRUE);
1002		tmp = tmp->flushed_depth_texture;
1003	}
1004
1005	endian = r600_colorformat_endian_swap(format);
1006
1007	offset_level = state->u.tex.first_level;
1008	last_level = state->u.tex.last_level - offset_level;
1009	if (!rscreen->use_surface_alloc) {
1010		width = u_minify(texture->width0, offset_level);
1011		height = u_minify(texture->height0, offset_level);
1012		depth = u_minify(texture->depth0, offset_level);
1013
1014		pitch = align(tmp->pitch_in_blocks[offset_level] *
1015				util_format_get_blockwidth(state->format), 8);
1016		array_mode = tmp->array_mode[offset_level];
1017		tile_type = tmp->tile_type;
1018
1019		if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1020			height = 1;
1021			depth = texture->array_size;
1022		} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1023			depth = texture->array_size;
1024		}
1025
1026		rstate->bo[0] = &tmp->resource;
1027		rstate->bo[1] = &tmp->resource;
1028		rstate->bo_usage[0] = RADEON_USAGE_READ;
1029		rstate->bo_usage[1] = RADEON_USAGE_READ;
1030
1031		rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1032				S_038000_TILE_MODE(array_mode) |
1033				S_038000_TILE_TYPE(tile_type) |
1034				S_038000_PITCH((pitch / 8) - 1) |
1035				S_038000_TEX_WIDTH(width - 1));
1036		rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1037				S_038004_TEX_DEPTH(depth - 1) |
1038				S_038004_DATA_FORMAT(format));
1039		rstate->val[2] = tmp->offset[offset_level] >> 8;
1040		rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1041		rstate->val[4] = (word4 |
1042				S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1043				S_038010_REQUEST_SIZE(1) |
1044				S_038010_ENDIAN_SWAP(endian) |
1045				S_038010_BASE_LEVEL(0));
1046		rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1047				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1048				S_038014_LAST_ARRAY(state->u.tex.last_layer));
1049		rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1050				S_038018_MAX_ANISO(4 /* max 16 samples */));
1051	} else {
1052		width = tmp->surface.level[offset_level].npix_x;
1053		height = tmp->surface.level[offset_level].npix_y;
1054		depth = tmp->surface.level[offset_level].npix_z;
1055		pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1056		tile_type = tmp->tile_type;
1057
1058		if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1059			height = 1;
1060			depth = texture->array_size;
1061		} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1062			depth = texture->array_size;
1063		}
1064		switch (tmp->surface.level[offset_level].mode) {
1065		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1066			array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1067			break;
1068		case RADEON_SURF_MODE_1D:
1069			array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1070			break;
1071		case RADEON_SURF_MODE_2D:
1072			array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1073			break;
1074		case RADEON_SURF_MODE_LINEAR:
1075		default:
1076			array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1077			break;
1078		}
1079
1080		rstate->bo[0] = &tmp->resource;
1081		rstate->bo[1] = &tmp->resource;
1082		rstate->bo_usage[0] = RADEON_USAGE_READ;
1083		rstate->bo_usage[1] = RADEON_USAGE_READ;
1084
1085		rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1086				S_038000_TILE_MODE(array_mode) |
1087				S_038000_TILE_TYPE(tile_type) |
1088				S_038000_PITCH((pitch / 8) - 1) |
1089				S_038000_TEX_WIDTH(width - 1));
1090		rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1091				S_038004_TEX_DEPTH(depth - 1) |
1092				S_038004_DATA_FORMAT(format));
1093		rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
1094		if (offset_level >= tmp->surface.last_level) {
1095			rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
1096		} else {
1097			rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1098		}
1099		rstate->val[4] = (word4 |
1100				S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1101				S_038010_REQUEST_SIZE(1) |
1102				S_038010_ENDIAN_SWAP(endian) |
1103				S_038010_BASE_LEVEL(0));
1104		rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1105				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1106				S_038014_LAST_ARRAY(state->u.tex.last_layer));
1107		rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1108				S_038018_MAX_ANISO(4 /* max 16 samples */));
1109	}
1110	return &view->base;
1111}
1112
1113static void r600_set_sampler_views(struct r600_context *rctx,
1114				   struct r600_textures_info *dst,
1115				   unsigned count,
1116				   struct pipe_sampler_view **views,
1117				   void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1118{
1119	struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1120	unsigned i;
1121
1122	if (count)
1123		r600_inval_texture_cache(rctx);
1124
1125	for (i = 0; i < count; i++) {
1126		if (rviews[i]) {
1127			if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth)
1128				rctx->have_depth_texture = true;
1129
1130			/* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1131			if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1132			     rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1133				dst->samplers_dirty = true;
1134
1135			set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1136		} else {
1137			set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1138		}
1139
1140		pipe_sampler_view_reference(
1141			(struct pipe_sampler_view **)&dst->views[i],
1142			views[i]);
1143	}
1144
1145	for (i = count; i < dst->n_views; i++) {
1146		if (dst->views[i]) {
1147			set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1148			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1149		}
1150	}
1151
1152	dst->n_views = count;
1153}
1154
1155static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1156				      struct pipe_sampler_view **views)
1157{
1158	struct r600_context *rctx = (struct r600_context *)ctx;
1159	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1160			       r600_context_pipe_state_set_vs_resource);
1161}
1162
1163static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1164				      struct pipe_sampler_view **views)
1165{
1166	struct r600_context *rctx = (struct r600_context *)ctx;
1167	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1168			       r600_context_pipe_state_set_ps_resource);
1169}
1170
1171static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1172{
1173	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1174	if (rstate == NULL)
1175		return;
1176
1177	rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1178	r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1179				(enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1180				S_009508_DISABLE_CUBE_ANISO(1) |
1181				S_009508_SYNC_GRADIENT(1) |
1182				S_009508_SYNC_WALKER(1) |
1183				S_009508_SYNC_ALIGNER(1));
1184
1185	free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1186	rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1187	r600_context_pipe_state_set(rctx, rstate);
1188}
1189
1190static void r600_bind_samplers(struct r600_context *rctx,
1191			       struct r600_textures_info *dst,
1192			       unsigned count, void **states)
1193{
1194	memcpy(dst->samplers, states, sizeof(void*) * count);
1195	dst->n_samplers = count;
1196	dst->samplers_dirty = true;
1197}
1198
1199static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1200{
1201	struct r600_context *rctx = (struct r600_context *)ctx;
1202	r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1203}
1204
1205static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1206{
1207	struct r600_context *rctx = (struct r600_context *)ctx;
1208	r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1209}
1210
1211static void r600_update_samplers(struct r600_context *rctx,
1212				 struct r600_textures_info *tex,
1213				 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1214{
1215	unsigned i;
1216
1217	if (tex->samplers_dirty) {
1218		int seamless = -1;
1219		for (i = 0; i < tex->n_samplers; i++) {
1220			if (!tex->samplers[i])
1221				continue;
1222
1223			/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1224			 * filtering between layers.
1225			 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1226			if (tex->views[i]) {
1227				if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1228				    tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1229					tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1230					tex->is_array_sampler[i] = true;
1231				} else {
1232					tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1233					tex->is_array_sampler[i] = false;
1234				}
1235			}
1236
1237			set_sampler(rctx, &tex->samplers[i]->rstate, i);
1238
1239			if (tex->samplers[i])
1240				seamless = tex->samplers[i]->seamless_cube_map;
1241		}
1242
1243		if (seamless != -1)
1244			r600_set_seamless_cubemap(rctx, seamless);
1245
1246		tex->samplers_dirty = false;
1247	}
1248}
1249
1250void r600_update_sampler_states(struct r600_context *rctx)
1251{
1252	r600_update_samplers(rctx, &rctx->vs_samplers,
1253			     r600_context_pipe_state_set_vs_sampler);
1254	r600_update_samplers(rctx, &rctx->ps_samplers,
1255			     r600_context_pipe_state_set_ps_sampler);
1256}
1257
1258static void r600_set_clip_state(struct pipe_context *ctx,
1259				const struct pipe_clip_state *state)
1260{
1261	struct r600_context *rctx = (struct r600_context *)ctx;
1262	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1263	struct pipe_constant_buffer cb;
1264
1265	if (rstate == NULL)
1266		return;
1267
1268	rctx->clip = *state;
1269	rstate->id = R600_PIPE_STATE_CLIP;
1270	for (int i = 0; i < 6; i++) {
1271		r600_pipe_state_add_reg(rstate,
1272					R_028E20_PA_CL_UCP0_X + i * 16,
1273					fui(state->ucp[i][0]));
1274		r600_pipe_state_add_reg(rstate,
1275					R_028E24_PA_CL_UCP0_Y + i * 16,
1276					fui(state->ucp[i][1]) );
1277		r600_pipe_state_add_reg(rstate,
1278					R_028E28_PA_CL_UCP0_Z + i * 16,
1279					fui(state->ucp[i][2]));
1280		r600_pipe_state_add_reg(rstate,
1281					R_028E2C_PA_CL_UCP0_W + i * 16,
1282					fui(state->ucp[i][3]));
1283	}
1284
1285	free(rctx->states[R600_PIPE_STATE_CLIP]);
1286	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1287	r600_context_pipe_state_set(rctx, rstate);
1288
1289	cb.buffer = NULL;
1290	cb.user_buffer = state->ucp;
1291	cb.buffer_offset = 0;
1292	cb.buffer_size = 4*4*8;
1293	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1294	pipe_resource_reference(&cb.buffer, NULL);
1295}
1296
1297static void r600_set_polygon_stipple(struct pipe_context *ctx,
1298					 const struct pipe_poly_stipple *state)
1299{
1300}
1301
1302static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1303{
1304}
1305
1306void r600_set_scissor_state(struct r600_context *rctx,
1307			    const struct pipe_scissor_state *state)
1308{
1309	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1310	uint32_t tl, br;
1311
1312	if (rstate == NULL)
1313		return;
1314
1315	rstate->id = R600_PIPE_STATE_SCISSOR;
1316	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1317	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1318	r600_pipe_state_add_reg(rstate,
1319				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1320	r600_pipe_state_add_reg(rstate,
1321				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1322
1323	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1324	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1325	r600_context_pipe_state_set(rctx, rstate);
1326}
1327
1328static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1329					const struct pipe_scissor_state *state)
1330{
1331	struct r600_context *rctx = (struct r600_context *)ctx;
1332
1333	if (rctx->chip_class == R600) {
1334		rctx->scissor_state = *state;
1335
1336		if (!rctx->scissor_enable)
1337			return;
1338	}
1339
1340	r600_set_scissor_state(rctx, state);
1341}
1342
1343static void r600_set_viewport_state(struct pipe_context *ctx,
1344					const struct pipe_viewport_state *state)
1345{
1346	struct r600_context *rctx = (struct r600_context *)ctx;
1347	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1348
1349	if (rstate == NULL)
1350		return;
1351
1352	rctx->viewport = *state;
1353	rstate->id = R600_PIPE_STATE_VIEWPORT;
1354	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1355	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1356	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1357	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1358	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1359	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1360
1361	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1362	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1363	r600_context_pipe_state_set(rctx, rstate);
1364}
1365
1366static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1367			const struct pipe_framebuffer_state *state, int cb)
1368{
1369	struct r600_screen *rscreen = rctx->screen;
1370	struct r600_resource_texture *rtex;
1371	struct r600_surface *surf;
1372	unsigned level = state->cbufs[cb]->u.tex.level;
1373	unsigned pitch, slice;
1374	unsigned color_info;
1375	unsigned format, swap, ntype, endian;
1376	unsigned offset;
1377	const struct util_format_description *desc;
1378	int i;
1379	unsigned blend_bypass = 0, blend_clamp = 1;
1380
1381	surf = (struct r600_surface *)state->cbufs[cb];
1382	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1383
1384	if (rtex->is_depth)
1385		rctx->have_depth_fb = TRUE;
1386
1387	if (rtex->is_depth && !rtex->is_flushing_texture) {
1388		rtex = rtex->flushed_depth_texture;
1389	}
1390
1391	/* XXX quite sure for dx10+ hw don't need any offset hacks */
1392	if (!rscreen->use_surface_alloc) {
1393		offset = r600_texture_get_offset(rtex,
1394						 level, state->cbufs[cb]->u.tex.first_layer);
1395		pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1396		slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1397		if (slice) {
1398			slice = slice - 1;
1399		}
1400		color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1401	} else {
1402		offset = rtex->surface.level[level].offset;
1403		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1404			offset += rtex->surface.level[level].slice_size *
1405				  state->cbufs[cb]->u.tex.first_layer;
1406		}
1407		pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1408		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1409		if (slice) {
1410			slice = slice - 1;
1411		}
1412		color_info = 0;
1413		switch (rtex->surface.level[level].mode) {
1414		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1415			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1416			break;
1417		case RADEON_SURF_MODE_1D:
1418			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1419			break;
1420		case RADEON_SURF_MODE_2D:
1421			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1422			break;
1423		case RADEON_SURF_MODE_LINEAR:
1424		default:
1425			color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1426			break;
1427		}
1428	}
1429	desc = util_format_description(surf->base.format);
1430
1431	for (i = 0; i < 4; i++) {
1432		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1433			break;
1434		}
1435	}
1436
1437	ntype = V_0280A0_NUMBER_UNORM;
1438	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1439		ntype = V_0280A0_NUMBER_SRGB;
1440	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1441		if (desc->channel[i].normalized)
1442			ntype = V_0280A0_NUMBER_SNORM;
1443		else if (desc->channel[i].pure_integer)
1444			ntype = V_0280A0_NUMBER_SINT;
1445	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1446		if (desc->channel[i].normalized)
1447			ntype = V_0280A0_NUMBER_UNORM;
1448		else if (desc->channel[i].pure_integer)
1449			ntype = V_0280A0_NUMBER_UINT;
1450	}
1451
1452	format = r600_translate_colorformat(surf->base.format);
1453	swap = r600_translate_colorswap(surf->base.format);
1454	if(rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1455		endian = ENDIAN_NONE;
1456	} else {
1457		endian = r600_colorformat_endian_swap(format);
1458	}
1459
1460	/* set blend bypass according to docs if SINT/UINT or
1461	   8/24 COLOR variants */
1462	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1463	    format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1464	    format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1465		blend_clamp = 0;
1466		blend_bypass = 1;
1467	}
1468
1469	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
1470		rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1471	else
1472		rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1473
1474	color_info |= S_0280A0_FORMAT(format) |
1475		S_0280A0_COMP_SWAP(swap) |
1476		S_0280A0_BLEND_BYPASS(blend_bypass) |
1477		S_0280A0_BLEND_CLAMP(blend_clamp) |
1478		S_0280A0_NUMBER_TYPE(ntype) |
1479		S_0280A0_ENDIAN(endian);
1480
1481	/* EXPORT_NORM is an optimzation that can be enabled for better
1482	 * performance in certain cases
1483	 */
1484	if (rctx->chip_class == R600) {
1485		/* EXPORT_NORM can be enabled if:
1486		 * - 11-bit or smaller UNORM/SNORM/SRGB
1487		 * - BLEND_CLAMP is enabled
1488		 * - BLEND_FLOAT32 is disabled
1489		 */
1490		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1491		    (desc->channel[i].size < 12 &&
1492		     desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1493		     ntype != V_0280A0_NUMBER_UINT &&
1494		     ntype != V_0280A0_NUMBER_SINT) &&
1495		    G_0280A0_BLEND_CLAMP(color_info) &&
1496		    !G_0280A0_BLEND_FLOAT32(color_info))
1497			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1498	} else {
1499		/* EXPORT_NORM can be enabled if:
1500		 * - 11-bit or smaller UNORM/SNORM/SRGB
1501		 * - 16-bit or smaller FLOAT
1502		 */
1503		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1504		    ((desc->channel[i].size < 12 &&
1505		      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1506		      ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1507		    (desc->channel[i].size < 17 &&
1508		     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1509			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1510	}
1511
1512	if (cb == 0)
1513		rctx->color0_format = color_info;
1514
1515	r600_pipe_state_add_reg_bo(rstate,
1516				R_028040_CB_COLOR0_BASE + cb * 4,
1517				offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1518	r600_pipe_state_add_reg_bo(rstate,
1519				R_0280A0_CB_COLOR0_INFO + cb * 4,
1520				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1521	r600_pipe_state_add_reg(rstate,
1522				R_028060_CB_COLOR0_SIZE + cb * 4,
1523				S_028060_PITCH_TILE_MAX(pitch) |
1524				S_028060_SLICE_TILE_MAX(slice));
1525	if (!rscreen->use_surface_alloc) {
1526		r600_pipe_state_add_reg(rstate,
1527					R_028080_CB_COLOR0_VIEW + cb * 4,
1528					0x00000000);
1529	} else {
1530		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1531			r600_pipe_state_add_reg(rstate,
1532						R_028080_CB_COLOR0_VIEW + cb * 4,
1533						0x00000000);
1534		} else {
1535			r600_pipe_state_add_reg(rstate,
1536						R_028080_CB_COLOR0_VIEW + cb * 4,
1537						S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1538						S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1539		}
1540	}
1541	r600_pipe_state_add_reg_bo(rstate,
1542				   R_0280E0_CB_COLOR0_FRAG + cb * 4,
1543				   0, &rtex->resource, RADEON_USAGE_READWRITE);
1544	r600_pipe_state_add_reg_bo(rstate,
1545				   R_0280C0_CB_COLOR0_TILE + cb * 4,
1546				   0, &rtex->resource, RADEON_USAGE_READWRITE);
1547}
1548
1549static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1550			const struct pipe_framebuffer_state *state)
1551{
1552	struct r600_screen *rscreen = rctx->screen;
1553	struct r600_resource_texture *rtex;
1554	struct r600_surface *surf;
1555	unsigned level, pitch, slice, format, offset, array_mode;
1556
1557	if (state->zsbuf == NULL)
1558		return;
1559
1560	level = state->zsbuf->u.tex.level;
1561
1562	surf = (struct r600_surface *)state->zsbuf;
1563	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1564
1565	if (!rscreen->use_surface_alloc) {
1566		/* XXX remove this once tiling is properly supported */
1567		array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1568			V_0280A0_ARRAY_1D_TILED_THIN1;
1569
1570		/* XXX quite sure for dx10+ hw don't need any offset hacks */
1571		offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1572				level, state->zsbuf->u.tex.first_layer);
1573		pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1574		slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1575		if (slice) {
1576			slice = slice - 1;
1577		}
1578	} else {
1579		offset = rtex->surface.level[level].offset;
1580		pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1581		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1582		if (slice) {
1583			slice = slice - 1;
1584		}
1585		switch (rtex->surface.level[level].mode) {
1586		case RADEON_SURF_MODE_2D:
1587			array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1588			break;
1589		case RADEON_SURF_MODE_1D:
1590		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1591		case RADEON_SURF_MODE_LINEAR:
1592		default:
1593			array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1594			break;
1595		}
1596	}
1597
1598	format = r600_translate_dbformat(state->zsbuf->texture->format);
1599
1600	r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
1601				offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1602	r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1603				S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
1604	if (!rscreen->use_surface_alloc) {
1605		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
1606	} else {
1607		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1608					S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1609					S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1610	}
1611	r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
1612				S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1613				&rtex->resource, RADEON_USAGE_READWRITE);
1614	r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1615				(surf->aligned_height / 8) - 1);
1616}
1617
1618static void r600_set_framebuffer_state(struct pipe_context *ctx,
1619					const struct pipe_framebuffer_state *state)
1620{
1621	struct r600_context *rctx = (struct r600_context *)ctx;
1622	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1623	uint32_t tl, br, shader_control;
1624
1625	if (rstate == NULL)
1626		return;
1627
1628	r600_flush_framebuffer(rctx, false);
1629
1630	/* unreference old buffer and reference new one */
1631	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1632
1633	util_copy_framebuffer_state(&rctx->framebuffer, state);
1634
1635	/* build states */
1636	rctx->have_depth_fb = 0;
1637	for (int i = 0; i < state->nr_cbufs; i++) {
1638		r600_cb(rctx, rstate, state, i);
1639	}
1640	if (state->zsbuf) {
1641		r600_db(rctx, rstate, state);
1642	}
1643
1644	shader_control = 0;
1645	rctx->fb_cb_shader_mask = 0;
1646	for (int i = 0; i < state->nr_cbufs; i++) {
1647		shader_control |= 1 << i;
1648		rctx->fb_cb_shader_mask |= 0xf << (i * 4);
1649	}
1650	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1651	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1652
1653	r600_pipe_state_add_reg(rstate,
1654				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1655	r600_pipe_state_add_reg(rstate,
1656				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1657
1658	r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1659				shader_control);
1660
1661	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1662	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1663	r600_context_pipe_state_set(rctx, rstate);
1664
1665	if (state->zsbuf) {
1666		r600_polygon_offset_update(rctx);
1667	}
1668}
1669
1670static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1671{
1672	struct radeon_winsys_cs *cs = rctx->cs;
1673	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1674	unsigned db_render_control = 0;
1675	unsigned db_render_override =
1676		S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1677		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1678		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1679
1680	if (a->occlusion_query_enabled) {
1681		if (rctx->chip_class >= R700) {
1682			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1683		}
1684		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1685	}
1686	if (a->flush_depthstencil_enabled) {
1687		db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
1688				     S_028D0C_STENCIL_COPY_ENABLE(1) |
1689				     S_028D0C_COPY_CENTROID(1);
1690	}
1691
1692	r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1693	r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1694	r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1695}
1696
1697static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1698{
1699	struct radeon_winsys_cs *cs = rctx->cs;
1700	struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1701	unsigned count = rctx->nr_vertex_buffers;
1702	unsigned i, offset;
1703
1704	for (i = 0; i < count; i++) {
1705		struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1706
1707		if (!rbuffer) {
1708			continue;
1709		}
1710
1711		offset = vb[i].buffer_offset;
1712
1713		/* fetch resources start at index 320 */
1714		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1715		r600_write_value(cs, (320 + i) * 7);
1716		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1717		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1718		r600_write_value(cs, /* RESOURCEi_WORD2 */
1719				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1720				 S_038008_STRIDE(vb[i].stride));
1721		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1722		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1723		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1724		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1725
1726		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1727		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1728	}
1729}
1730
1731static void r600_emit_constant_buffers(struct r600_context *rctx,
1732				       struct r600_constbuf_state *state,
1733				       unsigned buffer_id_base,
1734				       unsigned reg_alu_constbuf_size,
1735				       unsigned reg_alu_const_cache)
1736{
1737	struct radeon_winsys_cs *cs = rctx->cs;
1738	uint32_t dirty_mask = state->dirty_mask;
1739
1740	while (dirty_mask) {
1741		struct pipe_constant_buffer *cb;
1742		struct r600_resource *rbuffer;
1743		unsigned offset;
1744		unsigned buffer_index = ffs(dirty_mask) - 1;
1745
1746		cb = &state->cb[buffer_index];
1747		rbuffer = (struct r600_resource*)cb->buffer;
1748		assert(rbuffer);
1749
1750		offset = cb->buffer_offset;
1751
1752		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1753				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1754		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1755
1756		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1757		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1758
1759		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1760		r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1761		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1762		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1763		r600_write_value(cs, /* RESOURCEi_WORD2 */
1764				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1765				 S_038008_STRIDE(16));
1766		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1767		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1768		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1769		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1770
1771		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1772		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1773
1774		dirty_mask &= ~(1 << buffer_index);
1775	}
1776	state->dirty_mask = 0;
1777}
1778
1779static void r600_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1780{
1781	r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1782				   R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1783				   R_028980_ALU_CONST_CACHE_VS_0);
1784}
1785
1786static void r600_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1787{
1788	r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1789				   R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1790				   R_028940_ALU_CONST_CACHE_PS_0);
1791}
1792
1793void r600_init_state_functions(struct r600_context *rctx)
1794{
1795	r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1796	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1797	r600_init_atom(&rctx->vertex_buffer_state, r600_emit_vertex_buffers, 0, 0);
1798	r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffer, 0, 0);
1799	r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffer, 0, 0);
1800
1801	rctx->context.create_blend_state = r600_create_blend_state;
1802	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1803	rctx->context.create_fs_state = r600_create_shader_state;
1804	rctx->context.create_rasterizer_state = r600_create_rs_state;
1805	rctx->context.create_sampler_state = r600_create_sampler_state;
1806	rctx->context.create_sampler_view = r600_create_sampler_view;
1807	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1808	rctx->context.create_vs_state = r600_create_shader_state;
1809	rctx->context.bind_blend_state = r600_bind_blend_state;
1810	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1811	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1812	rctx->context.bind_fs_state = r600_bind_ps_shader;
1813	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1814	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1815	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1816	rctx->context.bind_vs_state = r600_bind_vs_shader;
1817	rctx->context.delete_blend_state = r600_delete_state;
1818	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1819	rctx->context.delete_fs_state = r600_delete_ps_shader;
1820	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1821	rctx->context.delete_sampler_state = r600_delete_state;
1822	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1823	rctx->context.delete_vs_state = r600_delete_vs_shader;
1824	rctx->context.set_blend_color = r600_set_blend_color;
1825	rctx->context.set_clip_state = r600_set_clip_state;
1826	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1827	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1828	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1829	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1830	rctx->context.set_sample_mask = r600_set_sample_mask;
1831	rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1832	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1833	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1834	rctx->context.set_index_buffer = r600_set_index_buffer;
1835	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1836	rctx->context.set_viewport_state = r600_set_viewport_state;
1837	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1838	rctx->context.texture_barrier = r600_texture_barrier;
1839	rctx->context.create_stream_output_target = r600_create_so_target;
1840	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1841	rctx->context.set_stream_output_targets = r600_set_so_targets;
1842}
1843
1844void r600_adjust_gprs(struct r600_context *rctx)
1845{
1846	struct r600_pipe_state rstate;
1847	unsigned num_ps_gprs = rctx->default_ps_gprs;
1848	unsigned num_vs_gprs = rctx->default_vs_gprs;
1849	unsigned tmp;
1850	int diff;
1851
1852	if (rctx->chip_class >= EVERGREEN)
1853		return;
1854
1855	if (!rctx->ps_shader || !rctx->vs_shader)
1856		return;
1857
1858	if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1859	{
1860		diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1861		num_vs_gprs -= diff;
1862		num_ps_gprs += diff;
1863	}
1864
1865	if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1866	{
1867		diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1868		num_ps_gprs -= diff;
1869		num_vs_gprs += diff;
1870	}
1871
1872	tmp = 0;
1873	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1874	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1875	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1876	rstate.nregs = 0;
1877	r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1878
1879	r600_context_pipe_state_set(rctx, &rstate);
1880}
1881
1882void r600_init_atom_start_cs(struct r600_context *rctx)
1883{
1884	int ps_prio;
1885	int vs_prio;
1886	int gs_prio;
1887	int es_prio;
1888	int num_ps_gprs;
1889	int num_vs_gprs;
1890	int num_gs_gprs;
1891	int num_es_gprs;
1892	int num_temp_gprs;
1893	int num_ps_threads;
1894	int num_vs_threads;
1895	int num_gs_threads;
1896	int num_es_threads;
1897	int num_ps_stack_entries;
1898	int num_vs_stack_entries;
1899	int num_gs_stack_entries;
1900	int num_es_stack_entries;
1901	enum radeon_family family;
1902	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1903	uint32_t tmp;
1904	unsigned i;
1905
1906	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1907
1908	/* R6xx requires this packet at the start of each command buffer */
1909	if (rctx->chip_class == R600) {
1910		r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1911		r600_store_value(cb, 0);
1912	}
1913	/* All asics require this one */
1914	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1915	r600_store_value(cb, 0x80000000);
1916	r600_store_value(cb, 0x80000000);
1917
1918	family = rctx->family;
1919	ps_prio = 0;
1920	vs_prio = 1;
1921	gs_prio = 2;
1922	es_prio = 3;
1923	switch (family) {
1924	case CHIP_R600:
1925		num_ps_gprs = 192;
1926		num_vs_gprs = 56;
1927		num_temp_gprs = 4;
1928		num_gs_gprs = 0;
1929		num_es_gprs = 0;
1930		num_ps_threads = 136;
1931		num_vs_threads = 48;
1932		num_gs_threads = 4;
1933		num_es_threads = 4;
1934		num_ps_stack_entries = 128;
1935		num_vs_stack_entries = 128;
1936		num_gs_stack_entries = 0;
1937		num_es_stack_entries = 0;
1938		break;
1939	case CHIP_RV630:
1940	case CHIP_RV635:
1941		num_ps_gprs = 84;
1942		num_vs_gprs = 36;
1943		num_temp_gprs = 4;
1944		num_gs_gprs = 0;
1945		num_es_gprs = 0;
1946		num_ps_threads = 144;
1947		num_vs_threads = 40;
1948		num_gs_threads = 4;
1949		num_es_threads = 4;
1950		num_ps_stack_entries = 40;
1951		num_vs_stack_entries = 40;
1952		num_gs_stack_entries = 32;
1953		num_es_stack_entries = 16;
1954		break;
1955	case CHIP_RV610:
1956	case CHIP_RV620:
1957	case CHIP_RS780:
1958	case CHIP_RS880:
1959	default:
1960		num_ps_gprs = 84;
1961		num_vs_gprs = 36;
1962		num_temp_gprs = 4;
1963		num_gs_gprs = 0;
1964		num_es_gprs = 0;
1965		num_ps_threads = 136;
1966		num_vs_threads = 48;
1967		num_gs_threads = 4;
1968		num_es_threads = 4;
1969		num_ps_stack_entries = 40;
1970		num_vs_stack_entries = 40;
1971		num_gs_stack_entries = 32;
1972		num_es_stack_entries = 16;
1973		break;
1974	case CHIP_RV670:
1975		num_ps_gprs = 144;
1976		num_vs_gprs = 40;
1977		num_temp_gprs = 4;
1978		num_gs_gprs = 0;
1979		num_es_gprs = 0;
1980		num_ps_threads = 136;
1981		num_vs_threads = 48;
1982		num_gs_threads = 4;
1983		num_es_threads = 4;
1984		num_ps_stack_entries = 40;
1985		num_vs_stack_entries = 40;
1986		num_gs_stack_entries = 32;
1987		num_es_stack_entries = 16;
1988		break;
1989	case CHIP_RV770:
1990		num_ps_gprs = 192;
1991		num_vs_gprs = 56;
1992		num_temp_gprs = 4;
1993		num_gs_gprs = 0;
1994		num_es_gprs = 0;
1995		num_ps_threads = 188;
1996		num_vs_threads = 60;
1997		num_gs_threads = 0;
1998		num_es_threads = 0;
1999		num_ps_stack_entries = 256;
2000		num_vs_stack_entries = 256;
2001		num_gs_stack_entries = 0;
2002		num_es_stack_entries = 0;
2003		break;
2004	case CHIP_RV730:
2005	case CHIP_RV740:
2006		num_ps_gprs = 84;
2007		num_vs_gprs = 36;
2008		num_temp_gprs = 4;
2009		num_gs_gprs = 0;
2010		num_es_gprs = 0;
2011		num_ps_threads = 188;
2012		num_vs_threads = 60;
2013		num_gs_threads = 0;
2014		num_es_threads = 0;
2015		num_ps_stack_entries = 128;
2016		num_vs_stack_entries = 128;
2017		num_gs_stack_entries = 0;
2018		num_es_stack_entries = 0;
2019		break;
2020	case CHIP_RV710:
2021		num_ps_gprs = 192;
2022		num_vs_gprs = 56;
2023		num_temp_gprs = 4;
2024		num_gs_gprs = 0;
2025		num_es_gprs = 0;
2026		num_ps_threads = 144;
2027		num_vs_threads = 48;
2028		num_gs_threads = 0;
2029		num_es_threads = 0;
2030		num_ps_stack_entries = 128;
2031		num_vs_stack_entries = 128;
2032		num_gs_stack_entries = 0;
2033		num_es_stack_entries = 0;
2034		break;
2035	}
2036
2037	rctx->default_ps_gprs = num_ps_gprs;
2038	rctx->default_vs_gprs = num_vs_gprs;
2039	rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2040
2041	/* SQ_CONFIG */
2042	tmp = 0;
2043	switch (family) {
2044	case CHIP_RV610:
2045	case CHIP_RV620:
2046	case CHIP_RS780:
2047	case CHIP_RS880:
2048	case CHIP_RV710:
2049		break;
2050	default:
2051		tmp |= S_008C00_VC_ENABLE(1);
2052		break;
2053	}
2054	tmp |= S_008C00_DX9_CONSTS(0);
2055	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2056	tmp |= S_008C00_PS_PRIO(ps_prio);
2057	tmp |= S_008C00_VS_PRIO(vs_prio);
2058	tmp |= S_008C00_GS_PRIO(gs_prio);
2059	tmp |= S_008C00_ES_PRIO(es_prio);
2060	r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2061
2062	/* SQ_GPR_RESOURCE_MGMT_2 */
2063	tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2064	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2065	r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2066	r600_store_value(cb, tmp);
2067
2068	/* SQ_THREAD_RESOURCE_MGMT */
2069	tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2070	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2071	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2072	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2073	r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2074
2075	/* SQ_STACK_RESOURCE_MGMT_1 */
2076	tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2077	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2078	r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2079
2080	/* SQ_STACK_RESOURCE_MGMT_2 */
2081	tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2082	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2083	r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2084
2085	r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2086
2087	if (rctx->chip_class >= R700) {
2088		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2089		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2090		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2091		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2092	} else {
2093		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2094		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2095		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2096		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2097	}
2098	r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2099	r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2100	r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2101	r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2102	r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2103	r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2104	r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2105	r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2106	r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2107	r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2108
2109	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2110	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2111	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2112	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2113	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2114	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2115	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2116	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2117	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2118	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2119	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2120	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2121	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2122	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2123
2124	r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2125	r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2126	r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2127
2128	r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2129	r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2130	r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2131	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2132
2133	r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2134
2135	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2136	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2137	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2138
2139	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2140
2141	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2142	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2143	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2144
2145	r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2146	r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2147	r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2148	r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2149
2150	r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2151	r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2152	r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2153
2154	r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
2155
2156	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2157	r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2158
2159	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2160	r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2161	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2162
2163	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2164	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2165	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2166	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2167	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2168	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2169	r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2170
2171	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2172	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2173	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2174
2175	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2176
2177	r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2178	for (i = 0; i < 8; i++) {
2179		r600_store_value(cb, 0);
2180	}
2181
2182	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2183	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2184
2185	if (rctx->chip_class >= R700) {
2186		r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2187	}
2188
2189	r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2190	r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2191	r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2192	r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2193	r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2194
2195	r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
2196
2197	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2198	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2199	r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2200
2201	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2202	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2203	r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2204
2205	r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2206	r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2207	r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2208
2209	r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2210	r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2211
2212	if (rctx->chip_class == R700 && rctx->screen->info.r600_has_streamout)
2213		r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2214	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2215
2216	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2217	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2218}
2219
2220void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2221{
2222	struct r600_context *rctx = (struct r600_context *)ctx;
2223	struct r600_pipe_state *rstate = &shader->rstate;
2224	struct r600_shader *rshader = &shader->shader;
2225	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2226	int pos_index = -1, face_index = -1;
2227	unsigned tmp, sid, ufi = 0;
2228	int need_linear = 0;
2229
2230	rstate->nregs = 0;
2231
2232	for (i = 0; i < rshader->ninput; i++) {
2233		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2234			pos_index = i;
2235		if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2236			face_index = i;
2237
2238		sid = rshader->input[i].spi_sid;
2239
2240		tmp = S_028644_SEMANTIC(sid);
2241
2242		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2243			rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2244			(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2245				rctx->rasterizer && rctx->rasterizer->flatshade))
2246			tmp |= S_028644_FLAT_SHADE(1);
2247
2248		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2249				rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2250			tmp |= S_028644_PT_SPRITE_TEX(1);
2251		}
2252
2253		if (rshader->input[i].centroid)
2254			tmp |= S_028644_SEL_CENTROID(1);
2255
2256		if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2257			need_linear = 1;
2258			tmp |= S_028644_SEL_LINEAR(1);
2259		}
2260
2261		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2262				tmp);
2263	}
2264
2265	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2266	for (i = 0; i < rshader->noutput; i++) {
2267		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2268			db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2269		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2270			db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2271	}
2272	if (rshader->uses_kill)
2273		db_shader_control |= S_02880C_KILL_ENABLE(1);
2274
2275	exports_ps = 0;
2276	num_cout = 0;
2277	for (i = 0; i < rshader->noutput; i++) {
2278		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2279		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2280			exports_ps |= 1;
2281		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2282			num_cout++;
2283		}
2284	}
2285	exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2286	if (!exports_ps) {
2287		/* always at least export 1 component per pixel */
2288		exports_ps = 2;
2289	}
2290
2291	shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
2292
2293	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2294				S_0286CC_PERSP_GRADIENT_ENA(1)|
2295				S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2296	spi_input_z = 0;
2297	if (pos_index != -1) {
2298		spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2299					S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2300					S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2301					S_0286CC_BARYC_SAMPLE_CNTL(1));
2302		spi_input_z |= 1;
2303	}
2304
2305	spi_ps_in_control_1 = 0;
2306	if (face_index != -1) {
2307		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2308			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2309	}
2310
2311	/* HW bug in original R600 */
2312	if (rctx->family == CHIP_R600)
2313		ufi = 1;
2314
2315	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2316	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2317	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2318	r600_pipe_state_add_reg_bo(rstate,
2319				   R_028840_SQ_PGM_START_PS,
2320				   0, shader->bo, RADEON_USAGE_READ);
2321	r600_pipe_state_add_reg(rstate,
2322				R_028850_SQ_PGM_RESOURCES_PS,
2323				S_028850_NUM_GPRS(rshader->bc.ngpr) |
2324				S_028850_STACK_SIZE(rshader->bc.nstack) |
2325				S_028850_UNCACHED_FIRST_INST(ufi));
2326	r600_pipe_state_add_reg(rstate,
2327				R_028854_SQ_PGM_EXPORTS_PS,
2328				exports_ps);
2329	/* only set some bits here, the other bits are set in the dsa state */
2330	r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2331				db_shader_control);
2332
2333	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2334	if (rctx->rasterizer)
2335		shader->flatshade = rctx->rasterizer->flatshade;
2336}
2337
2338void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2339{
2340	struct r600_context *rctx = (struct r600_context *)ctx;
2341	struct r600_pipe_state *rstate = &shader->rstate;
2342	struct r600_shader *rshader = &shader->shader;
2343	unsigned spi_vs_out_id[10] = {};
2344	unsigned i, tmp, nparams = 0;
2345
2346	/* clear previous register */
2347	rstate->nregs = 0;
2348
2349	for (i = 0; i < rshader->noutput; i++) {
2350		if (rshader->output[i].spi_sid) {
2351			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2352			spi_vs_out_id[nparams / 4] |= tmp;
2353			nparams++;
2354		}
2355	}
2356
2357	for (i = 0; i < 10; i++) {
2358		r600_pipe_state_add_reg(rstate,
2359					R_028614_SPI_VS_OUT_ID_0 + i * 4,
2360					spi_vs_out_id[i]);
2361	}
2362
2363	/* Certain attributes (position, psize, etc.) don't count as params.
2364	 * VS is required to export at least one param and r600_shader_from_tgsi()
2365	 * takes care of adding a dummy export.
2366	 */
2367	if (nparams < 1)
2368		nparams = 1;
2369
2370	r600_pipe_state_add_reg(rstate,
2371				R_0286C4_SPI_VS_OUT_CONFIG,
2372				S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2373	r600_pipe_state_add_reg(rstate,
2374				R_028868_SQ_PGM_RESOURCES_VS,
2375				S_028868_NUM_GPRS(rshader->bc.ngpr) |
2376				S_028868_STACK_SIZE(rshader->bc.nstack));
2377	r600_pipe_state_add_reg_bo(rstate,
2378			R_028858_SQ_PGM_START_VS,
2379			0, shader->bo, RADEON_USAGE_READ);
2380
2381	shader->pa_cl_vs_out_cntl =
2382		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2383		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2384		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2385		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2386}
2387
2388void r600_fetch_shader(struct pipe_context *ctx,
2389		       struct r600_vertex_element *ve)
2390{
2391	struct r600_pipe_state *rstate;
2392	struct r600_context *rctx = (struct r600_context *)ctx;
2393
2394	rstate = &ve->rstate;
2395	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2396	rstate->nregs = 0;
2397	r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2398				0,
2399				ve->fetch_shader, RADEON_USAGE_READ);
2400}
2401
2402void *r600_create_db_flush_dsa(struct r600_context *rctx)
2403{
2404	struct pipe_depth_stencil_alpha_state dsa;
2405	struct r600_pipe_state *rstate;
2406	struct r600_pipe_dsa *dsa_state;
2407	boolean quirk = false;
2408
2409	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2410		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2411		quirk = true;
2412
2413	memset(&dsa, 0, sizeof(dsa));
2414
2415	if (quirk) {
2416		dsa.depth.enabled = 1;
2417		dsa.depth.func = PIPE_FUNC_LEQUAL;
2418		dsa.stencil[0].enabled = 1;
2419		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2420		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2421		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2422		dsa.stencil[0].writemask = 0xff;
2423	}
2424
2425	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2426	dsa_state = (struct r600_pipe_dsa*)rstate;
2427	dsa_state->is_flush = true;
2428	return rstate;
2429}
2430