1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33#include "main/glheader.h" 34#include "main/macros.h" 35#include "main/enums.h" 36#include "program/program.h" 37 38#include "intel_batchbuffer.h" 39 40#include "brw_defines.h" 41#include "brw_context.h" 42#include "brw_eu.h" 43#include "brw_clip.h" 44 45 46 47 48struct brw_reg get_tmp( struct brw_clip_compile *c ) 49{ 50 struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0); 51 52 if (++c->last_tmp > c->prog_data.total_grf) 53 c->prog_data.total_grf = c->last_tmp; 54 55 return tmp; 56} 57 58static void release_tmp( struct brw_clip_compile *c, struct brw_reg tmp ) 59{ 60 if (tmp.nr == c->last_tmp-1) 61 c->last_tmp--; 62} 63 64 65static struct brw_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w) 66{ 67 return brw_imm_ud((w<<24) | (z<<16) | (y<<8) | x); 68} 69 70 71void brw_clip_init_planes( struct brw_clip_compile *c ) 72{ 73 struct brw_compile *p = &c->func; 74 75 if (!c->key.nr_userclip) { 76 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1)); 77 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1)); 78 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1)); 79 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1)); 80 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1)); 81 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1)); 82 } 83} 84 85 86 87#define W 3 88 89/* Project 'pos' to screen space (or back again), overwrite with results: 90 */ 91void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos ) 92{ 93 struct brw_compile *p = &c->func; 94 95 /* calc rhw 96 */ 97 brw_math_invert(p, get_element(pos, W), get_element(pos, W)); 98 99 /* value.xyz *= value.rhw 100 */ 101 brw_set_access_mode(p, BRW_ALIGN_16); 102 brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos, brw_swizzle1(pos, W)); 103 brw_set_access_mode(p, BRW_ALIGN_1); 104} 105 106 107static void brw_clip_project_vertex( struct brw_clip_compile *c, 108 struct brw_indirect vert_addr ) 109{ 110 struct brw_compile *p = &c->func; 111 struct brw_reg tmp = get_tmp(c); 112 GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map, 113 VERT_RESULT_HPOS); 114 GLuint ndc_offset = brw_vert_result_to_offset(&c->vue_map, 115 BRW_VERT_RESULT_NDC); 116 117 /* Fixup position. Extract from the original vertex and re-project 118 * to screen space: 119 */ 120 brw_MOV(p, tmp, deref_4f(vert_addr, hpos_offset)); 121 brw_clip_project_position(c, tmp); 122 brw_MOV(p, deref_4f(vert_addr, ndc_offset), tmp); 123 124 release_tmp(c, tmp); 125} 126 127 128 129 130/* Interpolate between two vertices and put the result into a0.0. 131 * Increment a0.0 accordingly. 132 */ 133void brw_clip_interp_vertex( struct brw_clip_compile *c, 134 struct brw_indirect dest_ptr, 135 struct brw_indirect v0_ptr, /* from */ 136 struct brw_indirect v1_ptr, /* to */ 137 struct brw_reg t0, 138 bool force_edgeflag) 139{ 140 struct brw_compile *p = &c->func; 141 struct brw_reg tmp = get_tmp(c); 142 GLuint slot; 143 144 /* Just copy the vertex header: 145 */ 146 /* 147 * After CLIP stage, only first 256 bits of the VUE are read 148 * back on Ironlake, so needn't change it 149 */ 150 brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1); 151 152 /* Iterate over each attribute (could be done in pairs?) 153 */ 154 for (slot = 0; slot < c->vue_map.num_slots; slot++) { 155 int vert_result = c->vue_map.slot_to_vert_result[slot]; 156 GLuint delta = brw_vue_slot_to_offset(slot); 157 158 if (vert_result == VERT_RESULT_EDGE) { 159 if (force_edgeflag) 160 brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1)); 161 else 162 brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta)); 163 } else if (vert_result == VERT_RESULT_PSIZ || 164 vert_result == VERT_RESULT_CLIP_DIST0 || 165 vert_result == VERT_RESULT_CLIP_DIST1) { 166 /* PSIZ doesn't need interpolation because it isn't used by the 167 * fragment shader. CLIP_DIST0 and CLIP_DIST1 don't need 168 * intepolation because on pre-GEN6, these are just placeholder VUE 169 * slots that don't perform any action. 170 */ 171 } else if (vert_result < VERT_RESULT_MAX) { 172 /* This is a true vertex result (and not a special value for the VUE 173 * header), so interpolate: 174 * 175 * New = attr0 + t*attr1 - t*attr0 176 */ 177 brw_MUL(p, 178 vec4(brw_null_reg()), 179 deref_4f(v1_ptr, delta), 180 t0); 181 182 brw_MAC(p, 183 tmp, 184 negate(deref_4f(v0_ptr, delta)), 185 t0); 186 187 brw_ADD(p, 188 deref_4f(dest_ptr, delta), 189 deref_4f(v0_ptr, delta), 190 tmp); 191 } 192 } 193 194 if (c->vue_map.num_slots % 2) { 195 GLuint delta = brw_vue_slot_to_offset(c->vue_map.num_slots); 196 197 brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0)); 198 } 199 200 release_tmp(c, tmp); 201 202 /* Recreate the projected (NDC) coordinate in the new vertex 203 * header: 204 */ 205 brw_clip_project_vertex(c, dest_ptr ); 206} 207 208void brw_clip_emit_vue(struct brw_clip_compile *c, 209 struct brw_indirect vert, 210 bool allocate, 211 bool eot, 212 GLuint header) 213{ 214 struct brw_compile *p = &c->func; 215 216 brw_clip_ff_sync(c); 217 218 assert(!(allocate && eot)); 219 220 /* Copy the vertex from vertn into m1..mN+1: 221 */ 222 brw_copy_from_indirect(p, brw_message_reg(1), vert, c->nr_regs); 223 224 /* Overwrite PrimType and PrimStart in the message header, for 225 * each vertex in turn: 226 */ 227 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header)); 228 229 230 /* Send each vertex as a seperate write to the urb. This 231 * is different to the concept in brw_sf_emit.c, where 232 * subsequent writes are used to build up a single urb 233 * entry. Each of these writes instantiates a seperate 234 * urb entry - (I think... what about 'allocate'?) 235 */ 236 brw_urb_WRITE(p, 237 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), 238 0, 239 c->reg.R0, 240 allocate, 241 1, /* used */ 242 c->nr_regs + 1, /* msg length */ 243 allocate ? 1 : 0, /* response_length */ 244 eot, /* eot */ 245 1, /* writes_complete */ 246 0, /* urb offset */ 247 BRW_URB_SWIZZLE_NONE); 248} 249 250 251 252void brw_clip_kill_thread(struct brw_clip_compile *c) 253{ 254 struct brw_compile *p = &c->func; 255 256 brw_clip_ff_sync(c); 257 /* Send an empty message to kill the thread and release any 258 * allocated urb entry: 259 */ 260 brw_urb_WRITE(p, 261 retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), 262 0, 263 c->reg.R0, 264 0, /* allocate */ 265 0, /* used */ 266 1, /* msg len */ 267 0, /* response len */ 268 1, /* eot */ 269 1, /* writes complete */ 270 0, 271 BRW_URB_SWIZZLE_NONE); 272} 273 274 275 276 277struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c ) 278{ 279 return brw_address(c->reg.fixed_planes); 280} 281 282 283struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c ) 284{ 285 if (c->key.nr_userclip) { 286 return brw_imm_uw(16); 287 } 288 else { 289 return brw_imm_uw(4); 290 } 291} 292 293 294/* If flatshading, distribute color from provoking vertex prior to 295 * clipping. 296 */ 297void brw_clip_copy_colors( struct brw_clip_compile *c, 298 GLuint to, GLuint from ) 299{ 300 struct brw_compile *p = &c->func; 301 302 if (brw_clip_have_vert_result(c, VERT_RESULT_COL0)) 303 brw_MOV(p, 304 byte_offset(c->reg.vertex[to], 305 brw_vert_result_to_offset(&c->vue_map, 306 VERT_RESULT_COL0)), 307 byte_offset(c->reg.vertex[from], 308 brw_vert_result_to_offset(&c->vue_map, 309 VERT_RESULT_COL0))); 310 311 if (brw_clip_have_vert_result(c, VERT_RESULT_COL1)) 312 brw_MOV(p, 313 byte_offset(c->reg.vertex[to], 314 brw_vert_result_to_offset(&c->vue_map, 315 VERT_RESULT_COL1)), 316 byte_offset(c->reg.vertex[from], 317 brw_vert_result_to_offset(&c->vue_map, 318 VERT_RESULT_COL1))); 319 320 if (brw_clip_have_vert_result(c, VERT_RESULT_BFC0)) 321 brw_MOV(p, 322 byte_offset(c->reg.vertex[to], 323 brw_vert_result_to_offset(&c->vue_map, 324 VERT_RESULT_BFC0)), 325 byte_offset(c->reg.vertex[from], 326 brw_vert_result_to_offset(&c->vue_map, 327 VERT_RESULT_BFC0))); 328 329 if (brw_clip_have_vert_result(c, VERT_RESULT_BFC1)) 330 brw_MOV(p, 331 byte_offset(c->reg.vertex[to], 332 brw_vert_result_to_offset(&c->vue_map, 333 VERT_RESULT_BFC1)), 334 byte_offset(c->reg.vertex[from], 335 brw_vert_result_to_offset(&c->vue_map, 336 VERT_RESULT_BFC1))); 337} 338 339 340 341void brw_clip_init_clipmask( struct brw_clip_compile *c ) 342{ 343 struct brw_compile *p = &c->func; 344 struct brw_reg incoming = get_element_ud(c->reg.R0, 2); 345 346 /* Shift so that lowest outcode bit is rightmost: 347 */ 348 brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26)); 349 350 if (c->key.nr_userclip) { 351 struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD); 352 353 /* Rearrange userclip outcodes so that they come directly after 354 * the fixed plane bits. 355 */ 356 brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14)); 357 brw_SHR(p, tmp, tmp, brw_imm_ud(8)); 358 brw_OR(p, c->reg.planemask, c->reg.planemask, tmp); 359 360 release_tmp(c, tmp); 361 } 362} 363 364void brw_clip_ff_sync(struct brw_clip_compile *c) 365{ 366 struct intel_context *intel = &c->func.brw->intel; 367 368 if (intel->needs_ff_sync) { 369 struct brw_compile *p = &c->func; 370 371 brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); 372 brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1)); 373 brw_IF(p, BRW_EXECUTE_1); 374 { 375 brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1)); 376 brw_ff_sync(p, 377 c->reg.R0, 378 0, 379 c->reg.R0, 380 1, /* allocate */ 381 1, /* response length */ 382 0 /* eot */); 383 } 384 brw_ENDIF(p); 385 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 386 } 387} 388 389void brw_clip_init_ff_sync(struct brw_clip_compile *c) 390{ 391 struct intel_context *intel = &c->func.brw->intel; 392 393 if (intel->needs_ff_sync) { 394 struct brw_compile *p = &c->func; 395 396 brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0)); 397 } 398} 399