brw_wm_state.c revision d375df220fae47f38944c4832bcbd5f5d568884c
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33 34#include "intel_fbo.h" 35#include "brw_context.h" 36#include "brw_state.h" 37#include "brw_defines.h" 38#include "brw_wm.h" 39 40/*********************************************************************** 41 * WM unit - fragment programs and rasterization 42 */ 43 44bool 45brw_color_buffer_write_enabled(struct brw_context *brw) 46{ 47 struct gl_context *ctx = &brw->intel.ctx; 48 const struct gl_fragment_program *fp = brw->fragment_program; 49 int i; 50 51 /* _NEW_BUFFERS */ 52 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { 53 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; 54 55 /* _NEW_COLOR */ 56 if (rb && 57 (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) || 58 fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) && 59 (ctx->Color.ColorMask[i][0] || 60 ctx->Color.ColorMask[i][1] || 61 ctx->Color.ColorMask[i][2] || 62 ctx->Color.ColorMask[i][3])) { 63 return true; 64 } 65 } 66 67 return false; 68} 69 70/** 71 * Setup wm hardware state. See page 225 of Volume 2 72 */ 73static void 74brw_prepare_wm_unit(struct brw_context *brw) 75{ 76 struct intel_context *intel = &brw->intel; 77 struct gl_context *ctx = &intel->ctx; 78 const struct gl_fragment_program *fp = brw->fragment_program; 79 struct brw_wm_unit_state *wm; 80 81 wm = brw_state_batch(brw, AUB_TRACE_WM_STATE, 82 sizeof(*wm), 32, &brw->wm.state_offset); 83 memset(wm, 0, sizeof(*wm)); 84 85 if (brw->wm.prog_data->prog_offset_16) { 86 /* These two fields should be the same pre-gen6, which is why we 87 * only have one hardware field to program for both dispatch 88 * widths. 89 */ 90 assert(brw->wm.prog_data->first_curbe_grf == 91 brw->wm.prog_data->first_curbe_grf_16); 92 } 93 94 /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */ 95 wm->thread0.grf_reg_count = brw->wm.prog_data->reg_blocks; 96 wm->wm9.grf_reg_count_2 = brw->wm.prog_data->reg_blocks_16; 97 98 wm->thread0.kernel_start_pointer = 99 brw_program_reloc(brw, 100 brw->wm.state_offset + 101 offsetof(struct brw_wm_unit_state, thread0), 102 brw->wm.prog_offset + 103 (wm->thread0.grf_reg_count << 1)) >> 6; 104 105 wm->wm9.kernel_start_pointer_2 = 106 brw_program_reloc(brw, 107 brw->wm.state_offset + 108 offsetof(struct brw_wm_unit_state, wm9), 109 brw->wm.prog_offset + 110 brw->wm.prog_data->prog_offset_16 + 111 (wm->wm9.grf_reg_count_2 << 1)) >> 6; 112 113 wm->thread1.depth_coef_urb_read_offset = 1; 114 wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; 115 116 if (intel->gen == 5) 117 wm->thread1.binding_table_entry_count = 0; /* hardware requirement */ 118 else { 119 /* BRW_NEW_NR_SURFACES */ 120 wm->thread1.binding_table_entry_count = brw->wm.nr_surfaces; 121 } 122 123 if (brw->wm.prog_data->total_scratch != 0) { 124 wm->thread2.scratch_space_base_pointer = 125 brw->wm.scratch_bo->offset >> 10; /* reloc */ 126 wm->thread2.per_thread_scratch_space = 127 ffs(brw->wm.prog_data->total_scratch) - 11; 128 } else { 129 wm->thread2.scratch_space_base_pointer = 0; 130 wm->thread2.per_thread_scratch_space = 0; 131 } 132 133 wm->thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf; 134 wm->thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length; 135 wm->thread3.urb_entry_read_offset = 0; 136 wm->thread3.const_urb_entry_read_length = 137 brw->wm.prog_data->curb_read_length; 138 /* BRW_NEW_CURBE_OFFSETS */ 139 wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2; 140 141 if (intel->gen == 5) 142 wm->wm4.sampler_count = 0; /* hardware requirement */ 143 else { 144 /* CACHE_NEW_SAMPLER */ 145 wm->wm4.sampler_count = (brw->wm.sampler_count + 1) / 4; 146 } 147 148 if (brw->wm.sampler_count) { 149 /* reloc */ 150 wm->wm4.sampler_state_pointer = (intel->batch.bo->offset + 151 brw->wm.sampler_offset) >> 5; 152 } else { 153 wm->wm4.sampler_state_pointer = 0; 154 } 155 156 /* BRW_NEW_FRAGMENT_PROGRAM */ 157 wm->wm5.program_uses_depth = (fp->Base.InputsRead & 158 (1 << FRAG_ATTRIB_WPOS)) != 0; 159 wm->wm5.program_computes_depth = (fp->Base.OutputsWritten & 160 BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0; 161 /* _NEW_BUFFERS 162 * Override for NULL depthbuffer case, required by the Pixel Shader Computed 163 * Depth field. 164 */ 165 if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH)) 166 wm->wm5.program_computes_depth = 0; 167 168 /* _NEW_COLOR */ 169 wm->wm5.program_uses_killpixel = fp->UsesKill || ctx->Color.AlphaEnabled; 170 171 172 /* BRW_NEW_FRAGMENT_PROGRAM 173 * 174 * If using the fragment shader backend, the program is always 175 * 8-wide. If not, it's always 16. 176 */ 177 if (ctx->Shader.CurrentFragmentProgram) { 178 struct brw_shader *shader = (struct brw_shader *) 179 ctx->Shader.CurrentFragmentProgram->_LinkedShaders[MESA_SHADER_FRAGMENT]; 180 181 if (shader != NULL && shader->ir != NULL) { 182 wm->wm5.enable_8_pix = 1; 183 if (brw->wm.prog_data->prog_offset_16) 184 wm->wm5.enable_16_pix = 1; 185 } 186 } 187 if (!wm->wm5.enable_8_pix) 188 wm->wm5.enable_16_pix = 1; 189 190 wm->wm5.max_threads = brw->wm_max_threads - 1; 191 192 /* _NEW_BUFFERS | _NEW_COLOR */ 193 if (brw_color_buffer_write_enabled(brw) || 194 wm->wm5.program_uses_killpixel || 195 wm->wm5.program_computes_depth) { 196 wm->wm5.thread_dispatch_enable = 1; 197 } 198 199 wm->wm5.legacy_line_rast = 0; 200 wm->wm5.legacy_global_depth_bias = 0; 201 wm->wm5.early_depth_test = 1; /* never need to disable */ 202 wm->wm5.line_aa_region_width = 0; 203 wm->wm5.line_endcap_aa_region_width = 1; 204 205 /* _NEW_POLYGONSTIPPLE */ 206 wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag; 207 208 /* _NEW_POLYGON */ 209 if (ctx->Polygon.OffsetFill) { 210 wm->wm5.depth_offset = 1; 211 /* Something wierd going on with legacy_global_depth_bias, 212 * offset_constant, scaling and MRD. This value passes glean 213 * but gives some odd results elsewere (eg. the 214 * quad-offset-units test). 215 */ 216 wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2; 217 218 /* This is the only value that passes glean: 219 */ 220 wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor; 221 } 222 223 /* _NEW_LINE */ 224 wm->wm5.line_stipple = ctx->Line.StippleFlag; 225 226 /* _NEW_DEPTH */ 227 if (unlikely(INTEL_DEBUG & DEBUG_STATS) || intel->stats_wm) 228 wm->wm4.stats_enable = 1; 229 230 /* Emit scratch space relocation */ 231 if (brw->wm.prog_data->total_scratch != 0) { 232 drm_intel_bo_emit_reloc(intel->batch.bo, 233 brw->wm.state_offset + 234 offsetof(struct brw_wm_unit_state, thread2), 235 brw->wm.scratch_bo, 236 wm->thread2.per_thread_scratch_space, 237 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); 238 } 239 240 /* Emit sampler state relocation */ 241 if (brw->wm.sampler_count != 0) { 242 drm_intel_bo_emit_reloc(intel->batch.bo, 243 brw->wm.state_offset + 244 offsetof(struct brw_wm_unit_state, wm4), 245 intel->batch.bo, (brw->wm.sampler_offset | 246 wm->wm4.stats_enable | 247 (wm->wm4.sampler_count << 2)), 248 I915_GEM_DOMAIN_INSTRUCTION, 0); 249 } 250 251 brw->state.dirty.cache |= CACHE_NEW_WM_UNIT; 252} 253 254const struct brw_tracked_state brw_wm_unit = { 255 .dirty = { 256 .mesa = (_NEW_POLYGON | 257 _NEW_POLYGONSTIPPLE | 258 _NEW_LINE | 259 _NEW_COLOR | 260 _NEW_DEPTH | 261 _NEW_BUFFERS), 262 263 .brw = (BRW_NEW_BATCH | 264 BRW_NEW_PROGRAM_CACHE | 265 BRW_NEW_FRAGMENT_PROGRAM | 266 BRW_NEW_CURBE_OFFSETS | 267 BRW_NEW_NR_WM_SURFACES), 268 269 .cache = (CACHE_NEW_WM_PROG | 270 CACHE_NEW_SAMPLER) 271 }, 272 .prepare = brw_prepare_wm_unit, 273}; 274 275