| b527dd65c830a2b008816cf390d5be906e29bb23 |
|
15-Nov-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Track fixed-function fragment shader as a shader
Previously the fixed-function fragment shader was tracked as a
gl_program. This means that it shows up in the driver as a Mesa IR
program instead of as a GLSL IR program. If a driver doesn't generate
Mesa IR from the GLSL IR, that program is empty. If the program is
empty there is either no rendering or a GPU hang.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 32dfa6e5ef3d1fb703ec34942c55408be22e7ec3 |
|
28-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move and rename "wm sampler" fields to just "sampler".
brw_wm_samplers actually enables any active samplers regardless of what
pipeline stage is using them, so it doesn't make much sense for it to be
WM-specific. So, rename it to "brw_samplers."
To properly generalize it, move sampler_count and sampler_offset from
brw_context::wm to a new brw_context::sampler that can be shared without
looking strange.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 6ba9090ea05e817bd38c1fcc63c53168b16593c7 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).
These fields control how many entries the hardware prefetches into the
state cache, so they only impact performance, not correctness. However,
it's not clear how to use this in a way that's beneficial.
According to the documentation, kernels "using a large number" of
entries may wish to program this to zero to avoid thrashing the cache;
it's unclear how many is too many. Also, Ironlake's WM was missing this
feature entirely---the count had to be zero.
The dirty bit tracking to handle this complicates the surface state
and binding table setup; removing it should simplify things and make
future refactoring easier. So just set 0 for the number of entries
rather than trying to compute and track it.
Appears to have no impact on Nexuiz and OpenArena on Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| c4aaf85285fc9484e95e9cda89db9cc6923259f4 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move unit state setup to emit() time.
It is only needed in time for brw_psp_urb_cbs(), which is also an emit().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| db6dd6d88fdc4361193dd063e4f150f01a104faa |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename (vs|wm)_max_threads to max_(vs|wm)_threads for consistency.
The inconsistency between vs_max_threads and max_vs_entries was rather
annoying. I could never seem to remember which one was reversed, which
made it harder to find quickly. "Max __ Threads" seems more natural.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| d375df220fae47f38944c4832bcbd5f5d568884c |
|
23-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a type argument to brw_state_batch().
I want to make brw_state_dump.c handle more than just the last
statechange, so I want to keep track of what's in the batch state. By
using AUB file numbering for most of these packets, this may be
reusable for aub dumping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 1791857d7d950d3d2834bbb09b495f51f43ef7c1 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Move the computation of register block count from unit to compile.
No net code size change, but unit update is down 0.8% code size
pre-gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| a98dd64af750fb6dae54b2dc02e0c5a3711156af |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Stop caching the combined depth/stencil region in brw_context.c.
This was going to get in the way of separate depth/stencil (which
wants to know about both, and whether they are the same rb), and also
wasn't a sufficient flag for the fix in the following commit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 5c742ea1ee0cea031cb99651155d0c7521f42b4e |
|
23-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move sampler state to state streaming.
Overall, across this series since the last set of numbers, gen6 3DMMES
taiji performance has dropped 0.8% +/- 0.3% (n=15), probably due to
the increased reissuing of state from some of the state objects that
otherwise never changed, and increased occurrence of the per-batch
overhead as we've increased how much we put in the batch BO without
increasing the batch BO's size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 1a447749ed421db8eb6ba20012630785aef9bb12 |
|
23-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move WM state to state streaming.
The samplers are about to become streamed for gen6 performance, which
would cause this unit to blow out the state cache.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 42ad2f0b9b6a18f1613f6d915a46b4a4a89c5aa2 |
|
14-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for 16-wide dispatch on gen5.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 59c6b775a6aacfe03c84dae62c2fd45d4af9d70b |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add gen6 register spilling support.
Most of this is code movement to get the scratch space allocated in a
shared location. Other than that, the only real changes are that the
old oword block messages now operate on oword-aligned areas (with new
messages for unaligned access, which we don't do), and that the
caching control is in the SFID part of the descriptor instead of
message control.
Fixes glsl-fs-convolution-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 403be1111190a3fe63ae03bc0111e0a0b026495b |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
Revert "i965: Use the fixed function GLSL program instead of the ARB program."
This reverts commit 81b34a4e3a7aec9cdf2781757408dc5e9eec79cb. There
were regressions in the core change that this depends on.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 81b34a4e3a7aec9cdf2781757408dc5e9eec79cb |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use the fixed function GLSL program instead of the ARB program.
This gets one more piece of the pipeline onto the new codegen backend.
Once ARB_fragment_program can generate GLSL programs, we can nuke the
old backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| df8ca3e0ec7bb804d9a225ed8e888b7199b70567 |
|
05-Feb-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove pointless keying of WM state on VUE size.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 834cc8e501c2632fd8f9fc78502a1a99803e6fb9 |
|
09-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: remove unused variable since brw_wm_glsl.c removal.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 5ba517baa22b05d594b8839ac06fe45b81c1d09f |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Nuke brw_wm_glsl.c.
It was only used for gen6 fragment programs (not GLSL shaders) at this
point, and it was clearly unsuited to the task -- missing opcodes,
corrupted texturing, and assertion failures hit various applications
of all sorts. It was easier to patch up the non-glsl for remaining
gen6 changes than to make brw_wm_glsl.c complete.
Bug #30530
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 84eba3ef71dfa822e5ff0463032cdd2e3515b888 |
|
13-Oct-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
Track separate programs for each stage
The assumption is that all stages are the same program or that
varyings are passed between stages using built-in varyings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 4e7252510976d8d3ff12437ea8842129f24d88f5 |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Correct scratch space allocation.
One, it was allocating increments of 1kb, but per thread scratch space
is a power of two. Two, the new FS wasn't getting total_scratch set
at all, so everyone thought they had 1kb and writes beyond 1kb would
go stomping on a neighbor thread.
With this plus the previous register spilling for the new FS,
glsl-fs-convolution-1 passes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| f30de6964018619658439216cd8bf9371ee6256d |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Disable thread dispatch when the FS doesn't do any work.
This should reduce the cost of generating shadow maps, for example.
No performance difference measured in nexuiz, though it does trigger
this path.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 3322fbaf3b5e305ce00c1d08c26965bb98e0cef0 |
|
14-Oct-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl: Slightly change the semantic of _LinkedShaders
Previously _LinkedShaders was a compact array of the linked shaders
for each shader stage. Now it is arranged such that each slot,
indexed by the MESA_SHADER_* defines, refers to a specific shader
stage. As a result, some slots will be NULL. This makes things a
little more complex in the linker, but it simplifies things in other
places.
As a side effect _NumLinkedShaders is removed.
NOTE: This may be a candidate for the 7.9 branch. If there are other
patches that get backported to 7.9 that use _LinkedShader, this patch
should be cherry picked also.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 9763d0a82a1ee605a8794f199d432824fb972b6a |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start building direct GLSL2 IR to 965 assembly codegen.
Our channel-expressions and vector-splitting changes now happen into a
private copy of the IR that we maintain for ourselves. Uniform
assignment still happens by the core, so we continue using Mesa IR
generation not just for swrast fallbacks but also for uniform values
(since there's no storage for their contents other than
shader_program->FragmentProgram->Parameters->ParameterValues). And
most importantly, at the moment no actual codegen is hooked up other
than emitting our favorite color to the framebuffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| ff81a1dd92f1bffcbfbd2c5268ea0d821b8e9dd4 |
|
21-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the GEM domain flags for the scratch space.
They go into the render cache, so while we don't care about their
contents after execution, failing to note them could cause the writes
to be flushed over important buffer contents later.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| df3c1a563f3d76b07ab82c7b230b0030452f36ff |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.
The new API makes so much more sense, I'd like to forget how the old
one worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 0b87f143c466f7e5bd730895ee29f1cd20a68f9b |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_G4X() across the driver with context structure usage.
Saves ~2KB of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 5606dfb572bf4b89b4882265924705bacc8c182b |
|
18-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'outputswritten64'
Add a GLbitfield64 type and several macros to operate on 64-bit
fields. The OutputsWritten field of gl_program is changed to use that
type. This results in a fair amount of fallout in drivers that use
programs.
No changes are strictly necessary at this point as all bits used are
below the 32-bit boundary. Fairly soon several bits will be added for
clip distances written by a vertex shader. This will cause several
bits used for varyings to be pushed above the 32-bit boundary. This
will affect any drivers that support GLSL.
At this point, only the i965 driver has been modified to support this
eventuality.
I did this as a "squash" merge. There were several places through the
outputswritten64 branch where things were broken. I foresee this
causing difficulties later for bisecting. The history is still
available in the branch.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 3e4539a471da48066a83eda8e14301dbc4dbf6db |
|
07-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Respect spec requirement for pixel shader computed depth with no zbuffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| cafea7528052624c8d3e4cd1c5b26a61bf04d1d0 |
|
14-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: VS constant buffers
Hook up a constant buffer, binding table, etc for the VS unit.
This will allow using large constant buffers with vertex shaders.
The new code is disabled at this time (use_const_buffer=FALSE).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 1ee0e226469514335b80ff42e4cbef0f355bd8c4 |
|
31-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor code movement, new comment
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| c82851598f535f5c92885987cafbb5e79a2505db |
|
23-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: rename scratch_buffer -> scratch_bo to be consistant with other buffers
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| c0d6e07909733af054cc592e2cfc6212155b0a9e |
|
23-Mar-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix occlusion query when no other WM state updates occur.
Turns out that XXX comment was important. We weren't flagging the WM to
re-update with the statistics enable, so we got zeroes out of our query.
Bug #20740, fixes piglit occlusion_query test.
Signed-off-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 5cbd1170da0a902fdc9c460584bc503b0c4085a6 |
|
07-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: avoid unnecessary calls to brw_wm_is_glsl()
This function scans the shader to see if it has any GLSL features like
conditionals and loops. Calling this during state validation is expensive.
Just call it when the shader is given to the driver and save the result.
There's some new/temporary assertions to be sure we don't get out of sync
on this.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 8d475822e6e19fa79719c856a2db5b6a205db1b9 |
|
28-Feb-2009 |
Brian Paul <brianp@vmware.com> |
mesa: rename, reorder FRAG_RESULT_x tokens
s/FRAG_RESULT_DEPR/FRAG_RESULT_DEPTH/
s/FRAG_RESULT_COLR/FRAG_RESULT/COLOR/
Remove FRAG_RESULT_COLH (NV half-precision) output since we never used it.
Next, we might merge the COLOR and DATA outputs (COLOR0, COLOR1, etc).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| e476acb1051ae1a7e5e2be35a89488a8e5b07ff4 |
|
28-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Add a new state flag BRW_NEW_NR_SURFACES instead of CACHE_NEW_SURFACE
The CACHE_NEW_SURFACE bit always gets spammed since we get many different
surface BOs per state emit, but the only consumer of it wanted to just know
how many surfaces were enabled.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 287d719a93728dfd736ecd6ef31c8101f12d58c2 |
|
28-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Remove BRW_WM_LOCK dirty bit, introduced to work around lack of relocs.
This was causing a prepare of wm state at every primitive emit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 5cb7ba10cc6aebfb96c6425d3d822d2b0ac5e102 |
|
03-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Update WM maximum threads for G4X.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
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08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
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11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
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03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| ab50ddaa9173ae108833db0edb209045788efc41 |
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07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
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17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| d0774eae304a9e109f2bdbb361fe0c1ef0cf6691 |
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20-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Fix WM unit cache keying that broke line stipple and polygon offset.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 8abffada70fcd62e3c2dcbcdc6d00d258805326b |
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03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert relocations to not be cleared out on buffer submit.
We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 0ff3eb637bac9e100aab0a109a46e81bea9203a3 |
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03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Fix some missing initialization in WM keys.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 9e9f6f105c81436cecfe55a8a80d2efe45bc0d72 |
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03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert WM unit to use a cache key instead of brw_cache_data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
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14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 7c71ef3a3d0cf2620525f468960cdc76a0fb0d33 |
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12-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
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08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 6ef27b88e6f767cd476676b33cb7c4ea6922234e |
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26-Oct-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Merge branch '965-glsl'
Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
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| 77e0523fb7769df4bf43747e136b1653b2421b97 |
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04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| e886ae4c58bc98897d6901e3f30deea008bc7f8a |
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28-Sep-2007 |
Eric Anholt <eric@anholt.net> |
Revert "WIP 965 conversion to dri_bufmgr."
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e.
Somehow I ended up with my branch's save-this-while-I-work-on-master commit
actually on master.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| b2f1aa2389473ed09170713301b042661d70a48e |
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27-Sep-2007 |
Eric Anholt <eric@anholt.net> |
WIP 965 conversion to dri_bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 410d8f7cdb40889e66f5c6794878ad9a5f572ee7 |
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29-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: samplers group in fours in WM_STATE. fix bug#9415
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
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21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 62db3cc34982d2fec9165633813ef6e656f7d497 |
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07-Jan-2007 |
Keith Packard <keithp@neko.keithp.com> |
Various warning fixes for i965 driver.
vertex/fragment programs provided as const.
bmSetFenceLock should return bmSetFence value.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 4068e2d1b766a9ccedcb8d7cd07c49d22dff39f0 |
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11-Dec-2006 |
Wang Zhenyu <zhenyu.z.wang@intel.com> |
i965: ARB_occlusion_query support
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 1456a0fff6a68dac046aaa57585eadf65ad66892 |
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07-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Use lower alignments where possible. Also pad out allocated blocks to
a multiple of alignment to avoid accumulating unusable free blocks.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 133f14168009393c5f396d218521625cb79b653f |
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07-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Make sure bmBufferOffset is called for all active buffers every time
we render. Currenly requires that some state be re-examined after
every LOCK_HARDWARE().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
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09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_state.c
|