1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * Keith Whitwell <keith@tungstengraphics.com> 31 */ 32 33#ifndef __RADEON_DRM_H__ 34#define __RADEON_DRM_H__ 35 36/* WARNING: If you change any of these defines, make sure to change the 37 * defines in the X server file (radeon_sarea.h) 38 */ 39#ifndef __RADEON_SAREA_DEFINES__ 40#define __RADEON_SAREA_DEFINES__ 41 42/* Old style state flags, required for sarea interface (1.1 and 1.2 43 * clears) and 1.2 drm_vertex2 ioctl. 44 */ 45#define RADEON_UPLOAD_CONTEXT 0x00000001 46#define RADEON_UPLOAD_VERTFMT 0x00000002 47#define RADEON_UPLOAD_LINE 0x00000004 48#define RADEON_UPLOAD_BUMPMAP 0x00000008 49#define RADEON_UPLOAD_MASKS 0x00000010 50#define RADEON_UPLOAD_VIEWPORT 0x00000020 51#define RADEON_UPLOAD_SETUP 0x00000040 52#define RADEON_UPLOAD_TCL 0x00000080 53#define RADEON_UPLOAD_MISC 0x00000100 54#define RADEON_UPLOAD_TEX0 0x00000200 55#define RADEON_UPLOAD_TEX1 0x00000400 56#define RADEON_UPLOAD_TEX2 0x00000800 57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 61#define RADEON_REQUIRE_QUIESCENCE 0x00010000 62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 63#define RADEON_UPLOAD_ALL 0x003effff 64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 65 66/* New style per-packet identifiers for use in cmd_buffer ioctl with 67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old 68 * state bits and the packet size: 69 */ 70#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 71#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 72#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 73#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 74#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 75#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 76#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 77#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 78#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 79#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 80#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 81#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 82#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 83#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 84#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 85#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 86#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 87#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 88#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 89#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 90#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 91#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 92#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 93#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 94#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 95#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 96#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 97#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 98#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 99#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 100#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 101#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 102#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 103#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 104#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 105#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 106#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 107#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 108#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 109#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 110#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 111#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 112#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 113#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 114#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 115#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 116#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 117#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 118#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 119#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 120#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 121#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 122#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 123#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 124#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 125#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 126#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 127#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 128#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 129#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 130#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 131#define R200_EMIT_PP_CUBIC_FACES_0 61 132#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 133#define R200_EMIT_PP_CUBIC_FACES_1 63 134#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 135#define R200_EMIT_PP_CUBIC_FACES_2 65 136#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 137#define R200_EMIT_PP_CUBIC_FACES_3 67 138#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 139#define R200_EMIT_PP_CUBIC_FACES_4 69 140#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 141#define R200_EMIT_PP_CUBIC_FACES_5 71 142#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 143#define RADEON_EMIT_PP_TEX_SIZE_0 73 144#define RADEON_EMIT_PP_TEX_SIZE_1 74 145#define RADEON_EMIT_PP_TEX_SIZE_2 75 146#define R200_EMIT_RB3D_BLENDCOLOR 76 147#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 148#define RADEON_EMIT_PP_CUBIC_FACES_0 78 149#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 150#define RADEON_EMIT_PP_CUBIC_FACES_1 80 151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 152#define RADEON_EMIT_PP_CUBIC_FACES_2 82 153#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 154#define R200_EMIT_PP_TRI_PERF_CNTL 84 155#define R200_EMIT_PP_AFS_0 85 156#define R200_EMIT_PP_AFS_1 86 157#define R200_EMIT_ATF_TFACTOR 87 158#define R200_EMIT_PP_TXCTLALL_0 88 159#define R200_EMIT_PP_TXCTLALL_1 89 160#define R200_EMIT_PP_TXCTLALL_2 90 161#define R200_EMIT_PP_TXCTLALL_3 91 162#define R200_EMIT_PP_TXCTLALL_4 92 163#define R200_EMIT_PP_TXCTLALL_5 93 164#define R200_EMIT_VAP_PVS_CNTL 94 165#define RADEON_MAX_STATE_PACKETS 95 166 167/* Commands understood by cmd_buffer ioctl. More can be added but 168 * obviously these can't be removed or changed: 169 */ 170#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 171#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 172#define RADEON_CMD_VECTORS 3 /* emit vector data */ 173#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 174#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 175#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 176#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 177#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 178 * doesn't make the cpu wait, just 179 * the graphics hardware */ 180#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 181 182typedef union { 183 int i; 184 struct { 185 unsigned char cmd_type, pad0, pad1, pad2; 186 } header; 187 struct { 188 unsigned char cmd_type, packet_id, pad0, pad1; 189 } packet; 190 struct { 191 unsigned char cmd_type, offset, stride, count; 192 } scalars; 193 struct { 194 unsigned char cmd_type, offset, stride, count; 195 } vectors; 196 struct { 197 unsigned char cmd_type, addr_lo, addr_hi, count; 198 } veclinear; 199 struct { 200 unsigned char cmd_type, buf_idx, pad0, pad1; 201 } dma; 202 struct { 203 unsigned char cmd_type, flags, pad0, pad1; 204 } wait; 205} drm_radeon_cmd_header_t; 206 207#define RADEON_WAIT_2D 0x1 208#define RADEON_WAIT_3D 0x2 209 210/* Allowed parameters for R300_CMD_PACKET3 211 */ 212#define R300_CMD_PACKET3_CLEAR 0 213#define R300_CMD_PACKET3_RAW 1 214 215/* Commands understood by cmd_buffer ioctl for R300. 216 * The interface has not been stabilized, so some of these may be removed 217 * and eventually reordered before stabilization. 218 */ 219#define R300_CMD_PACKET0 1 220#define R300_CMD_VPU 2 /* emit vertex program upload */ 221#define R300_CMD_PACKET3 3 /* emit a packet3 */ 222#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 223#define R300_CMD_CP_DELAY 5 224#define R300_CMD_DMA_DISCARD 6 225#define R300_CMD_WAIT 7 226# define R300_WAIT_2D 0x1 227# define R300_WAIT_3D 0x2 228/* these two defines are DOING IT WRONG - however 229 * we have userspace which relies on using these. 230 * The wait interface is backwards compat new 231 * code should use the NEW_WAIT defines below 232 * THESE ARE NOT BIT FIELDS 233 */ 234# define R300_WAIT_2D_CLEAN 0x3 235# define R300_WAIT_3D_CLEAN 0x4 236 237# define R300_NEW_WAIT_2D_3D 0x3 238# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 239# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 241 242#define R300_CMD_SCRATCH 8 243#define R300_CMD_R500FP 9 244 245typedef union { 246 unsigned int u; 247 struct { 248 unsigned char cmd_type, pad0, pad1, pad2; 249 } header; 250 struct { 251 unsigned char cmd_type, count, reglo, reghi; 252 } packet0; 253 struct { 254 unsigned char cmd_type, count, adrlo, adrhi; 255 } vpu; 256 struct { 257 unsigned char cmd_type, packet, pad0, pad1; 258 } packet3; 259 struct { 260 unsigned char cmd_type, packet; 261 unsigned short count; /* amount of packet2 to emit */ 262 } delay; 263 struct { 264 unsigned char cmd_type, buf_idx, pad0, pad1; 265 } dma; 266 struct { 267 unsigned char cmd_type, flags, pad0, pad1; 268 } wait; 269 struct { 270 unsigned char cmd_type, reg, n_bufs, flags; 271 } scratch; 272 struct { 273 unsigned char cmd_type, count, adrlo, adrhi_flags; 274 } r500fp; 275} drm_r300_cmd_header_t; 276 277#define RADEON_FRONT 0x1 278#define RADEON_BACK 0x2 279#define RADEON_DEPTH 0x4 280#define RADEON_STENCIL 0x8 281#define RADEON_CLEAR_FASTZ 0x80000000 282#define RADEON_USE_HIERZ 0x40000000 283#define RADEON_USE_COMP_ZBUF 0x20000000 284 285#define R500FP_CONSTANT_TYPE (1 << 1) 286#define R500FP_CONSTANT_CLAMP (1 << 2) 287 288/* Primitive types 289 */ 290#define RADEON_POINTS 0x1 291#define RADEON_LINES 0x2 292#define RADEON_LINE_STRIP 0x3 293#define RADEON_TRIANGLES 0x4 294#define RADEON_TRIANGLE_FAN 0x5 295#define RADEON_TRIANGLE_STRIP 0x6 296 297/* Vertex/indirect buffer size 298 */ 299#define RADEON_BUFFER_SIZE 65536 300 301/* Byte offsets for indirect buffer data 302 */ 303#define RADEON_INDEX_PRIM_OFFSET 20 304 305#define RADEON_SCRATCH_REG_OFFSET 32 306#define R600_SCRATCH_REG_OFFSET 256 307 308#define RADEON_NR_SAREA_CLIPRECTS 12 309 310/* There are 2 heaps (local/GART). Each region within a heap is a 311 * minimum of 64k, and there are at most 64 of them per heap. 312 */ 313#define RADEON_LOCAL_TEX_HEAP 0 314#define RADEON_GART_TEX_HEAP 1 315#define RADEON_NR_TEX_HEAPS 2 316#define RADEON_NR_TEX_REGIONS 64 317#define RADEON_LOG_TEX_GRANULARITY 16 318 319#define RADEON_MAX_TEXTURE_LEVELS 12 320#define RADEON_MAX_TEXTURE_UNITS 3 321 322#define RADEON_MAX_SURFACES 8 323 324/* Blits have strict offset rules. All blit offset must be aligned on 325 * a 1K-byte boundary. 326 */ 327#define RADEON_OFFSET_SHIFT 10 328#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 329#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 330 331#endif /* __RADEON_SAREA_DEFINES__ */ 332 333typedef struct { 334 unsigned int red; 335 unsigned int green; 336 unsigned int blue; 337 unsigned int alpha; 338} radeon_color_regs_t; 339 340typedef struct { 341 /* Context state */ 342 unsigned int pp_misc; /* 0x1c14 */ 343 unsigned int pp_fog_color; 344 unsigned int re_solid_color; 345 unsigned int rb3d_blendcntl; 346 unsigned int rb3d_depthoffset; 347 unsigned int rb3d_depthpitch; 348 unsigned int rb3d_zstencilcntl; 349 350 unsigned int pp_cntl; /* 0x1c38 */ 351 unsigned int rb3d_cntl; 352 unsigned int rb3d_coloroffset; 353 unsigned int re_width_height; 354 unsigned int rb3d_colorpitch; 355 unsigned int se_cntl; 356 357 /* Vertex format state */ 358 unsigned int se_coord_fmt; /* 0x1c50 */ 359 360 /* Line state */ 361 unsigned int re_line_pattern; /* 0x1cd0 */ 362 unsigned int re_line_state; 363 364 unsigned int se_line_width; /* 0x1db8 */ 365 366 /* Bumpmap state */ 367 unsigned int pp_lum_matrix; /* 0x1d00 */ 368 369 unsigned int pp_rot_matrix_0; /* 0x1d58 */ 370 unsigned int pp_rot_matrix_1; 371 372 /* Mask state */ 373 unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 374 unsigned int rb3d_ropcntl; 375 unsigned int rb3d_planemask; 376 377 /* Viewport state */ 378 unsigned int se_vport_xscale; /* 0x1d98 */ 379 unsigned int se_vport_xoffset; 380 unsigned int se_vport_yscale; 381 unsigned int se_vport_yoffset; 382 unsigned int se_vport_zscale; 383 unsigned int se_vport_zoffset; 384 385 /* Setup state */ 386 unsigned int se_cntl_status; /* 0x2140 */ 387 388 /* Misc state */ 389 unsigned int re_top_left; /* 0x26c0 */ 390 unsigned int re_misc; 391} drm_radeon_context_regs_t; 392 393typedef struct { 394 /* Zbias state */ 395 unsigned int se_zbias_factor; /* 0x1dac */ 396 unsigned int se_zbias_constant; 397} drm_radeon_context2_regs_t; 398 399/* Setup registers for each texture unit 400 */ 401typedef struct { 402 unsigned int pp_txfilter; 403 unsigned int pp_txformat; 404 unsigned int pp_txoffset; 405 unsigned int pp_txcblend; 406 unsigned int pp_txablend; 407 unsigned int pp_tfactor; 408 unsigned int pp_border_color; 409} drm_radeon_texture_regs_t; 410 411typedef struct { 412 unsigned int start; 413 unsigned int finish; 414 unsigned int prim:8; 415 unsigned int stateidx:8; 416 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 417 unsigned int vc_format; /* vertex format */ 418} drm_radeon_prim_t; 419 420typedef struct { 421 drm_radeon_context_regs_t context; 422 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 423 drm_radeon_context2_regs_t context2; 424 unsigned int dirty; 425} drm_radeon_state_t; 426 427typedef struct { 428 /* The channel for communication of state information to the 429 * kernel on firing a vertex buffer with either of the 430 * obsoleted vertex/index ioctls. 431 */ 432 drm_radeon_context_regs_t context_state; 433 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 434 unsigned int dirty; 435 unsigned int vertsize; 436 unsigned int vc_format; 437 438 /* The current cliprects, or a subset thereof. 439 */ 440 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 441 unsigned int nbox; 442 443 /* Counters for client-side throttling of rendering clients. 444 */ 445 unsigned int last_frame; 446 unsigned int last_dispatch; 447 unsigned int last_clear; 448 449 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 450 1]; 451 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 452 int ctx_owner; 453 int pfState; /* number of 3d windows (0,1,2ormore) */ 454 int pfCurrentPage; /* which buffer is being displayed? */ 455 int crtc2_base; /* CRTC2 frame offset */ 456 int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 457} drm_radeon_sarea_t; 458 459/* WARNING: If you change any of these defines, make sure to change the 460 * defines in the Xserver file (xf86drmRadeon.h) 461 * 462 * KW: actually it's illegal to change any of this (backwards compatibility). 463 */ 464 465/* Radeon specific ioctls 466 * The device specific ioctl range is 0x40 to 0x79. 467 */ 468#define DRM_RADEON_CP_INIT 0x00 469#define DRM_RADEON_CP_START 0x01 470#define DRM_RADEON_CP_STOP 0x02 471#define DRM_RADEON_CP_RESET 0x03 472#define DRM_RADEON_CP_IDLE 0x04 473#define DRM_RADEON_RESET 0x05 474#define DRM_RADEON_FULLSCREEN 0x06 475#define DRM_RADEON_SWAP 0x07 476#define DRM_RADEON_CLEAR 0x08 477#define DRM_RADEON_VERTEX 0x09 478#define DRM_RADEON_INDICES 0x0A 479#define DRM_RADEON_NOT_USED 480#define DRM_RADEON_STIPPLE 0x0C 481#define DRM_RADEON_INDIRECT 0x0D 482#define DRM_RADEON_TEXTURE 0x0E 483#define DRM_RADEON_VERTEX2 0x0F 484#define DRM_RADEON_CMDBUF 0x10 485#define DRM_RADEON_GETPARAM 0x11 486#define DRM_RADEON_FLIP 0x12 487#define DRM_RADEON_ALLOC 0x13 488#define DRM_RADEON_FREE 0x14 489#define DRM_RADEON_INIT_HEAP 0x15 490#define DRM_RADEON_IRQ_EMIT 0x16 491#define DRM_RADEON_IRQ_WAIT 0x17 492#define DRM_RADEON_CP_RESUME 0x18 493#define DRM_RADEON_SETPARAM 0x19 494#define DRM_RADEON_SURF_ALLOC 0x1a 495#define DRM_RADEON_SURF_FREE 0x1b 496/* KMS ioctl */ 497#define DRM_RADEON_GEM_INFO 0x1c 498#define DRM_RADEON_GEM_CREATE 0x1d 499#define DRM_RADEON_GEM_MMAP 0x1e 500#define DRM_RADEON_GEM_PREAD 0x21 501#define DRM_RADEON_GEM_PWRITE 0x22 502#define DRM_RADEON_GEM_SET_DOMAIN 0x23 503#define DRM_RADEON_GEM_WAIT_IDLE 0x24 504#define DRM_RADEON_CS 0x26 505#define DRM_RADEON_INFO 0x27 506#define DRM_RADEON_GEM_SET_TILING 0x28 507#define DRM_RADEON_GEM_GET_TILING 0x29 508#define DRM_RADEON_GEM_BUSY 0x2a 509 510#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 511#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 512#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 513#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 514#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 515#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 516#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 517#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 518#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 519#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 520#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 521#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 522#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 523#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 524#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 525#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 526#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 527#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 528#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 529#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 530#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 531#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 532#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 533#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 534#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 535#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 536#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 537/* KMS */ 538#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 539#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 540#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 541#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 542#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 543#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 544#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 545#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 546#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 547#define DRM_IOCTL_RADEON_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 548#define DRM_IOCTL_RADEON_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 549#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 550 551typedef struct drm_radeon_init { 552 enum { 553 RADEON_INIT_CP = 0x01, 554 RADEON_CLEANUP_CP = 0x02, 555 RADEON_INIT_R200_CP = 0x03, 556 RADEON_INIT_R300_CP = 0x04, 557 RADEON_INIT_R600_CP = 0x05 558 } func; 559 unsigned long sarea_priv_offset; 560 int is_pci; /* for overriding only */ 561 int cp_mode; 562 int gart_size; 563 int ring_size; 564 int usec_timeout; 565 566 unsigned int fb_bpp; 567 unsigned int front_offset, front_pitch; 568 unsigned int back_offset, back_pitch; 569 unsigned int depth_bpp; 570 unsigned int depth_offset, depth_pitch; 571 572 unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */ 573 unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */ 574 unsigned long ring_offset; 575 unsigned long ring_rptr_offset; 576 unsigned long buffers_offset; 577 unsigned long gart_textures_offset; 578} drm_radeon_init_t; 579 580typedef struct drm_radeon_cp_stop { 581 int flush; 582 int idle; 583} drm_radeon_cp_stop_t; 584 585typedef struct drm_radeon_fullscreen { 586 enum { 587 RADEON_INIT_FULLSCREEN = 0x01, 588 RADEON_CLEANUP_FULLSCREEN = 0x02 589 } func; 590} drm_radeon_fullscreen_t; 591 592#define CLEAR_X1 0 593#define CLEAR_Y1 1 594#define CLEAR_X2 2 595#define CLEAR_Y2 3 596#define CLEAR_DEPTH 4 597 598typedef union drm_radeon_clear_rect { 599 float f[5]; 600 unsigned int ui[5]; 601} drm_radeon_clear_rect_t; 602 603typedef struct drm_radeon_clear { 604 unsigned int flags; 605 unsigned int clear_color; 606 unsigned int clear_depth; 607 unsigned int color_mask; 608 unsigned int depth_mask; /* misnamed field: should be stencil */ 609 drm_radeon_clear_rect_t __user *depth_boxes; 610} drm_radeon_clear_t; 611 612typedef struct drm_radeon_vertex { 613 int prim; 614 int idx; /* Index of vertex buffer */ 615 int count; /* Number of vertices in buffer */ 616 int discard; /* Client finished with buffer? */ 617} drm_radeon_vertex_t; 618 619typedef struct drm_radeon_indices { 620 int prim; 621 int idx; 622 int start; 623 int end; 624 int discard; /* Client finished with buffer? */ 625} drm_radeon_indices_t; 626 627/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 628 * - allows multiple primitives and state changes in a single ioctl 629 * - supports driver change to emit native primitives 630 */ 631typedef struct drm_radeon_vertex2 { 632 int idx; /* Index of vertex buffer */ 633 int discard; /* Client finished with buffer? */ 634 int nr_states; 635 drm_radeon_state_t __user *state; 636 int nr_prims; 637 drm_radeon_prim_t __user *prim; 638} drm_radeon_vertex2_t; 639 640/* v1.3 - obsoletes drm_radeon_vertex2 641 * - allows arbitarily large cliprect list 642 * - allows updating of tcl packet, vector and scalar state 643 * - allows memory-efficient description of state updates 644 * - allows state to be emitted without a primitive 645 * (for clears, ctx switches) 646 * - allows more than one dma buffer to be referenced per ioctl 647 * - supports tcl driver 648 * - may be extended in future versions with new cmd types, packets 649 */ 650typedef struct drm_radeon_cmd_buffer { 651 int bufsz; 652 char __user *buf; 653 int nbox; 654 struct drm_clip_rect __user *boxes; 655} drm_radeon_cmd_buffer_t; 656 657typedef struct drm_radeon_tex_image { 658 unsigned int x, y; /* Blit coordinates */ 659 unsigned int width, height; 660 const void __user *data; 661} drm_radeon_tex_image_t; 662 663typedef struct drm_radeon_texture { 664 unsigned int offset; 665 int pitch; 666 int format; 667 int width; /* Texture image coordinates */ 668 int height; 669 drm_radeon_tex_image_t __user *image; 670} drm_radeon_texture_t; 671 672typedef struct drm_radeon_stipple { 673 unsigned int __user *mask; 674} drm_radeon_stipple_t; 675 676typedef struct drm_radeon_indirect { 677 int idx; 678 int start; 679 int end; 680 int discard; 681} drm_radeon_indirect_t; 682 683/* enum for card type parameters */ 684#define RADEON_CARD_PCI 0 685#define RADEON_CARD_AGP 1 686#define RADEON_CARD_PCIE 2 687 688/* 1.3: An ioctl to get parameters that aren't available to the 3d 689 * client any other way. 690 */ 691#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 692#define RADEON_PARAM_LAST_FRAME 2 693#define RADEON_PARAM_LAST_DISPATCH 3 694#define RADEON_PARAM_LAST_CLEAR 4 695/* Added with DRM version 1.6. */ 696#define RADEON_PARAM_IRQ_NR 5 697#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 698/* Added with DRM version 1.8. */ 699#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 700#define RADEON_PARAM_STATUS_HANDLE 8 701#define RADEON_PARAM_SAREA_HANDLE 9 702#define RADEON_PARAM_GART_TEX_HANDLE 10 703#define RADEON_PARAM_SCRATCH_OFFSET 11 704#define RADEON_PARAM_CARD_TYPE 12 705#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 706#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 707#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 708#define RADEON_PARAM_DEVICE_ID 16 709#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 710 711typedef struct drm_radeon_getparam { 712 int param; 713 void __user *value; 714} drm_radeon_getparam_t; 715 716/* 1.6: Set up a memory manager for regions of shared memory: 717 */ 718#define RADEON_MEM_REGION_GART 1 719#define RADEON_MEM_REGION_FB 2 720 721typedef struct drm_radeon_mem_alloc { 722 int region; 723 int alignment; 724 int size; 725 int __user *region_offset; /* offset from start of fb or GART */ 726} drm_radeon_mem_alloc_t; 727 728typedef struct drm_radeon_mem_free { 729 int region; 730 int region_offset; 731} drm_radeon_mem_free_t; 732 733typedef struct drm_radeon_mem_init_heap { 734 int region; 735 int size; 736 int start; 737} drm_radeon_mem_init_heap_t; 738 739/* 1.6: Userspace can request & wait on irq's: 740 */ 741typedef struct drm_radeon_irq_emit { 742 int __user *irq_seq; 743} drm_radeon_irq_emit_t; 744 745typedef struct drm_radeon_irq_wait { 746 int irq_seq; 747} drm_radeon_irq_wait_t; 748 749/* 1.10: Clients tell the DRM where they think the framebuffer is located in 750 * the card's address space, via a new generic ioctl to set parameters 751 */ 752 753typedef struct drm_radeon_setparam { 754 unsigned int param; 755 int64_t value; 756} drm_radeon_setparam_t; 757 758#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 759#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 760#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 761#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 762#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 763#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 764/* 1.14: Clients can allocate/free a surface 765 */ 766typedef struct drm_radeon_surface_alloc { 767 unsigned int address; 768 unsigned int size; 769 unsigned int flags; 770} drm_radeon_surface_alloc_t; 771 772typedef struct drm_radeon_surface_free { 773 unsigned int address; 774} drm_radeon_surface_free_t; 775 776#define DRM_RADEON_VBLANK_CRTC1 1 777#define DRM_RADEON_VBLANK_CRTC2 2 778 779/* 780 * Kernel modesetting world below. 781 */ 782#define RADEON_GEM_DOMAIN_CPU 0x1 783#define RADEON_GEM_DOMAIN_GTT 0x2 784#define RADEON_GEM_DOMAIN_VRAM 0x4 785 786struct drm_radeon_gem_info { 787 uint64_t gart_size; 788 uint64_t vram_size; 789 uint64_t vram_visible; 790}; 791 792#define RADEON_GEM_NO_BACKING_STORE 1 793 794struct drm_radeon_gem_create { 795 uint64_t size; 796 uint64_t alignment; 797 uint32_t handle; 798 uint32_t initial_domain; 799 uint32_t flags; 800}; 801 802#define RADEON_TILING_MACRO 0x1 803#define RADEON_TILING_MICRO 0x2 804#define RADEON_TILING_SWAP 0x4 805#define RADEON_TILING_SURFACE 0x8 /* this object requires a surface 806 * when mapped - i.e. front buffer */ 807 808struct drm_radeon_gem_set_tiling { 809 uint32_t handle; 810 uint32_t tiling_flags; 811 uint32_t pitch; 812}; 813 814struct drm_radeon_gem_get_tiling { 815 uint32_t handle; 816 uint32_t tiling_flags; 817 uint32_t pitch; 818}; 819 820struct drm_radeon_gem_mmap { 821 uint32_t handle; 822 uint32_t pad; 823 uint64_t offset; 824 uint64_t size; 825 uint64_t addr_ptr; 826}; 827 828struct drm_radeon_gem_set_domain { 829 uint32_t handle; 830 uint32_t read_domains; 831 uint32_t write_domain; 832}; 833 834struct drm_radeon_gem_wait_idle { 835 uint32_t handle; 836 uint32_t pad; 837}; 838 839struct drm_radeon_gem_busy { 840 uint32_t handle; 841 uint32_t domain; 842}; 843 844struct drm_radeon_gem_pread { 845 /** Handle for the object being read. */ 846 uint32_t handle; 847 uint32_t pad; 848 /** Offset into the object to read from */ 849 uint64_t offset; 850 /** Length of data to read */ 851 uint64_t size; 852 /** Pointer to write the data into. */ 853 /* void *, but pointers are not 32/64 compatible */ 854 uint64_t data_ptr; 855}; 856 857struct drm_radeon_gem_pwrite { 858 /** Handle for the object being written to. */ 859 uint32_t handle; 860 uint32_t pad; 861 /** Offset into the object to write to */ 862 uint64_t offset; 863 /** Length of data to write */ 864 uint64_t size; 865 /** Pointer to read the data from. */ 866 /* void *, but pointers are not 32/64 compatible */ 867 uint64_t data_ptr; 868}; 869 870#define RADEON_CHUNK_ID_RELOCS 0x01 871#define RADEON_CHUNK_ID_IB 0x02 872 873struct drm_radeon_cs_chunk { 874 uint32_t chunk_id; 875 uint32_t length_dw; 876 uint64_t chunk_data; 877}; 878 879struct drm_radeon_cs_reloc { 880 uint32_t handle; 881 uint32_t read_domains; 882 uint32_t write_domain; 883 uint32_t flags; 884}; 885 886struct drm_radeon_cs { 887 uint32_t num_chunks; 888 uint32_t cs_id; 889 /* this points to uint64_t * which point to cs chunks */ 890 uint64_t chunks; 891 /* updates to the limits after this CS ioctl */ 892 uint64_t gart_limit; 893 uint64_t vram_limit; 894}; 895 896#define RADEON_INFO_DEVICE_ID 0x00 897#define RADEON_INFO_NUM_GB_PIPES 0x01 898#define RADEON_INFO_NUM_Z_PIPES 0x02 899 900struct drm_radeon_info { 901 uint32_t request; 902 uint32_t pad; 903 uint64_t value; 904}; 905 906#endif 907