1#ifndef _H_MSM_VPU_H_ 2#define _H_MSM_VPU_H_ 3 4#include <linux/videodev2.h> 5 6/* 7 * V 4 L 2 E X T E N S I O N S B Y V P U 8 */ 9 10/* 11 * v4l2_buffer: 12 * 13 * VPU uses multi-plane v4l2_buffer in the following manner: 14 * each plane can be a separate ION buffer, or all planes are from the 15 * same ION buffer (under this case all planes have the same fd, but different 16 * offset). 17 * 18 * For struct v4l2_plane 19 * fd: ION fd representing the ION buffer this plane is from 20 * reserved[0]: offset of this plane from the start of the ION buffer in 21 * bytes. Needed when all planes are from the same ION buffer. 22 */ 23#define V4L2_PLANE_MEM_OFFSET 0 24 25/* 26 * struct v4l2_format: 27 * always use v4l2_pix_format_mplane, even when there is only one plane 28 * 29 * v4l2_pix_format_mplane: 30 * 31 * VPU uses v4l2_pix_format_mplane for pixel format configuration 32 * The following members of this structure is either extended or changed: 33 * pixelformat: extended, a few more private formats added 34 * colorspace: possible values are enum vpu_colorspace 35 * field: when it is V4L2_FIELD_ALTERNATE, flags from vpu format extension 36 * specifies which field first. 37 * reserved[]: VPU format extension. struct v4l2_format_vpu_extension 38 */ 39enum vpu_colorspace { 40 VPU_CS_MIN = 0, 41 /* RGB with full range*/ 42 VPU_CS_RGB_FULL = 1, 43 /* RGB with limited range*/ 44 VPU_CS_RGB_LIMITED = 2, 45 /* REC 601 with full range */ 46 VPU_CS_REC601_FULL = 3, 47 /* REC 601 with limited range */ 48 VPU_CS_REC601_LIMITED = 4, 49 /* REC 709 with full range */ 50 VPU_CS_REC709_FULL = 5, 51 /* REC 709 with limited range */ 52 VPU_CS_REC709_LIMITED = 6, 53 /* SMPTE 240 with full range */ 54 VPU_CS_SMPTE240_FULL = 7, 55 /* SMPTE 240 with limited range */ 56 VPU_CS_SMPTE240_LIMITED = 8, 57 VPU_CS_MAX = 9, 58}; 59 60 61#define VPU_FMT_EXT_FLAG_BT 1 /* bottom field first */ 62#define VPU_FMT_EXT_FLAG_TB 2 /* top field first */ 63#define VPU_FMT_EXT_FLAG_3D 4 /* 3D format */ 64struct v4l2_format_vpu_extension { 65 __u8 flag; 66 __u8 gap_in_lines; 67}; 68 69/* 70 * Supported pixel formats: 71 * 72 * VPU supported pixel format fourcc codes (use in s_fmt pixelformat field). 73 * Can be enumerated using VIDIOC_ENUM_FMT 74 * 75 * Standard V4L2 formats, defined in videodev2.h : 76 * 77 * V4L2_PIX_FMT_RGB24 24 bit RGB-8-8-8 78 * V4L2_PIX_FMT_RGB32 32 bit XRGB-8-8-8-8 79 * V4L2_PIX_FMT_BGR24 24 bit BGR-8-8-8 80 * V4L2_PIX_FMT_BGR32 32 bit BGRX-8-8-8-8 81 * 82 * V4L2_PIX_FMT_NV12 12 bit YUV 4:2:0 semi-planar NV12 83 * V4L2_PIX_FMT_NV21 12 bit YUV 4:2:0 semi-planar NV21 84 * V4L2_PIX_FMT_YUYV 16 bit YUYV 4:2:2 interleaved 85 * V4L2_PIX_FMT_YVYU 16 bit YVYU 4:2:2 interleaved 86 * V4L2_PIX_FMT_UYVY 16 bit UYVY 4:2:2 interleaved 87 * V4L2_PIX_FMT_VYUY 16 bit VYUY 4:2:2 interleaved 88 * 89 * 90 * Private VPU formats, defined here : 91 * 92 * V4L2_PIX_FMT_XRGB2 32 bit XRGB-2-10-10-10 93 * V4L2_PIX_FMT_XBGR2 32 bit XBGR-2-10-10-10 94 * 95 * V4L2_PIX_FMT_YUYV10 24 bit YUYV 4:2:2 10 bit per component loose 96 * V4L2_PIX_FMT_YUV8 24 bit YUV 4:4:4 8 bit per component 97 * V4L2_PIX_FMT_YUV10 32 bit YUV 4:4:4 10 bit per component loose 98 * V4L2_PIX_FMT_YUYV10BWC 10 bit YUYV 4:2:2 compressed, for output only 99 */ 100#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2') 101#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2') 102#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L') 103#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8') 104#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L') 105#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C') 106 107/* 108 * VIDIOC_S_INPUT/VIDIOC_S_OUTPUT 109 * 110 * The single integer passed by these commands specifies port type in the 111 * lower 16 bits, and pipe bit mask in the higher 16 bits. 112 */ 113/* input / output types */ 114#define VPU_INPUT_TYPE_HOST 0 115#define VPU_INPUT_TYPE_VCAP 1 116#define VPU_OUTPUT_TYPE_HOST 0 117#define VPU_OUTPUT_TYPE_DISPLAY 1 118 119/* input / output pipe bit fields */ 120#define VPU_PIPE_VCAP0 (1 << 16) 121#define VPU_PIPE_VCAP1 (1 << 17) 122#define VPU_PIPE_DISPLAY0 (1 << 18) 123#define VPU_PIPE_DISPLAY1 (1 << 19) 124#define VPU_PIPE_DISPLAY2 (1 << 20) 125#define VPU_PIPE_DISPLAY3 (1 << 21) 126 127/* 128 * V P U E V E N T S : I D s A N D D A T A P A Y L O A D S 129 */ 130 131/* 132 * Event ID: set in type field of struct v4l2_event 133 * payload: returned in u.data array of struct v4l2_event 134 * 135 * 136 * VPU_EVENT_FLUSH_DONE: Done flushing buffers after VPU_FLUSH_BUFS ioctl 137 * payload data: enum v4l2_buf_type (buffer type of flushed port) 138 * 139 * VPU_EVENT_ACTIVE_REGION_CHANGED: New Active Region Detected 140 * payload data: struct v4l2_rect (new active region rectangle) 141 * 142 * VPU_EVENT_SESSION_TIMESTAMP: New Session timestamp 143 * payload data: vpu_frame_timestamp_info 144 * 145 * 146 * VPU_EVENT_HW_ERROR: a hardware error occurred in VPU 147 * payload data: NULL 148 * 149 * VPU_EVENT_INVALID_CONFIG: invalid VPU session configuration 150 * payload data: NULL 151 * 152 * VPU_EVENT_FAILED_SESSION_STREAMING: Failed to stream session 153 * payload data: NULL 154 */ 155#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000) 156enum VPU_PRIVATE_EVENT { 157 VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE, 158 159 VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1, 160 VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2, 161 VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3, 162 163 VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11, 164 VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12, 165 VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13, 166 167 VPU_EVENT_END 168}; 169 170 171/* 172 * V P U CO N T R O L S : S T R U C T S A N D I D s 173 * 174 * Controls are video processing parameters 175 */ 176 177/* 178 * Standard VPU Controls 179 */ 180struct vpu_ctrl_standard { 181 __u32 enable; /* boolean: 0=disable, else=enable */ 182 __s32 value; 183}; 184 185struct vpu_ctrl_auto_manual { 186 __u32 enable; /* boolean: 0=disable, else=enable */ 187 __u32 auto_mode; /* boolean: 0=manual, else=automatic */ 188 __s32 value; 189}; 190 191struct vpu_ctrl_range_mapping { 192 __u32 enable; /* boolean: 0=disable, else=enable */ 193 __u32 y_range; /* the range mapping set for Y [0, 7] */ 194 __u32 uv_range; /* the range mapping set for UV [0, 7] */ 195}; 196 197#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1 198struct vpu_ctrl_active_region_param { 199 __u32 enable; /* boolean: 0=disable, else=enable */ 200 /* number of exclusion regions */ 201 __u32 num_exclusions; 202 /* roi where active region detection is applied */ 203 struct v4l2_rect detection_region; 204 /* roi(s) excluded from active region detection*/ 205 struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS]; 206}; 207 208struct vpu_ctrl_deinterlacing_mode { 209 __u32 field_polarity; 210 __u32 mvp_mode; 211}; 212 213struct vpu_ctrl_hqv { 214 __u32 enable; 215 /* strength control of all sharpening features [0, 100] */ 216 __u32 sharpen_strength; 217 /* strength control of Auto NR feature [0, 100] */ 218 __u32 auto_nr_strength; 219}; 220 221struct vpu_info_frame_timestamp { 222 /* presentation timestamp of the frame */ 223 __u32 pts_low; 224 __u32 pts_high; 225 /* qtimer snapshot */ 226 __u32 qtime_low; 227 __u32 qtime_high; 228}; 229 230struct vpu_control { 231 __u32 control_id; 232 union control_data { 233 __s32 value; 234 struct vpu_ctrl_standard standard; 235 struct vpu_ctrl_auto_manual auto_manual; 236 struct vpu_ctrl_range_mapping range_mapping; 237 struct vpu_ctrl_active_region_param active_region_param; 238 struct v4l2_rect active_region_result; 239 struct vpu_ctrl_deinterlacing_mode deinterlacing_mode; 240 struct vpu_ctrl_hqv hqv; 241 struct vpu_info_frame_timestamp timestamp; 242 __u8 reserved[124]; 243 } data; 244}; 245 246/* 247 * IDs for standard controls (use in control_id field of struct vpu_control) 248 * 249 * VPU_CTRL_NOISE_REDUCTION: noise reduction level, data: auto_manual, 250 * value: [0, 100] (step in increments of 25). 251 * 252 * VPU_CTRL_IMAGE_ENHANCEMENT: image enhancement level, data: auto_manual, 253 * value: [-100, 100] (step in increments of 1). 254 * 255 * VPU_CTRL_ANAMORPHIC_SCALING: anamorphic scaling config, data: standard, 256 * value: [0, 100] (step in increments of 1). 257 * 258 * VPU_CTRL_DIRECTIONAL_INTERPOLATION: directional interpolation config 259 * data: standard, value: [0, 100] (step in increments of 1). 260 * 261 * VPU_CTRL_BACKGROUND_COLOR: , data: value, 262 * value: red[0:7] green[8:15] blue[16:23] alpha[24:31] 263 * 264 * VPU_CTRL_RANGE_MAPPING: Y/UV range mapping, data: range_mapping, 265 * y_range: [0, 7], uv_range: [0, 7] (step in increments of 1). 266 * 267 * VPU_CTRL_DEINTERLACING_MODE: deinterlacing mode, data: deinterlacing_mode, 268 * field_polarity: [0, 2], mvp_mode: [0, 2] (step in increments of 1). 269 * 270 * VPU_CTRL_ACTIVE_REGION_PARAM: active region detection parameters (set only) 271 * data: active_region_param, 272 * 273 * VPU_CTRL_ACTIVE_REGION_RESULT: detected active region roi (get only) 274 * data: active_region_result 275 * 276 * VPU_CTRL_PRIORITY: Session priority, data: value, 277 * value: high 100, normal 50 278 * 279 * VPU_CTRL_CONTENT_PROTECTION: input content protection status, data: value, 280 * value: secure 1, non-secure 0 281 * 282 * VPU_CTRL_DISPLAY_REFRESH_RATE: display refresh rate (set only) 283 * data: value (set to __u32 16.16 format) 284 * 285 * VPU_CTRL_HQV: hqv block config, data: hqv, 286 * sharpen_strength: [0, 100] (step in increments of 25), 287 * auto_nr_strength: [0, 100] (step in increments of 1). 288 * 289 * VPU_CTRL_HQV_SHARPEN: , data: value, 290 * sharpen_strength: [0, 100] (step in increments of 1). 291 * 292 * VPU_CTRL_HQV_AUTONR: , data: value, 293 * auto_nr_strength: [0, 100] (step in increments of 1). 294 * 295 * VPU_CTRL_ACE: , data: value 296 * 297 * VPU_CTRL_ACE_BRIGHTNESS: , data: value, 298 * value: [-100, 100] (step in increments of 1). 299 * 300 * VPU_CTRL_ACE_CONTRAST: , data: value, 301 * value: [-100, 100] (step in increments of 1). 302 * 303 * VPU_CTRL_2D3D: , data: value, 304 * value: 1 enabled, 0 disabled 305 * 306 * VPU_CTRL_2D3D_DEPTH: , data: value, 307 * value: [0, 100] (step in increments of 1). 308 * 309 * VPU_CTRL_TIMESTAMP_INFO_MODE: timestamp reporting mode, 310 * data: value specifying how frequent a timestamp reporting info, value 311 * is in frames 312 * 313 * VPU_INFO_TIMESTAMP: timestamp information (get only) 314 * data: struct vpu_frame_timestamp_info 315 * 316 * VPU_CTRL_FRC: enable/disable FRC, data: value, 317 * value: 1 enable, 0 disable 318 * 319 * VPU_CTRL_FRC_MOTION_SMOOTHNESS: , data: value, 320 * value: [0, 100] (step in increments of 1). 321 * 322 * VPU_CTRL_FRC_MOTION_CLEAR: , data: value, 323 * value: [0, 100] (step in increments of 1). 324 * 325 * VPU_CTRL_LATENCY: session latency, data: value in us 326 * 327 * VPU_CTRL_LATENCY_MODE: data: value (ultra low, low, etc.) 328 * 329 * VPU_INFO_STATISTICS: frames dropped, etc (get only), 330 * data: reserved 331 */ 332#define VPU_CTRL_ID_MIN 0 333 334#define VPU_CTRL_NOISE_REDUCTION 1 335#define VPU_CTRL_IMAGE_ENHANCEMENT 2 336#define VPU_CTRL_ANAMORPHIC_SCALING 3 337#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4 338#define VPU_CTRL_BACKGROUND_COLOR 5 339#define VPU_CTRL_RANGE_MAPPING 6 340#define VPU_CTRL_DEINTERLACING_MODE 7 341#define VPU_CTRL_ACTIVE_REGION_PARAM 8 342#define VPU_CTRL_ACTIVE_REGION_RESULT 9 343#define VPU_CTRL_PRIORITY 10 344#define VPU_CTRL_CONTENT_PROTECTION 11 345#define VPU_CTRL_DISPLAY_REFRESH_RATE 12 346 347#define VPU_CTRL_HQV 20 348#define VPU_CTRL_HQV_SHARPEN 21 349#define VPU_CTRL_HQV_AUTONR 22 350#define VPU_CTRL_ACE 23 351#define VPU_CTRL_ACE_BRIGHTNESS 24 352#define VPU_CTRL_ACE_CONTRAST 25 353#define VPU_CTRL_2D3D 26 354#define VPU_CTRL_2D3D_DEPTH 27 355#define VPU_CTRL_FRC 28 356#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29 357#define VPU_CTRL_FRC_MOTION_CLEAR 30 358 359#define VPU_INFO_TIMESTAMP 35 360#define VPU_CTRL_TIMESTAMP_INFO_MODE 36 361#define VPU_INFO_STATISTICS 37 362#define VPU_CTRL_LATENCY 38 363#define VPU_CTRL_LATENCY_MODE 39 364 365#define VPU_CTRL_ID_MAX 40 366 367 368/* 369 * Extended VPU Controls (large data payloads) 370 */ 371#define VPU_MAX_EXT_DATA_SIZE 720 372struct vpu_control_extended { 373 /* 374 * extended control type 375 * 0: system 376 * 1: session 377 */ 378 __u32 type; 379 380 /* 381 * size and ptr of the data to send 382 * maximum VPU_MAX_EXT_DATA_SIZE bytes 383 */ 384 __u32 data_len; 385 void __user *data_ptr; 386 387 /* 388 * size and ptr of the buffer to recv data 389 * maximum VPU_MAX_EXT_DATA_SIZE bytes 390 */ 391 __u32 buf_size; 392 void __user *buf_ptr; 393}; 394 395/* 396 * Port specific controls 397 */ 398struct vpu_control_port { 399 __u32 control_id; 400 __u32 port; /* 0: INPUT, 1: OUTPUT */ 401 union control_port_data { 402 __u32 framerate; 403 } data; 404}; 405 406/* 407 * IDs for port controls (use in control_id field of struct vpu_control_port) 408 * 409 * VPU_CTRL_FPS: set frame rate, data: __u32, 16.16 format 410 */ 411#define VPU_CTRL_FPS 1000 412 413 414/* 415 * V P U D E V I C E P R I V A T E I O C T L C O D E S 416 */ 417 418/* VPU Session ioctls */ 419#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int) 420#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int) 421#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int) 422 423/* Explicit commit of session configuration */ 424#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10)) 425 426/* Flush all buffers of given type (port) */ 427#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), \ 428 enum v4l2_buf_type) 429 430/* VPU controls get/set ioctls (for most controls with small data) */ 431#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), \ 432 struct vpu_control) 433#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), \ 434 struct vpu_control) 435 436/* extended control set/get ioctls (large data payloads) */ 437#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), \ 438 struct vpu_control_extended) 439#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), \ 440 struct vpu_control_extended) 441 442/* VPU port (input/output) specific controls get/set ioctls */ 443#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), \ 444 struct vpu_control_port) 445#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), \ 446 struct vpu_control_port) 447 448#endif /* _H_MSM_VPU_H_ */ 449 450