| eca91cf163d50090db36d0b2abbffcff813a2adf |
09-Jan-2015 |
Dave Airlie <airlied@redhat.com> |
radeon: align r600/700 fmask to 128 X blocks.
After much searching and empricial testing, and reading of
things I've no justifcation for this fix, other than it really
appears this is what the hw is doing or close enough.
It makes sense that each entry in the FMASK corresponds to
an entry in the CMASKm and the CMASK is organised into 128x128
blocks, but I can't find anything in any of the docs/info from AMD.
But I've spent a lot of time on this, and this seems to be the
simplest fix, in that we don't over allocate things too much,
once this fix in place we can nuke the extra multiplier in mesa.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
adeon_surface.c
|
| c866dc7c00e7f5f219901a9a81bf456a24d29cd1 |
26-Sep-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Always multiply pitch_bytes by nsamples, not by slice_pt
slice_pt is tileb[0] / tile_split, which isn't directly related to the
pitch.
This caused pitch_bytes to be too large in some cases.
[0] Tile size in bytes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
adeon_surface.c
|
| 6281cf1b4310ff0b7670677cb4113a89ebf0b619 |
07-Sep-2014 |
Emil Velikov <emil.l.velikov@gmail.com> |
radeon: use drm_mmap/drm_munmap wrappers
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
adeon_bo_gem.c
adeon_cs_gem.c
adeon_surface.c
|
| 268dce4192125ceb6a65f1c8d885e4b656310578 |
07-Sep-2014 |
Emil Velikov <emil.l.velikov@gmail.com> |
automake: pick up all files for distribution.
Autotools is already smart enough to pick the *.pc.in files but it
needs some help with the Android.mk ones.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
akefile.am
|
| adb1cdcdde23f21ad4dd21725e8a759c13c18dbf |
27-Jul-2014 |
Emil Velikov <emil.l.velikov@gmail.com> |
radeon: add Android build support
v2 Rename the headers variable(s) to *_H_FILES.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
ndroid.mk
|
| 4255d3d51dfe85be93d3e246f24b7bb56950a8c2 |
24-Aug-2014 |
Emil Velikov <emil.l.velikov@gmail.com> |
libdrm, freedreno, intel, nouveau, radeon: add Makefile.sources
Will be used to consolidate the required sources lists as well as the
install-able headers. This is turn will help us to avoid the
duplication with the upcoming Android build support.
v2: Rename the headers variable to *_H_FILES.
v3: Rebase on top of symbol visibility patches.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
akefile.am
akefile.sources
|
| 391bba9c4cd2825eadaa648df10e3d1c99c66e80 |
18-Aug-2014 |
Maks Naumov <maksqwe1@ukr.net> |
radeon: Fix surf->bankh init by default value when surf->tile_split == 0
Signed-off-by: Maks Naumov <maksqwe1@ukr.net>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
adeon_surface.c
|
| 22b995d8cbf1059535c5de5ba1869c1623ae5b08 |
21-Aug-2014 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 3ad801bf1fc4ad3becdcf329fc6fe807eb312e89 |
21-Aug-2014 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add new CIK pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 58ce9d6292c7033ff76bb2ef35da0e4c36de2389 |
31-Jul-2014 |
Maarten Lankhorst <maarten.lankhorst@canonical.com> |
radeon: Use symbol visibility.
All the bof_* symbols are now no longer exported.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
akefile.am
adeon_bo.c
adeon_bo_gem.c
adeon_cs.c
adeon_cs_gem.c
adeon_cs_space.c
adeon_surface.c
|
| 2169dce96c5503ef8f6e4bb008e989d0ef02ec8e |
26-Jul-2014 |
Marek Olšák <marek.olsak@amd.com> |
radeon: fix typo in sample split / fixes MSAA on Hawaii
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
adeon_surface.c
|
| 72f84b85afbe762b86ea8c095fee01e7d406b131 |
15-Jul-2014 |
Thomas Klausner <wiz@NetBSD.org> |
radeon: Remove superfluous parentheses.
Signed-off-by: Thomas Klausner <wiz@NetBSD.org>
adeon_surface.c
|
| 3bdf1f78d8abfb2552947d1990b40c7355b921fc |
12-Nov-2013 |
Samuel Li <samuel.li@amd.com> |
radeon: add Mullins pci ids
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
600_pci_ids.h
|
| c2bc8ad438693262480ce1426bcf5c1d8ec4e808 |
17-Apr-2014 |
Samuel Li <samuel.li@amd.com> |
radeon: add Mullins chip family
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
adeon_surface.c
|
| e8cbc579651ef55274763c67acb366dd4155e0ce |
24-Dec-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: fix sumo2 pci id
0x9649 is sumo2, not sumo.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 1543c96e154d6801cf725c3b511d61604a378e03 |
10-Dec-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: avoid possible divide by 0 in surface manager
Some users report hitting a divide by 0 with the tile split in
certain apps. Tile_split shouldn't ever be 0 unless the surface
structure was not properly initialized. I think there may be some
cases where mesa uses an improperly initialized surface struct,
but I haven't had time to track it down.
Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=72425
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
adeon_surface.c
|
| c8a437f4c76527b3c8385699ccee07f35fe3f166 |
26-Nov-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Update unaligned offset for 2D->1D tiling transition on SI
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71983
Tested-by: Arek Ruśniak <arek.rusi@gmail.com>
adeon_surface.c
|
| 3f4648902296efa3a8cc0abc941d978637f0ee28 |
23-Nov-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeon: handle P16 pipe configs for Hawaii
adeon_surface.c
|
| f0e399d8f0c3c006687e0fc8e68268087607d5f5 |
18-Nov-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: don't overallocate stencil by 4 on SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
adeon_surface.c
|
| 67d92404d62044972599dcef3011d17fca46eed5 |
22-Nov-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeon: implement 2D tiling for CIK
Bug fixes and simplification by Marek.
We have to use the tile index of 0 for non-MSAA depth-stencil after all.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
adeon_surface.h
|
| ce8af454259279c14c44bcd32c429640ca5e1691 |
14-Nov-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: fix mipmap level 0 and 1 alignment for SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| 1a84eea45bf9d3915698a04199c594a63fcca4a2 |
24-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add hawaii pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| efcc456030334a692e2fce7bbd279df3aee13a6d |
24-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add hawaii chip family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| 75f747b919e1b1cd852eeaa8e662e72273189fb2 |
19-Sep-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeon: fix pitch alignment for non-power-of-two mipmaps on SI
This fixes VM protection faults.
I have a new piglit test which can iterate over all possible widths, heights,
and depths (including NPOT) and tests mipmapping with various texture targets.
After this is committed, I'll make a new release of libdrm and bump
the libdrm version requirement in Mesa.
adeon_surface.c
|
| a48d6e5621fea701e36724cc144d9fe293332824 |
18-Sep-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIK
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| 58d008883165ba35c83041fa9ed84937163d5f76 |
06-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: pad CS to 8 DW
Aligns the IB to 8 DWs. The aligns the IB to the
CP fetch size. r6xx also require at least 4 DW
alignment to avoid a hw bug.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
adeon_cs_gem.c
|
| 8a2e0fa917996e72bfc0dbdf228fc0bfb433d279 |
25-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add berlin pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 378bb47a784a3808c9b256fe7a52e10a4fcabf92 |
25-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add kabini pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 96c04c23fca6656483f66ecb0da0679df02eb9c0 |
07-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add Bonaire pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 0ff7f2760d052503d5cf65ded34a66fe20ccec28 |
07-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add CIK chip families
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| a0178c00c70f4b47e09ed7564fc2ccde611231a0 |
05-Jun-2013 |
Mark Kettenis <kettenis@openbsd.org> |
radeon: correct RADEON_GEM_WAIT_IDLE use
RADEON_GEM_WAIT_IDLE is declared DRM_IOW but libdrm
uses it with drmCommandWriteRead instead of drmCommandWrite
which leads to the ioctl being unmatched and returning an
error on at least OpenBSD.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
adeon_bo_gem.c
|
| e5e51c2110ebf6e1edaa14b7567c5d6a79008a90 |
24-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
radeon: add RADEON_SURF_FMASK flag which disables 2D->1D tiling transition
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
adeon_surface.h
|
| 96e90aabc4c0238de2f2d245899f991a3b996587 |
13-May-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add HAINAN pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| c56729cc1564bb4204ca30a18499a78a39f48892 |
13-May-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add HAINAN family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| ec3c257eb6958da493aee6f010f51a07d7ba4160 |
25-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add new richland pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 439d7d74320a148a2d53aec1ca28eba672ad9353 |
25-Apr-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| a36cdb858e21f287d7b51ded2f211f1c84bda90b |
08-Apr-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon: add si tiling support v5
v2: Only writte tile index if flags for it is set
v3: Remove useless allow2d scanout flags
v4: Split radeon_drm.h update to its own patch
v5: update against lastest next tree for radeon
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
adeon_surface.c
adeon_surface.h
|
| 36a2daad2416ad55a859c483b0d7ed93a5eff6e0 |
08-Mar-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add pci ids for Richland APUs
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| ade2ad2d66ac341a12eca37bcb30d40199eb4e02 |
07-Mar-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeonsi: make sure tile_split field are not garbage
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| 353f073bc134a94d13fe82e4f3d983efe3cf70ad |
24-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add OLAND pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 76ae1f4837ceb2c15ccf847e4abe2b5c4f66df85 |
24-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add OLAND family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| 303ca37e722e68900cb7eb43ddbef8069b0c711b |
17-Jan-2013 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Fix 1D tiling layout on SI.
Very similar to Evergreen, but slightly different rules for tile / slice
alignment. Fortunately, these map quite naturally onto the previous fixes for
linear aligned layout on SI.
2D tiling still needs more work here and possibly in the kernel.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
adeon_surface.c
|
| 0980633afd9c7eecc0c75ef3bea4d3c6b7aa1898 |
27-Nov-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: track global bo name and always return the same
To avoid kernel rejecting cs if we return different global name
for same bo keep track of global name and always return the same.
Seems to fix issue with suspend/resume failing and repeatly printing
following message :
[drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -35!
There might still be way for a rogue program to trigger this issue.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_bo_gem.c
|
| 171666e4b8127c17c68ea0d44cf4e81ec342f2d0 |
22-Nov-2012 |
Alex Deucher <alexdeucher@gmail.com> |
radeon: add new SI pci id
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
600_pci_ids.h
|
| e32fff8e9ea8d522679eaab21a9555cab134fb36 |
16-Oct-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| bc494b310d76f701798aee0f2b0b472d608cbfaf |
28-Aug-2012 |
Andreas Boll <andreas.boll.dev@gmail.com> |
radeon: fix unused-function warning
radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but
not used [-Wunused-function]
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_cs_gem.c
|
| a4cb7233a8da171e53b48b376be5c1265c29a612 |
16-Oct-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add some new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 1aebfdc1121ccb6babb3a63dc0b99d68b4860b04 |
30-Sep-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI
This allows texturing with depth-stencil buffers directly without the copy
to CB. The separate miptree description for stencil is added, because
the stencil mipmap offsets are not really depth offsets/4 (at least
for the texture units).
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
adeon_surface.h
|
| 77413e77b82a5d800c86b7d3b864d6cc797721c9 |
30-Sep-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: don't force stencil tile split to 0
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| b3d90bbc1d43bb11d8de25109f403b1b30533c34 |
29-Sep-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: don't take the stencil-specific codepath for buffers without stencil
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| b925022a3e4616665b388a78abab4e3270b4b4ec |
05-Sep-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.
Another corner case that isn't well-explained yet.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
adeon_surface.c
|
| 45083e6d36125c64267c917da3d81e1e144ed33d |
04-Sep-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Memory footprint of SI mipmap base level is padded to powers of two.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
adeon_surface.c
|
| 8572444fd0cda3e7b9557c09d2d0f7a9e049a2e7 |
31-Aug-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Fix layout of linear aligned mipmaps on SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
adeon_surface.c
|
| 853429b939c792c4bc0bc91fdef696e3251b88d9 |
20-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: align r600 msaa buffers to a multiple of macrotile size * num samples
I am not sure whether this is needed, but better be safe than sorry.
adeon_surface.c
|
| 58545722d0ee52f112859322466d9366915575b5 |
19-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: fix allocation of MSAA surfaces on r600-r700
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| 3163cfe4db925429760407e77140e2d595338bc2 |
12-Jun-2012 |
Dave Airlie <airlied@redhat.com> |
radeon: add prime import/export support
this adds radeon version of the prime import/export support.
Signed-off-by: Dave Airlie <airlied@redhat.com>
akefile.am
adeon_bo_gem.c
adeon_bo_gem.h
|
| 128803a107fde8ce36036e59437a536fc4d46553 |
07-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: tweak TILE_SPLIT for MSAA surfaces
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| e14aedce64e365ef1a8726ed8c1ebed881d7a398 |
07-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: force 2D tiling for MSAA surfaces
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| 23372955730048bbcddafc74365d911f9a74fb13 |
29-Jul-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG
If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
v2: actually do it correctly
Reviewed-by: Christian König <christian.koenig@amd.com>
adeon_surface.c
|
| ad66c17209811acdae21e44290a449523882a734 |
29-Jul-2012 |
Marek Olšák <maraeo@gmail.com> |
radeon: simplify ZS buffer checking on r600
Setting those flags has no effect anywhere else.
Reviewed-by: Christian König <christian.koenig@amd.com>
adeon_surface.c
|
| 9f823ca236058d7eb37d54a077170fff2d691b99 |
06-Aug-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add some new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| dd944a00815c38af1e7424f67bf71ffb90deceb1 |
06-Aug-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add some missing evergreen pci ids
Noticed by: Harald van Dijk <fdo@gigawatt.nl>
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=53124
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| a1d462d2a6f720538eaf1199a94dd27cd04e8a54 |
17-Jun-2012 |
Dave Airlie <airlied@redhat.com> |
radeon/surface: free version after using it.
fixes leak in valgrind.
Signed-off-by: Dave Airlie <airlied@redhat.com>
adeon_surface.c
|
| d1fcfb17b9642ae351b03056a27b328f314ca80a |
13-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: force 1D array mode for z/stencil surface
On r6xx or evergreen z/stencil surface don't support linear or
linear aligned surface, force 1D tiled mode for those.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| 2f56002cc0b5424902dfe2bd4024f7b825ecde67 |
11-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: enabled 2D tiling for evergreen only on fixed kernel
Due to a kernel bug, enabled 2D tiling for evergreen only on
newer fixed kernel.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| 325e2e52a96ede6a19e891f769c803cb9ba85e10 |
11-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: always properly initialize stencil_offset field
Reported-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| c2b77a02d4e188cfa6d1b73a721946fd9b1d3577 |
06-Jun-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: fall back to 1D tiling only with broken kernels
Certain cards report the the wrong bank setup which causes
surface init to fail in the ddx and leads to no accel.
If we hit an invalid tiling parameter, just set a default
value and disable 2D tiling.
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=43448
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
adeon_surface.c
|
| c563db07bf6a40d2415b560685ed7604830b9fb7 |
05-Jun-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add new pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| 481234f2909c0506962a2f42da862da6a9b13fd8 |
16-May-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon: Add Southern Islands PCI IDs.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
600_pci_ids.h
adeon_surface.c
|
| cf7cc62a9817a495264bbb037f0175cef9bd7a53 |
10-May-2012 |
Anisse Astier <anisse@astier.eu> |
radeon: Add new R600 PCI ids for surface manager
This is the same list of PCI ids added by Alex Deucher in xf86-video-ati commit
aacbd629b02cbee3f9e6a0ee452b4e3f21376bd3.
This is needed since the addition of the surface allocator helper in
commit c51f7f0e460dcadb9f1a56ecf1615810877c33c8 ; it needs to differentiate
pre and post-R600 GPUs.
Therefore we should maintain another PCI id list.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48138
Signed-off-by: Anisse Astier <anisse@astier.eu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
|
| c50cc24690938db53cd91ae9ff2fa0958693f80d |
14-Feb-2012 |
Alex Deucher <alexander.deucher@amd.com> |
radeon: add TN surface support
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
600_pci_ids.h
adeon_surface.c
|
| 9b3ad51ae5fd9654df8ef75de845a519015150bb |
14-Feb-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: fix pitch alignment for scanout buffer
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| 2cfac57d364d0166ed9472b086c16aea376f495a |
08-Feb-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeon_cs_setup_bo: Fix accounting if caller specified write and read domains.
Only account for the write domain in that case.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=43893 .
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
adeon_cs_space.c
|
| 356b87d8b34daf9aeadd33465141bc212ad6e3ff |
06-Feb-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: add r600_pci_ids.h to header file
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
akefile.am
|
| 10c0837780b2d4a33568c16bb92527e196d6c05e |
03-Feb-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: fix surface API for good before anyone start relying on it
The mipmap level computation was wrong, we need to know the block
width, height, depth of compressed texture to properly compute this.
Change API to provide block width, height, depth instead of nblk_x,
nblk_y, nblk_z.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
adeon_surface.h
|
| 6a720cb8660975acea1100e61a88a92a7cb3856e |
02-Feb-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon: surface fix macro -> micro tile fallback
We need to force 1D tiling only on old kernel the fallback was
broken along the way.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_surface.c
|
| c51f7f0e460dcadb9f1a56ecf1615810877c33c8 |
10-Dec-2011 |
Jerome Glisse <jglisse@redhat.com> |
radeon: add surface allocator helper v10
The surface allocator is able to build complete miptree when allocating
surface for r600/r700/evergreen/northern islands GPU family. It also
compute bo size and alignment for render buffer, depth buffer and
scanout buffer.
v2 fix r6xx/r7xx 2D tiling width align computation
v3 add tile split support and fix 1d texture alignment
v4 rework to more properly support compressed format, split surface pixel
size and surface element size in separate fields
v5 support texture array (still issue on r6xx)
v6 split surface value computation and mipmap tree building, rework eg
and newer computation
v7 add a check for tile split and 2d tiled
v8 initialize mode value before testing it in all case, reenable
2D macro tile mode on r6xx for cubemap and array. Fix cubemap
to force array size to the number of face.
v9 fix handling of stencil buffer on evergreen
v10 on evergreen depth buffer need to have enough room for a stencil
buffer just after depth one
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
akefile.am
600_pci_ids.h
adeon_surface.c
adeon_surface.h
|
| 8420743301a36dc1316fadf53bf8e1478068400a |
02-Dec-2010 |
Marek Olšák <maraeo@gmail.com> |
radeon: silence valgrind warnings by zeroing memory
adeon_bo_gem.c
adeon_cs_gem.c
|
| b8c4e5836cf1eff3e8c666f24567bd4c2fa31140 |
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
Fix radeon distcheck.
akefile.am
|
| af98ccf4dd5dcb1b904ec32b9bd1521e6bf7dda5 |
26-Apr-2010 |
Marek Olšák <maraeo@gmail.com> |
radeon: use the const qualifier in radeon_cs_write_table
Signed-off-by: Marek Olšák <maraeo@gmail.com>
adeon_cs.h
|
| 78de69713d742645c1c4347a06afca5b38f97184 |
08-Apr-2010 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: add new cs command stream dumping facilities
Dump command stream + associated bo into a binary file
which follow a similar design as json file. It allows
to intercept a command stream and replay it in a standalone
program (see radeondb tools).
akefile.am
of.c
of.h
adeon_cs_gem.c
|
| cc20ed8100834b7a5129ed403dee6c0e15d82cd1 |
29-Mar-2010 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: tab/whitespace cleanup
adeon_cs_gem.c
|
| 976e779f9cd0571dd2c218580485b39d37bd18a0 |
26-Feb-2010 |
Julien Cristau <jcristau@debian.org> |
Install headers to $(includedir)/libdrm
Avoids conflicts with kernel headers.
Signed-off-by: Julien Cristau <jcristau@debian.org>
Reviewed-by: Rémi Cardona <remi@gentoo.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
akefile.am
ibdrm_radeon.pc.in
|
| 966c9907c040b4fe4b288b4a9d82598797aee743 |
28-Aug-2009 |
Pauli Nieminen <suokkos@gmail.com> |
libdrm_radeon: Optimize cs_gem_reloc to do less looping.
bo->referenced_in_cs is checked if bo is already in cs. Adding and removing
reference in bo is done with atomic operations to allow parallel access to a
bo from multiple contexts.
cs->id generation code quarentees there is not duplicated ids which limits
number of cs->ids to 32. If there is more cs objects rest will get id 0.
V2:
- Fix configure to check for atomics operations if libdrm_radeon is only selected.
- Make atomic operations private to libdrm.
This optimization decreases cs_write_reloc share of torcs profiling from 4.3%
to 2.6%.
Tested-by: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
adeon_bo_gem.c
adeon_bo_gem.h
adeon_cs.c
adeon_cs.h
adeon_cs_gem.c
adeon_cs_int.h
|
| 4b6f70f20cbaccb18f122e87ac0d471356b01a59 |
14-Feb-2010 |
Marek Olšák <maraeo@gmail.com> |
radeon: add square-tiling flag
adeon_bo.h
|
| 1802e1a4e747b5906d3af10c4a53fd457eddcbb4 |
01-Feb-2010 |
Pauli Nieminen <suokkos@gmail.com> |
libdrm/radeon: Fix section size mismatch to reset the section.
If there is section size mismatch reusing the section object
makes section start fail.
Reseting the object before doing error checking prevents the
possible flood of errors.
adeon_cs_gem.c
|
| 520c658706aa896d64f374cc74065394111f6122 |
02-Feb-2010 |
Dave Airlie <airlied@redhat.com> |
radeon: enable by default now that kms is out of staging
ibdrm_radeon.pc.in
|
| 320811b282d7f57b364f8414e2e7b714f89b0503 |
14-Jan-2010 |
Jerome Glisse <jglisse@redhat.com> |
radeon: get device id from the kernel, use it in cs_print
This allow external tools to know for which asics a cs
is destinated to.
adeon_cs_gem.c
|
| 2612371a626337452e598a3339355bf980f5be38 |
14-Jan-2010 |
Jerome Glisse <jglisse@redhat.com> |
radeon: simpler cs print function
We don't intend libdrm-radeon to become clever enough to
decode cs for all GPU we support. Better to let an external
tool do the job. This will print raw cs in an easy to parse
way.
adeon_cs_gem.c
|
| 74937cda177363ff4ede9e2b4ea2bec04cda892e |
14-Jan-2010 |
Jerome Glisse <jglisse@redhat.com> |
radeon: indentation + trailing space cleanup
adeon_cs.c
|
| 6bf1ed2979ca56d3e8dd8938fc08e3810887ae8a |
14-Jan-2010 |
Jerome Glisse <jglisse@redhat.com> |
radeon: indentation & trailing space cleanup
adeon_bo.c
adeon_bo.h
adeon_bo_gem.c
adeon_bo_gem.h
adeon_bo_int.h
adeon_cs.h
adeon_cs_gem.h
adeon_cs_space.c
|
| b06cb754a1eee0746c40f62c51d4f0544c39c843 |
14-Jan-2010 |
Jerome Glisse <jglisse@redhat.com> |
radeon: indentation + trailing space cleanup
adeon_cs_gem.c
|
| 6de39fc73050a386a39c53e522098a0a784e7ff8 |
21-Dec-2009 |
Dave Airlie <airlied@redhat.com> |
radeon: fix BO null check, should be in higher level fn
adeon_bo.c
adeon_bo_gem.c
|
| 125994ab30d4f0f126c62fa741ec62a52d69d7a8 |
17-Dec-2009 |
Dave Airlie <airlied@redhat.com> |
radeon: straighten out the API insanity.
as Michel pointed out we are exposing too much info for these object
for this to be maintainable going forward.
This patch set minimises the exposed parts of the radeon_bo and
radeon_cs objects to the piece necessary for ddx/mesa to operate
at a decent speed.
The major problem is mesa contains a legacy BO/CS managers which we still
need to expose functionality to, and we really cannot change the API
until we can drop the non-KMS codepaths.
Signed-off-by: Dave Airlie <airlied@redhat.com>
akefile.am
adeon_bo.c
adeon_bo.h
adeon_bo_gem.c
adeon_bo_int.h
adeon_cs.c
adeon_cs.h
adeon_cs_gem.c
adeon_cs_int.h
adeon_cs_space.c
adeon_track.c
adeon_track.h
|
| b84314a86ea4ad30e0f57a71b4ef0fa138fb24c6 |
07-Dec-2009 |
Jerome Glisse <jglisse@redhat.com> |
radeon: Use drmIoctl so we restart ioctl on EINTR or EAGAIN
This is needed as change in kernel will lead to ioctl returning
EINTR if they are interrupted.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
adeon_bo_gem.c
|
| 10ce0ec18806ae32a5d615c693626a085b0dd7b8 |
20-Nov-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
Merge remote branch 'origin/master' into libdrm
|
| 4f57abfe66091281c9f59c14e6ea27b524b55d5b |
17-Nov-2009 |
Kristian Høgsberg <krh@bitplanet.net> |
Move libdrm/ up one level
akefile.am
ibdrm_radeon.pc.in
adeon_bo.h
adeon_bo_gem.c
adeon_bo_gem.h
adeon_cs.h
adeon_cs_gem.c
adeon_cs_gem.h
adeon_cs_space.c
adeon_track.c
adeon_track.h
|