| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 72c84a8294a061208d2dc76caf282d83b0f84549 |
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12-Nov-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Export intrinsics:__builtin_arm_{dmb,dsb} to frontend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| d1311ac171f9cb90cab4906a6c0e091b6b65b862 |
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01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 5df37dab763ce377095389c4ea1cff88db369954 |
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19-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARMv8] Add support for the v8 cryptography extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| a4d46d7fc6431ec3576839f11cb61862b784cb3e |
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18-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add CRC instructions.
Patch by Bradley Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 4897151df698197f0eb5c4085545312dbb20c94d |
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05-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| d3128a4a5a8531a256a224422d7da178d18459eb |
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28-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.
Clang is now generating cleaner IR, so this removes the old variants which
should be completely unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 6fec715a1a662ce3b560f85c710875cfeeb1fb98 |
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19-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 59b3300664d062bf04159eacaeb44d6c729e6a8c |
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18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add NEON instructions VCVT{A, N, P, M}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 19c14abf1c4ccebfa7d07bdd6ea8462a15c0b749 |
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17-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add support for the NEON instructions vmaxnm/vminnm.
This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 2f438131f115a3860ee344a827a091790d6dc13d |
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16-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement ldrex, strex and clrex intrinsics
Intrinsics already existed for the 64-bit variants, so these support operations
of size at most 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
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| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
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02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/IR/IntrinsicsARM.td
|