| 560a17f4e3f8019a108abb7848a4735c59a43be0 |
|
20-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM with patches for fp16
Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363,
r235530, r235609, r235610, r237004
r235191 has a required bug-fix and the rest are all related to fp16.
Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6
(cherry picked from commit a18e6af1712fd41c4a705a19ad71f6e9ac7a4e68)
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 16abd8ab144c62c7b1c821c8a083c2345d249d54 |
|
25-Oct-2014 |
Stephen Hines <srhines@google.com> |
Merge in the following upstream patches to resolve Cortex-A57 crashes.
r214957
r215233
r216455
r216721
r217682
r217689
r217690
r217735
Change-Id: Ia53b88591471325df132caf26e1087510a65ce36
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 863c7b48a6672f7074b2e69683fe4259c8c31bd7 |
|
09-Dec-2013 |
Tim Northover <tnorthover@apple.com> |
Merge rest of r196210. Some bits strayed into r196701, turning 3.4 red. This
should fix the issue.
------------------------------------------------------------------------
r196210 | haoliu | 2013-12-03 06:06:55 +0000 (Tue, 03 Dec 2013) | 3 lines
[AArch64]Add missing floating point convert, round and misc intrinsics.
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| f04a4d74b86733b853b7445ab6d5a3bde025a30d |
|
08-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196456:
------------------------------------------------------------------------
r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines
For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 9584d3222fa54f7419d008c41d49b4b44331c51c |
|
08-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196190:
------------------------------------------------------------------------
r196190 | jiangning | 2013-12-02 17:29:32 -0800 (Mon, 02 Dec 2013) | 2 lines
Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| f4b097829a14829bb0e538123326c7537f122a5f |
|
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195932:
------------------------------------------------------------------------
r195932 | d0k | 2013-11-28 11:58:56 -0800 (Thu, 28 Nov 2013) | 3 lines
Silence sign-compare warning and reduce nesting.
No functionality change.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 508d25f26bf636d5e2c78ce720c7c67bb87d43d2 |
|
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195905:
------------------------------------------------------------------------
r195905 | jiangning | 2013-11-27 17:34:55 -0800 (Wed, 27 Nov 2013) | 3 lines
Remove the variable only used by assert to avoid the build failure
caused by build options [-Werror,-Wunused-variable].
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| d85ed0caa1f780cbd13af1891d2a30fdfbad547a |
|
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195843:
------------------------------------------------------------------------
r195843 | jiangning | 2013-11-27 06:02:25 -0800 (Wed, 27 Nov 2013) | 2 lines
Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 8a0ff1f236e77214878c9d493e786b30656ad2a1 |
|
26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195716:
------------------------------------------------------------------------
r195716 | kevinqin | 2013-11-25 19:26:47 -0800 (Mon, 25 Nov 2013) | 3 lines
Refactored the implementation of AArch64 NEON instruction ZIP, UZP
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 36c7806f4eacd676932ba630246f88e0e37b1cd4 |
|
19-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 97577757c6dc84233ad10cd432664257e593e76d |
|
18-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.
The functions are like: vst1_s8_x2 ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| a08063a000cfc7499f08a472d85f14e7a5e90f8d |
|
14-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction class SIMD misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 258115258f8fe15e9d74b5fb524f90b75bb917d1 |
|
06-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 591c2f738a3e12026ff5504a486d54fc21fb3049 |
|
05-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 8263dcdf23bc534405745959c97cbfd562362458 |
|
05-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implemented aarch64 neon intrinsic vcopy_lane with float type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| c2884320feebc543d2ce51151d5418dfc18da9e4 |
|
31-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| f853a034a1fdccd194da04ca1e2e1aa8bcbd16b4 |
|
30-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar floating-point compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 160a14e2b1b3bfd2bd67cb03a7ae213fb35211cc |
|
29-Oct-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
[AArch64] Implement FrameAddr and ReturnAddr
Fixes PR17690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 2f21452ba1ee5bde8fee438b4cf1a1ce95beb6ca |
|
24-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.
When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 767f816b926376bd850a62a28d35343ad0559c91 |
|
11-Oct-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (copy).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 6a5a667517160ca1b557002a29d08868ae029451 |
|
10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 812ddcc50f8bc3ec6ce115863ff2263815906aaf |
|
10-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| d622bef31d11a5a6429fe7fad557c9b111e96f69 |
|
10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 2aeb4771a6ca0ee253e4836edbab5705203d9bb4 |
|
07-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| dd518bcc9dd9e4028b2a979ced09edd5b6becd07 |
|
04-Oct-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (3V elem).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 477fc628b3c9ce1c970d4a678dd5607b15242cc8 |
|
24-Sep-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Initial support for Neon scalar instructions.
Patch by Ana Pazos.
1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 630c5e06d633fad142af4b145ee684e90754700e |
|
13-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: use RegisterOperand for NEON registers.
Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.
The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 19fdc268c316b3b0bdcb2b558449819f4f402d6a |
|
04-Sep-2013 |
Hao Liu <Hao.Liu@arm.com> |
Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
and 4 convert instructions:
scvtf,ucvtf,fcvtzs,fcvtzu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| d9767021f83879429e930b068d1d6aef22285b33 |
|
15-Aug-2013 |
Hao Liu <Hao.Liu@arm.com> |
Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 3add0679d24a00c4a585809c6ce54486f6a458f5 |
|
13-Aug-2013 |
Michael Gottesman <mgottesman@apple.com> |
Update makeLibCall to return both the call and the chain associated with the libcall instead of just the call. This allows us to specify libcalls that return void.
LowerCallTo returns a pair with the return value of the call as the first
element and the chain associated with the return value as the second element. If
we lower a call that has a void return value, LowerCallTo returns an SDValue
with a NULL SDNode and the chain for the call. Thus makeLibCall by just
returning the first value makes it impossible for you to set up the chain so
that the call is not eliminated as dead code.
I also updated all references to makeLibCall to reflect the new return type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 87773c318fcee853fb34a80a10c4347d523bdafb |
|
01-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: add initial NEON support
Patch by Ana Pazos.
- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise
- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic
- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same
- Intial implementation of instruction class:
Scalar Arithmetic
- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.
- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 4632e31f516fc982580dfccd09af60fdcabe561d |
|
25-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: fix even more JIT failures
The last patch corrected some issues, but constant-pool entries had actual
codegen bugs in the large memory model (which MCJIT uses).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| f67c7d7e8c5949037e85dd233876989c1fea7099 |
|
15-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Make some arrays 'static const'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| e54885af9b54bfc7436a928a48d3db1ef88a2a70 |
|
09-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
|
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 4393f48c03300203594e22d248808f20dd59d886 |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction info and register info objects.
These objects are internal to the TargetMachine object and may change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
|
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| effc16bb4946e6de988933e810026aed12560855 |
|
04-May-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: assert code model is small for TLS accesses
Supporting TLS in the large memory model is rather difficult at the
moment, so make sure no-one gets into difficulties by mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| cd1b09b25b57c1fb09a50ded1d6852a5a1cb6377 |
|
04-May-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: support large code model for jump-tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| b2efdde06c00023287255d9a09861e43fb5efebd |
|
04-May-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: implement support for blockaddress in large code model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 45db92038bf540fbbd8dfe5dff520aa8566d7cef |
|
04-May-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: implement large code model access to global variables.
The MOVZ/MOVK instruction sequence may not be the most efficient (a
literal-pool load could be better) but adding that would require
reinstating the ConstantIslands pass.
For now the sequence is correct, and that's enough. Beware, as of
commit GNU ld does not appear to support the relocations needed for
this. Its primary purpose (for now) will be to support JITed code,
since in that case there is no guarantee of where your code will end
up in memory relative to external symbols it references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 8b71994fde0f0fcdf7a8260dc773fb7376b1231f |
|
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused ShouldFoldAtomicFences flag.
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 211ffd242df8bacf4cbe034f5ca7545ab75b45df |
|
08-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: remove barriers from AArch64 atomic operations.
I've managed to convince myself that AArch64's acquire/release
instructions are sufficient to guarantee C++11's required semantics,
even in the sequentially-consistent case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 69fe178f7781fa3c01d013ac7b7858926064f6ca |
|
08-Mar-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: expand sincos operations, we don't support them.
Patch based on Mans Rullgard's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 6ff20f205b2aa126b268bcada9920f56715161be |
|
28-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: be more careful resorting to inefficient addressing for weak vars.
If an otherwise weak var is actually defined in this unit, it can't be
undefined at runtime so we can use normal global variable sequences (ADRP/ADD)
to access it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 5366ab21f4595d0e3888b2d23f38469da2465b8d |
|
28-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: don't drop GlobalAddress offset when handling extern_weak decls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 279b9184c2ff4fea93b198a3519b8cb3a1d8d195 |
|
28-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: Use cbnz instead of cmp/b.ne pair for atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 9831bf06e8747206d27d480f06dedbf4a8605145 |
|
17-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
AArch64: Avoid shifts by 64, that's undefined behavior.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 1e8839302b70d77de63844332bdee9ce7d06f2c9 |
|
15-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 5464c301c4472f54f700e171750fc51d39a0f4b8 |
|
14-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: stop claiming that NEON registers are usable for now.
If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.
This fixes test failures when AArch64 is the default target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 612779eb83a98cec1e11dc823ba2e6420edbce54 |
|
11-Feb-2013 |
Joel Jones <joel_k_jones@apple.com> |
Spelling correction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 8a06229c89f848bf742e2b88423d02558b7ca638 |
|
06-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Implement external weak (ELF) symbols on AArch64
Weakly defined symbols should evaluate to 0 if they're undefined at
link-time. This is impossible to do with the usual address generation
patterns, so we should use a literal pool entry to materlialise the
address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| baa3c50a7bb0ddb0397b71b732c52b19cb700116 |
|
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to AArch64 return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| a693205ce1d5a57ae4d855d5773f5e1c89eff063 |
|
05-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Fix signed-unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174387 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| dfe076af9879eb68a7b8331f9c02eecf563d85be |
|
05-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Fix formatting in AArch64 backend.
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 19254c49a8752fe8c6fa648a6eb29f20a1f62c8b |
|
05-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove cyclic dependency in AArch64 libraries
This moves the bit twiddling and string fiddling functions required by other
parts of the backend into a separate library. Previously they resided in
AArch64Desc, which created a circular dependency between various components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|
| 72062f5744557e270a38192554c3126ea5f97434 |
|
31-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
|