| 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| c3cee57f7d20f69a84fd88464ed8cf050e63c7ad |
|
09-Sep-2013 |
Bill Wendling <isanbard@gmail.com> |
Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.
Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.
<rdar://problem/13623355>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 5510728d28bb1ee04abc32da3d21b7df12948053 |
|
01-Sep-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| f69a29b23a116a3520f185054290c445abf9aa62 |
|
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Revert "Fix the build broken by r189315." and "Move everything depending on Object/MachOFormat.h over to Support/MachO.h."
This reverts commits r189319 and r189315. r189315 broke some tests on what I
believe are big-endian platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 9c3dd1b0d1e96ef408b68da3b06c6ebd6c943601 |
|
27-Aug-2013 |
Charles Davis <cdavis5x@gmail.com> |
Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 02265382929b0275d7b7b334eab5e2fd34e1b9fe |
|
22-Jul-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:
1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 6c921a55f4d5fc51a127fcc673ac1c9b46273899 |
|
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| c139672407b6ad8d2929fd0c52591216fd32b4b6 |
|
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
- For now, The tests are marked as XFAIL for win32 hosts.
FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 6915854dd27bfedd2bc261cb19b148557670b98c |
|
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().
FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 2266ef3f5e7608d0ae491acd77b755b171cc6475 |
|
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 19d54337169ae4af2d44ae39664d0bac1ae0309c |
|
14-Jan-2013 |
Quentin Colombet <qcolombet@apple.com> |
Follow up of commit r172472.
Refactor the big if/else sequence into one string switch for ARM subtype selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 398db9368d72d1d60d40b2e18c16ca2c14aa7f39 |
|
14-Jan-2013 |
Quentin Colombet <qcolombet@apple.com> |
Complete the existing support of ARM v6m, v7m, and v7em, i.e., respectively cortex-m0, cortex-m3, and cortex-m4 on the backend side.
Adds new subtype values for the MachO format and use them when the related triple are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 251040bc18eedfa56d01fe92836e55cfd8c5d990 |
|
08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| f2a1c83c86ceefb9a241aa728d1d1239a64b894e |
|
05-Dec-2012 |
David Sehr <sehr@google.com> |
Correct ARM NOP encoding
The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which
causes the emission of a coprocessor instruction rather than "mov r0, r0"
as indicated in the comment. The test also checks for the wrong encoding.
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| cb4028b91d7c1b0163d1b6c85911668d3d19c75a |
|
24-Nov-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM: Share applyFixup between ELF and Darwin.
The implementations already diverged a bit, merge them back together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| b4316028b3978e65cc2b97042292637857dfad49 |
|
02-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
MachO: direct-to-object attribute for data-in-code markers.
The target backend can support data-in-code load commands even when
the assembler doesn't, or vice-versa. Allow targets to opt-in for
direct-to-object.
PR13973.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| eb1641d54a7eda7717304bc4d55d059208d8ebed |
|
29-Sep-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add LLVM support for Swift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 536a88ad5bf160232205192a7ce72e50bfadbded |
|
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend
store this and use it to not emit long nops when the CPU is geode which
doesnt support them.
Fixes PR11212.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 2d524b0765145f1c7888166c985a25452f16b2bc |
|
04-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 7a3afa91ad8f68428373948fc16375e99bff3c6f |
|
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Diagnostics for out of range fixups.
Replace some assert() calls w/ actual diagnostics. In a perfect world,
there'd be range checks on these values long before things ever reached
this code. For now, though, issuing a better-late-than-never diagnostic
is still a big improvement over assert().
rdar://11347287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 9da7892fbe1c9e7c592c5928e36724a0e190a777 |
|
26-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Thumb ldr(literal) base address alignment is 32-bits.
The base address for the PC-relative load is Align(PC,4), so it's the
address of the word containing the 16-bit instruction, not the address
of the instruction itself. Ugh.
rdar://11314619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| b54efe809f258af2bd1cfbde6e196f70a8a33081 |
|
12-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'adr' fixups don't need the interworking addend tweaking.
They reference the PC directly, so things work properly that way.
rdar://11231229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| bf3c322640fdaf6e4a60a59ed8cb108a7f6685ad |
|
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix encoding fixup resolution for ldrd and friends.
The 8-bit payload is not contiguous in the opcode. Move the upper nibble
over 4 bits into the correct place.
rdar://11158641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| cb0809b82b126e79b99755ae4fc3d9733faea038 |
|
30-Mar-2012 |
James Molloy <james.molloy@arm.com> |
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 4e02f23de24375294005f88b5254a3775d39fcb2 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| f1d0f7781e766df878bec4e7977fa3204374f394 |
|
26-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes and forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| fa1f74470a51a57b7b8feb4c4ba18501c3f2709a |
|
19-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM branch relaxation for unconditional t1 branches.
rdar://11059157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 7b25ecf6adbf3c4709c48033acfeb6ebbb4452ab |
|
27-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| e545ee20f1b6ea6c03919cc9bc1a4a059c2f03b6 |
|
19-Jan-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Silence warnings about mixing enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 9363c58dc2473a6470d3e7037afe8a215bee7e3e |
|
19-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 relaxation for tADR to t2ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| d26bad079d6977309699e0bc9203451904acbd86 |
|
19-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Add comment and fix range check in condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 256ba4f42a16da2b3ffc757aa7bf191890765580 |
|
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 relaxation for LDR(literal).
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.
rdar://10711829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| ec3433852dd11e8ff60c9610b4c84468e5935f2b |
|
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. MCAsmBackend naming conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 5a7efa7f134dd6f8f927c162d9f4062eaa3eb4ac |
|
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 load/store fixups don't set the thumb bit.
Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.
rdar://10348687.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 9b5b125c34b47e0e7eef2548acee8bf1448c4b71 |
|
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Move some ARM specific MCAssmebler bits into the ARMAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 69bbda03918a18bd4477bb254d51346ee3033567 |
|
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the ARM specific parts of the ELF writer to Target/ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| dc9a8a378daf432d8dcfc178507afe149706f9a6 |
|
21-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce the exposure of Triple::OSType in the ELF object writer. This will
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 2f196747f15240691bd4e622f7995edfedf90f61 |
|
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| cb86509e7a0f831e28c89f84c22a409115d01c38 |
|
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up value checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| d9a6e8978dd65c85d68bf1141d992da576878cd8 |
|
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM handling of tBcc branch relaxation.
rdar://10069056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| 370b78d795154899a22ca2b4674e890661ff1d59 |
|
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Move target-specific logic out of generic MCAssembler.
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|
| f503ef6800fcbda99d6ae581ee8cfe3204becb3c |
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06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Simple branch relaxation for Thumb2 Bcc instructions.
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| 2abba8496cb394af53b531e95067d5cae78bb9ee |
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16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| b84acd24687c721e3da46bb56a94d393bc5a8cbc |
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16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix encoding of NOP used for padding in ARM mode .align.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| 681460f954e9c13ffd2f02f27bba048ccf90abaf |
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01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD/VST assembly parsing for symbolic address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| f391e9f696183a8dfb6b0d1e791687a520552f85 |
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01-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Correct for my over-eager delete finger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| 98602ac9a99c5243a9e1abdb0e72dd326ec4958d |
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30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Fixup valus for movt/movw are for the whole value.
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| b9d3ff872908bcf648b826c1c48db2cacd813b95 |
|
25-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM asm backend initialize isThumbMode based on target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| 67b95f902a51b591b6178e370d23ffaca841275d |
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19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(literal).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| 90b5a08e1ffc4a1c18f7fa964ca561fa4b03c314 |
|
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb blx instruction fixup has same data range as bl.
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| d0d3f7e01ff7f83575816f6e1d75aa2224ebc2cb |
|
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| 78c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5c |
|
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| a7cfc08ebe737062917b442830eb5321b0f79e89 |
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23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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| be74029f44c32efc09274a16cbff588ad10dc5ea |
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23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARM mc routines into MCTargetDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
|