| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
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08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| ebe69fe11e48d322045d5949c83283927a0d790b |
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23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 8a7f9de9d42e5817167e374dd61408dcac31a102 |
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04-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Clean up code for Mips16 large frame handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 41e632d9e1a55d36cb08b0551ad82a13d9137a5e |
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07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 6c1301ba8c017e39123e41a3cb5fb6984c0b4766 |
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22-May-2013 |
Reed Kotler <rkotler@mips.com> |
Mips16 does not use register scavenger from TargetRegisterInfo. It allocates
a RegScavenger object on it's own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| e2e80cbdcfc5e69fd59715f9dcde3154cffa8169 |
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02-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[mips] Fix the head Mips16RegisterInfo.cpp comment
...aka a test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 5114226c1896f250be8881adf67d55a7e54b50fc |
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29-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define a function which returns the GPR register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 700ed80d3da5e98e05ceb90e9bfb66058581a6db |
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21-Feb-2013 |
Eli Bendersky <eliben@google.com> |
Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.
There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.
The refactoring was OK'd by Anton Korobeynikov on llvmdev.
Note: this touches the target interfaces, so out-of-tree targets may
be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 61b97b8c1721ba45e5c10ca307ceebe1efdf72a9 |
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08-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
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02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| a40ba2b3b2c909c366e5479d4e51ed35a0ada934 |
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21-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
Call llvm_unreachable instead of assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 0fd831325006d3d3f73022b4908ceacfbf7aa262 |
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20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
There is one more patch to finish large frames. Make sure we assert
on code that has large frames which will not yet compile correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 1f23239c5bdbeb45a612238acd48bb497b3cce15 |
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20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
Turn on register scavenger for Mips 16
We use an unused Mips 32 register for the emergency slot
instead of using the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
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03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 9441125d636dee246acf9cb6c8f264edda92c335 |
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31-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5 |
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28-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
This patch is for the implementation of mips16 complex pattern addr16.
Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.
The Mips16InstrInfo.td has been updated to use addr16 instead of addr.
The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| c878f3899c01db796d72bab8ac5156c124eb30ca |
|
26-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
|
| 71eab96bfd4d57a14105324cc0e0cac8eb3f7c8e |
|
23-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unused private field to silence build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 91a35f03da446009cd1de4cdabaa1cdec7e74e0c |
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23-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add a member of type Mips16InstrInfo/MipsSEInstrInfo to class
Mips16RegisterInfo/MipsSERegisterInfo.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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| 24e79e55daa5d2812d2a5ea0a282ebe48ef465e6 |
|
04-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
Change these to patterns.
2. Add another 16 instructions.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
|
| 71746220d3d1c3e8efba35038ac2ff14b4a4d3ae |
|
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits
instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
|
| 8589010e3d1d5a902992a5039cffa9d4116982c5 |
|
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
|