| 560a17f4e3f8019a108abb7848a4735c59a43be0 |
|
20-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM with patches for fp16
Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363,
r235530, r235609, r235610, r237004
r235191 has a required bug-fix and the rest are all related to fp16.
Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6
(cherry picked from commit a18e6af1712fd41c4a705a19ad71f6e9ac7a4e68)
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 714e04b84ac5c2342f468aa55953694e4cdf3834 |
|
12-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix a bug in function CC_MipsO32_FP64. The second double precision
argument was not being passed in $f14.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d4765aa047c43dc0ce2c4a6a3ccdb91b8fa73c51 |
|
12-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Revert part of r194510 that was accidentally committed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0a227ad4d5e12ca90fd937bf2b05d8bca291a1ad |
|
12-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix and re-enable a test case that has been disabled for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9e2838e29b0820afc35f6ef2d465d4aca9ed402a |
|
12-Nov-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
asm ("ldi.w %w0, 1", "=f"(result));
Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.
MSA registers (including control registers) are supported in clobber lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 95830221bd4877816adc6707eb34ca68c5a515d2 |
|
09-Nov-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5956bed6992577d2899b81498b1703e07efc2057 |
|
28-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify LowerFormalArguments using getRegClassFor.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| adb1297d49dd345821d7aa91057a0b22e6209a16 |
|
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename isel nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 89fee2ff928254f21cc9be358e1d8d4498fa0aee |
|
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Transfer kill flag to the newly created operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192662 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 25dafa388a1b8052e4817c5d6378b3408b80744e |
|
10-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not generate INS/EXT nodes if target does not have support for
ins/ext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 116189a997a71d0e63db64ef4c6c3906078d94cf |
|
07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Coding style clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 243702b95a471ffb7d2374dfad3d7f8b11bee7e7 |
|
07-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6ff59a16a05d43fdda587ce600b5b42a63cf3d33 |
|
28-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.
Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:
1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25 // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25 // jump to lazy-binding stub again.
With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:
1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25 // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25 // directly jump to func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 200a7434f6abc1e469fdf1ee547bc3fe4fbfcc02 |
|
27-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e36a62c23d332658e4513d67eedb392b9c27f470 |
|
25-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r191350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 793803449870a661c1a09e400df9b04492772196 |
|
25-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define getTargetNode as a template function.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3706eda52c4565016959902a3f5aaf7271516286 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f515964d36834ec918fe831029bc72ccdcec34d3 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 93d995719e2459a6e9ccdb2c93a8ede8fa88c899 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7e0df9aa2966d0462e34511524a4958e226b74ee |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp
This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).
There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.
compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 89d13c1b380218d381be035eb5e4d83dcbc391cc |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ae1fb8fc19dcfd2f0e33a36f40d687b08dcc9a6b |
|
24-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics)
MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9a1aaeb012e593fba977015c5d8b6b1aa41a908c |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
operation and implemented the DAG combines necessary to fold sign/zero
extends into the extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 915432ca1306d10453c9eb523cbc4b257642f62a |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| da521cc1cc733ee1c27b00e4c0e365c8b702e2e0 |
|
23-Sep-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).
Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ae43dac30037395cce2b54af0a02500985813183 |
|
11-Sep-2013 |
Eli Friedman <eli.friedman@gmail.com> |
Fix unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c673f9c6fecb0f828845ada7ea5458f66f896283 |
|
30-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a problem with dual mips16/mips32 mode. When the underlying processor
has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3c380d5e28f86984b147fcd424736c498773f37e |
|
28-Aug-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.
Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ad341d48f0fc131d1c31a0c824736e70c34e0476 |
|
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.
Test case will be added when support for mfhc1 and mthc1 is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a98a486ad194c38293efcc5359d6ed2493f950dc |
|
20-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cbaf6d0cc3d3f363f269346817a90d3cbc8d1084 |
|
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename HIRegs and LORegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bfb07b1054b653661306848e695b34e79289a15b |
|
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Properly parse registers that appear in inline-asm constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1858786285139b87961d9ca08de91dcd59364afb |
|
07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9758562aa706a5a20a9d833074e733ed544db776 |
|
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Implement llvm.trap intrinsic.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 407883b69b3bc10ebf053f5922d877b2e786d124 |
|
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 83d8ef133b121b7e752e7468cb1e0e5e3b636aee |
|
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP branch instructions to have explicit FP condition code register
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a0ec3f9b7b826b9b40b80199923b664bad808cce |
|
14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f349a6e9e6ee0b589c403e0c5785266da121d05c |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c93822901aef17aaf8bb1303f27b47025fd1d582 |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 62204220e1dc2dc21256adf765728ae257b33eac |
|
04-Jul-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5112243aec9486a669d44b72e6648e8a920c9931 |
|
01-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
|
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| affed7e11d9107285b1a9ffa2cf78a141fa27a3d |
|
31-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Big-endian code generation for atomic instructions.
Patch by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 |
|
30-May-2013 |
Andrew Trick <atrick@apple.com> |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2591b5c6c3e07e40d3e39f614aba4a927c43bd9f |
|
21-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename option to make it compatible with gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f894199a14fff1399f6ee9d78c6a601d86649155 |
|
20-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ae7e7cb3d3ec657b7e6dd94cf036cdc65c182f59 |
|
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
Previously, three instructions were needed:
trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)
Now we need only two:
trunc.w.s $f0, $f2
swc1 $f0, 0($2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 63451435402d9c401475596b6e741b5bbaad0bbd |
|
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Factor out unaligned store lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f4037688242aad3109fdfd42b50df56b4a613c02 |
|
16-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete unused enum value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 46090914b783b632618268f2a5c99aab83732688 |
|
11-May-2013 |
Reed Kotler <rkotler@mips.com> |
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c147c1b994e1187cb471cdb7ee05f5f875eff4e0 |
|
01-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix handling of instructions which copy to/from accumulator registers.
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cd6c57917db22a3913a2cdbadfa79fed3547bdec |
|
01-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Instruction selection patterns for DSP-ASE vector select and compare
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 13ec4812fc733c37bb3329982bc044d186e0bea2 |
|
30-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify code.
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6265d5c91a18b2fb6499eb581c488315880c044d |
|
20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 97a62bf2a4a2d141aad8af3531c3b69934f134c1 |
|
20-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Instruction selection patterns for DSP-ASE vector shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2fbe90cf93fcb153ac1d651c764785c9b09887f6 |
|
18-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4e0980af2e9eda80cbd82895167e650d83ffe087 |
|
13-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and
lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fee62c167b1f731998ff4d315830154d17ec6f85 |
|
11-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.
- Rename function.
- Pass iterator by value.
- Remove header include.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2c2c33a167c82db9abd9b6173c1cdfdaa40c2071 |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d593a77b4cf3b81cd657e351e47cad25ee037ce1 |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.
We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f5926fd844a84adcf1ae4f193146f2877997b82c |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.
Mips16's instructions are unaffected by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9cf0724cc3a570fe64146fda7518cef5c740e988 |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2459afe69791ea04f2a060a2acc7104242844ace |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dd958925b0064981f4894ab5b8f37b02faa0c759 |
|
30-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5ac065a79767cc112eba63136183b7103765d0d3 |
|
13-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for
mips16 and MipsSETargetLowering is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f635ef401786c84df32090251a8cf45981ecca33 |
|
12-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename function and variable names to start with proper case. Fix typos.
Delete commented-out code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3ef5383b3537a420c5e2ab3e657c378e5185549d |
|
08-Mar-2013 |
Tom Stellard <thomas.stellard@amd.com> |
DAGCombiner: Use correct value type for checking legality of BR_CC v3
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.
v2:
- Expand more BR_CC value types for NVPTX
v3:
- Expand correct BR_CC value types for Hexagon, Mips, and XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b7656a9cc4bf36752df38e7c02b910c9390b9c39 |
|
06-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Custom-legalize BR_JT.
In N64-static, GOT address is needed to compute the branch address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1e3e869899468de2210f9777905340d907c814c6 |
|
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets
returned in registers $2 and $4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7433b2e1142a46c1dbb491d91e0175cb9ce83167 |
|
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly
handle fp128 returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cb2eafdfa358ae8a1e1f9ae39d8c72cd4d446da1 |
|
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating
point registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5fdee6d2b5a72a826bf6db47c319ddac08cd9f57 |
|
05-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Correct handling of fp128 (long double) formals and read long double
parameters from floating point registers if target is mips64 hard float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0b9675d631a33ecde9e11febea48a2c6551bfeec |
|
04-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips specific inline assembler constraint 'R'
'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b3ea880a706cde45818e1a0f5b162358ac8bb5bd |
|
04-Mar-2013 |
Jia Liu <proljc@gmail.com> |
Mips ISD typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| de89ecd011c453108c7641f44360f3a93af90206 |
|
25-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 29cb2591f9f7ec948e7b0e719b1db6cef99010d0 |
|
25-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make psuedo FEXT_T8I816_ins into a custom emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176002 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 459d35cb7975804048684261f2358eedbd2209c1 |
|
24-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Make psuedo FEXT_T8I816_ins a custom inserter. It should be expanded
as early as possible; which means during instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 50354a3f4a5c9e3689d502a935430f2a57a44af2 |
|
23-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand pseudos/macros for Selt. This is the last of the complex
macros.The rest is some small misc. stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 606893294095e214f50937e8f8e9770efaab07a7 |
|
22-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Emit call16 operator instead of got_disp. The former allows lazy binding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 00ddc5a7274fb4131f1a724bc350fd756156a80f |
|
22-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refers
to the immediate operand of sli or cmp function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7617d032ae12ba96ad65f37d91274e6f8c14e690 |
|
22-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand mips16 SelT form pseudso/macros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ffbe432595c78ba28c8a9d200bf92996eed5e5d9 |
|
21-Feb-2013 |
Reed Kotler <rkotler@mips.com> |
Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3450f800aa65c91f0496816ba6061a422a74c1fe |
|
20-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ffd28a44f04ab2de5a7092fbd5ff17af79f56e28 |
|
15-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up class MipsCCInfo.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| baabdecbb9bf5b32fa81b1e2830ab13076d549f1 |
|
05-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not use function CC_MipsN_VarArg unless the function being analyzed
is a vararg function.
The original code was examining flag OutputArg::IsFixed to determine whether
CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this
flag is often set to false when the function being analyzed is a non-variadic
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d07359667118ab1e889c3b9163b5e6a12414c38b |
|
05-Feb-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move MRI liveouts to Mips return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 544cc21cf4807116251a699d8b1d3d4bace21597 |
|
30-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Lower EH_RETURN.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 52dd806ed9c656c1b4fd073c8e086b563104f601 |
|
28-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove addToNoHelperNeeded function that was left unused after r173649. Fixes a -Wunused warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bc49cf73079c1223fba5046047517fc3c00d5284 |
|
28-Jan-2013 |
Reed Kotler <rkotler@mips.com> |
Make some code a little simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d07c64dce67595e9b27e039c558800b7499df7c7 |
|
26-Jan-2013 |
Reed Kotler <rkotler@mips.com> |
fix use of std::std. it's ordered set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b3105b9a9bb318672364b3d63e07b6325c3be3d7 |
|
24-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsISelLowering.cpp: Fill unreachable paths to fix warnings. [-Wsometimes-uninitialized]
FIXME: Could they, unreachable(s), be removed?
FIXME: I could prefer the coding standards...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 00cdf602ae73e039c5d5244bae4bffb5e6455096 |
|
24-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsISelLowering.cpp: Fix a warning, take two. [-Wunused-variable]
...and fix a typo, s/#ifdef/#ifndef/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d5a336cdb5ed691b0288c8d4aa4c5b1899b7e39b |
|
24-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
MipsISelLowering.cpp: Fix a warning. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8453b3f66a3c3200ea828491ef5cf162db9ccfb2 |
|
24-Jan-2013 |
Reed Kotler <rkotler@mips.com> |
The next phase of Mips16 hard float implementation.
Allow Mips16 routines to call Mips32 routines that have abi requirements
that either arguments or return values are passed in floating point
registers. This handles only the pic case. We have not done non pic
for Mips16 yet in any form.
The libm functions are Mips32, so with this addition we have a complete
Mips16 hard float implementation.
We still are not able to complete mix Mip16 and Mips32 with hard float.
That will be the next phase which will have several steps. For Mips32
to freely call Mips16 some stub functions must be created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bf6a77b98715012c0fa3bdbb3ba55fa7c24c1548 |
|
22-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Clean up code in MipsTargetLowering::LowerCall. No functional change
intended
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e13f441e002b95bb64d883d173f6aff9615556fd |
|
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] MipsTargetLowering::getSetCCResultType should return a vector type if
vectors are being compared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bacbf1c2cb58af7d839027768a7a67e117a6cc5f |
|
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
set register class properly for mips16 here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c28ee9622a4348c9d7a18d34fecc029f5817a5e2 |
|
20-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
This assert is overly restrictive and does not work for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ed23fa8e55f5a58741c20c601410c2822d00f066 |
|
15-Dec-2012 |
Reed Kotler <rkotler@mips.com> |
This code implements most of mips16 hardfloat as it is done by gcc.
In this case, essentially it is soft float with different library routines.
The next step will be to make this fully interoperational with mips32 floating
point and that requires creating stubs for functions with signatures that
contain floating point types.
I have a more sophisticated design for mips16 hardfloat which I hope to
implement at a later time that directly does floating point without the need
for function calls.
The mips16 encoding has no floating point instructions so one needs to
switch to mips32 mode to execute floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a61b17c18a67f1b3faef2f2108379c4337ce9bb7 |
|
13-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ed185daba7432e9df717f0199336889784b10da3 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not copy GOT address to register $gp if the function being called has
internal linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 946a3a9f22c967d5432eaab5fa464b91343477cd |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?
This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7d34267df63e23be1957f738de783c145febb7af |
|
12-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 34525f9ac098c1c6bc9002886d6da3039a284fd2 |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8163ca76f0b0d336c5436364ffb3b85be1162e7a |
|
11-Dec-2012 |
Patrik Hagglund <patrik.h.hagglund@ericsson.com> |
Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.
This is the first, in a series of patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
|
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f3c0c77bc34706cc3c2bbc5e4aaae984f52d01a7 |
|
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete nodes and instructions for dynamic alloca that are no longer in
use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f09a03776dbbc882c9b15eeccb8ec847058fbfa0 |
|
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Generate big GOT code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d43e06de594e734513eb4e24193eb2dd5288c0c4 |
|
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper
functions added in r168456.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6b28b80791c742f4c561eeeae399338a8903dd6d |
|
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add helper functions that create nodes for computing address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 81784cb374d7e3cbcd86f19315052d30cb7c49f9 |
|
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add command line option "-mxgot".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 59be760f61d54e24bae70c4465021a6f0746d278 |
|
21-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] When a node which loads from a GOT is created, pass a MachinePointerInfo
referring to a GOT entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 94e472832f30320d273f5630044c6bbd626e9949 |
|
17-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Initial implementation of MipsTargetLowering::isLegalAddressingMode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e90a3bcae1cd936aa760cffe5607266279b210d1 |
|
07-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7085221a593ac5cb2478a4f81e0f7212616a9afb |
|
07-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete MipsFunctionInfo::NextStackOffset. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 294166d541fd634fea09fb1fe48457536ef43ed0 |
|
02-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the size
of the incoming argument area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2f34d754d00fbe2e4a98762d71d0fae5f4b0cf45 |
|
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Allow tail-call optimization for vararg functions and functions which
use the caller's stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b33b34a7dc447cf52702b8892c9829344e81f73a |
|
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add code for saving formal argument information to MipsFunctionInfo. This
information will be used by IsEligibleForTailCallOptimization to determine
whether a call can be tail-call optimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7d71209912bb55856f34df7013382e6dd310983b |
|
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of function MipsTargetLowering::passArgOnStack which emits nodes
for passing a function call argument on a stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e7b406d7ac150189522f0a139f1a2f76bde2cb26 |
|
30-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not do tail-call optimization if target is mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8834a20d5dcb905d454321bb0668f1e086563212 |
|
29-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Expand all atomic ops for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 21a9a98b77c48fb5084d3ef470083704d13c3929 |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not tail-call optimize vararg functions or functions with byval
arguments.
This is rather conservative and should be fixed later to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4618e0b574bf879d062a39b5867d9c314a4639e0 |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the
previous iteration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fe30a9be40a6bc22ccfab96915f4a71966f53023 |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Use the methods and classes that were added to simplify LowerCall and
LowerFormalArguments in MipsTargetLowering.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f084847373210540f345698295af333834493322 |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers
of vararg functions back to the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| db40edeb11f4f97c8de5428a84346834deaa2a47 |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add method MipsTargetLowering::passByValArg.
This method emits nodes for passing byval arguments in registers and stack.
This has the same functionality as existing functions PassByValArg64 and
WriteByValArg which will be deleted later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| eb98ae46bca786f033f8f4ab5f89ac046bd9f28e |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add method MipsTargetLowering::copyByValRegs.
This method copies byval arguments passed in registers onto the stack and has
the same functionality as existing functions CopyMips64ByValRegs and
ReadByValArg which will be deleted later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7887c90a7b80b994a51a2a3b88eef3643473e67c |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add class MipsCC which provides methods used to analyze formal and call
arguments and inquire about calling convention information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3649255e14e369aa70bf1122cd5b0e1a92431662 |
|
27-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Delete MipsFunctionInfo::InArgFIRange.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2ef5bd3ba685704bc9c0d03654cb0b7fd1b071e6 |
|
24-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure sret argument is returned in register V0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 30580cea43ac9108627e0616df6a30518ee7c0ef |
|
20-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use 64-bit registers to return an sret pointer if target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2b861be96ef18174c201ce6a94c5130445bc5b40 |
|
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add code to do tail call optimization.
Currently, it is enabled only if option "enable-mips-tail-calls" is given and
all of the callee's arguments are passed in registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e06ce4c2c48351d6d74ac2f81e72e17e5ec9fdc7 |
|
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete MipsFunctionInfo::MaxCallFrameSize which is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 58d1e3f72a61b5f8ace620c9e16baaecbb3f53f1 |
|
19-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add node and enum for mips tail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 97d9f081a92c18bb4fd1c069dccde7c99301150a |
|
10-Oct-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsTargetLowering::CanLowerReturn.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dfb8dbb4fd97140aa9bf6b9dadbca25665144c09 |
|
05-Oct-2012 |
Reed Kotler <rkotler@mips.com> |
Patch for integer multiply, signed/unsigned, long/long long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 01f7089bca51744226306e09db4954e3df02b3be |
|
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2df483efb3a3d99dd82eb88e13490ae464bf0e43 |
|
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: all the remaining instructions which read or write accumulators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fd89e6ffdab95ae6b4568b8a4153064952f61ea6 |
|
27-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS DSP: add support for extract-word instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b430cecc0eeaa3f916b396b9f5fdee04cf306658 |
|
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add MIPS DSP register classes. Set actions of DSP vector operations and override
TargetLowering's callback functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6fad5e742d0213bdd68daa7d376387bcec80b5fd |
|
22-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
SelectionDAG node enums for MIPS DSP nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f934d159ae6b57f05d8163265b9deaa29315d2e7 |
|
15-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Handled unaligned load/stores properly in Mips16
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| afc945b614a2bf99014d5820c8849451030ea82b |
|
13-Sep-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Misc.
1. Remove RA from list of allocatable registers
2. Enable d,y,r constraint inline assembly instructions
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6c7ccaa3fd1d6e96d0bf922554b09d2b17c3b0e3 |
|
12-Sep-2012 |
Michael Liao <michael.liao@intel.com> |
Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 59324297650c12a8dccf1a7ad650a9e895fdc17e |
|
06-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Stop casting away const qualifier needlessly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e7338cd550a4ccde6796d2987b482ea9f0e239ef |
|
22-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.
This bug was originally reported by Carl Norum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1d165f1c252d1541b4788bf81092a9299cc764e5 |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e2d529ac1111f153628a9c5c654f4a514e841b47 |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
When store nodes or memcpy nodes are created to copy the function call
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 36bcc11236af961ff94820bf9817ecb4f98ace7e |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 480eeb54315e35b9d18213c2d56d2166e154b62d |
|
27-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Pass the correct call frame size to callseq_start node. This is needed to
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e11246c64eb8ea3da0060be4ddb9596c8cc04439 |
|
26-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix call setup for PIC.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160774 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3ee306cbc0a295409c464ffaad5ef694de8eb09a |
|
24-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add basic ability to setup call frame, and make procedure calls.
Hello world will compile and execute with this patch.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fef904d0e824a2c587f8c1063b6c4fbf47fec898 |
|
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b7dd9fc678ab4b4c57d333cd9940b0e0d7952ea6 |
|
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
Test case will be added later when long branch patch is checked in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3fef29d88100881e7a52e570c30052e0d44c62ee |
|
11-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ba584fe8feb840a82ad5966cb9eca6df0eeaafc2 |
|
11-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Lower RETURNADDR node in Mips backend.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2 |
|
10-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make register Mips::RA allocatable if not in mips16 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 10de025a67aa37112d5d4cd703925a7c1996422a |
|
03-Jul-2012 |
Jack Carter <jcarter@mips.com> |
mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 80c1b38eff2fb3200cdddb1ef6641d64de8496a8 |
|
03-Jul-2012 |
Eric Christopher <echristo@apple.com> |
Revert " mips32 long long register inline asm constraint support." as
it appears to be breaking the bots.
This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1b055ce320fa13f6f1ac81670d11b45e01f79876 |
|
03-Jul-2012 |
Jack Carter <jcarter@mips.com> |
mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 864f66085cd9543070ef01b9f7371c110ecd7898 |
|
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix coding style violations. Remove white spaces and tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8782707f5074ab3951eb6424394bc8d2a2fa584a |
|
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
pattern:
(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
"tjt" is a TargetJumpTable node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e193b325837bee5f9a848a16077a6e156fe88fba |
|
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158414 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2bd7e532b49cb461f7e16acb01124b56aa169844 |
|
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 777a1202852ae3b9466c815b7e2463da3ba2f669 |
|
13-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement fastcc calling convention for MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 94ccee2222fa841d7ca3b13305934a570d90767f |
|
04-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is
inserted after the shift-left-logical node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 70a07c7fc437045a2421d279a99b19981f08acc2 |
|
04-Jun-2012 |
Hans Wennborg <hans@hanshq.net> |
MIPS TLS: use the model selected by TargetMachine::getTLSModel().
This was mostly done already in r156162, but I missed one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 00edc3dea28c158c5e2b6d4fd3d2da13ee933e2a |
|
02-Jun-2012 |
Chris Lattner <sabre@nondot.org> |
remove an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7664f05326f8426b6f9b978fd1f79aca91135703 |
|
02-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Set operation actions for load/store nodes in the Mips backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1cd0ec007a4bdce4acf2ba99fe9231fd0859ea80 |
|
02-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which
custom-lower unaligned load and store nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b6f1dc2f09a3d633c43f3160625e3e57319443a2 |
|
02-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Define Mips specific unaligned load/store nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f66b7b1ff667bbcf9d71f540488b49b38bf72b1d |
|
02-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand unaligned i16 loads/stores for the Mips backend.
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 28ee4fdf20dd4f938036a7de1ca134ff6ebd9da5 |
|
31-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Cleanup and factoring of mips16 tablegen classes. Make register classes
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
|
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 92d4aec5737cf81f08059bbc5c18f39d8c16c429 |
|
12-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make the following changes in MipsISelLowering.cpp:
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
before the call node. This will ensure $gp is valid at the entry of the
called function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a284acb8a79468f378452826b2426b4bcdc27e94 |
|
09-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand 64-bit shifts if target ABI is O32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| af97f73ca03d16ffa069af65a494d0933665ce11 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'x' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4adbefebd2eeeab4d7007b697b4cc20e40ba06b8 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'l' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1d5a392e2cff41488e47e038231fb114ea0eb941 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'c' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 54412a789a35386e11612739dd3b30ab382e5127 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'P' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1ce2034e43b94abb9930fd86430c46c0bf309ed7 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'O' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 60cfc7908ef6acdfab0ea4af5b2c50087a8f36d8 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'N' inline asm constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5ac47bba83ac1a1b79addc8d5e36e8a468324153 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'L' inline asm constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f49f846eec471ca64a72c151dbaa62a9306d4e37 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the inline asm constraint 'K'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e5076d484b2f530e2e2422fb06c268970b53b055 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Support the 'J' constraint.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 50ab03954ec0a43708ad0a5cf3d253ce41a30db3 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Add support for the 'I' inline asm constraint. Also add tests
from the previous 2 patches.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0ed1f764f4e0d4cc940052e8ccca260bf5c39407 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3ccbd47ecb83ad758ff310dea8c4f54d53f39326 |
|
07-May-2012 |
Eric Christopher <echristo@apple.com> |
When using inline asm constraints representing
non-floating point general registers allow 8 and 16-bit
elements.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fd5abd546e8e035755005a654d60d6f5f74cfe2c |
|
04-May-2012 |
Hans Wennborg <hans@hanshq.net> |
Make ARM and Mips use TargetMachine::getTLSModel()
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8959393533bfbdcbbfe3c5f336729394896100ce |
|
21-Apr-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC.
Thanks to Andy Gibbs, to report the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155287 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 420761a0f193e87d08ee1c51b26bba23ab4bac7f |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1cc6333161be8bbeb516bc7c74d4400dca58b997 |
|
12-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
otherwise expand FNEG during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c12a6e6b53bb6df62a0020bda91206fd149c430a |
|
12-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
Invalid operation is signaled if the operand of these instructions is NaN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154545 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 056c51e59820c4c36d3b9d2f22acb6fd121b798e |
|
12-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix bugs in lowering of FCOPYSIGN nodes.
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.
Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 56ce6b35209723cc453a6258a44f442d63be2b64 |
|
05-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Reapply 154038 without the failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 657a4e774ca27ec3b74100b893bdc08654bc916a |
|
04-Apr-2012 |
Owen Anderson <resistor@mac.com> |
Revert r154038. It was causing make check failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e825fb38887cb236a7247c48b7ff0de423b5d645 |
|
04-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix LowerGlobalAddress to produce instructions with the correct relocation
types for N32 ABI. Add new test case and update existing ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c75ceb7809954891226fcdcf80256a101a08b723 |
|
04-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix LowerJumpTable to produce instructions with the correct relocation
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 86a27330553cc51f72917aa256bc6cf14c210432 |
|
04-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix LowerConstantPool to produce instructions with the correct relocation
types for N32 ABI and update test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 03d830e4f9d8e50e3d9260587cdb652c48996068 |
|
04-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix LowerBlockAddress to produce instructions with the correct relocation
types for N32 ABI and update test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 21ecc2f4edbbc2c4ec1c2e2c87dc5a5ee6f58a68 |
|
29-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand FREM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b4549e1c0ecec1b9ea6b0e5ffe01c84c9842d668 |
|
27-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Pass the llvm IR pointer value and offset to the constructor of
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value.
The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 13daee30824d02b4657a2a97129eebfe3f9b9107 |
|
27-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix bug in LowerConstantPool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153498 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c5eaae4e9bc75b203b3a9922b480729bc4f340e2 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d229b7b8f4495a0471f3d2812050bfaa3a209e39 |
|
10-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set
operation action of nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0a40c2353c7e95bce6aee9bc557b90d5e0789765 |
|
10-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ee8c3b03fb96d37315544149a295c29b0d4de8c8 |
|
08-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Invoke setTargetDAGCombine for SELECT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e2bdf7fc935008dda6fba3d6fdd0a12193fd7b18 |
|
08-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Swap the operands of a select node if the false (the second) operand is 0.
For example, this pattern
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)
This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5fdf50065d1b481aed3222477f61f1075459210d |
|
08-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Set minimum function alignment to 3 if target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b2930b92d3e9734ced6679844666799648ebbd7a |
|
01-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Changes for migrating to using register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dfa27aea12ae1d69a7e94ed5e6df6be1cc90d9e3 |
|
01-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix bugs which were introduced when support for base+index floating point loads
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
|
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bb481f882093fb738d2bb15610c79364bada5496 |
|
28-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 44b6c715ac87505f98066fa3bf6e3e99a26b886a |
|
28-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for floating point base register + offset register addressing mode
load and store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 648f00c2f0eb29c0ae2a333fa0bfa55970059f08 |
|
24-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add an option to use a virtual register as the global base register instead of
reserving a physical register ($gp or $28) for that purpose.
This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.
example:
.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 44d23825d61d530b8d562329ec8fc2d4f843bb8d |
|
22-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c5707112e7635d1dd2f2cc9c4f42e79a51302cca |
|
17-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 38bdc5762f58b64d652864d154bf1b4dffb5ed39 |
|
17-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not promote i32 arguments to i64. This was causing unnecessary sign extension
instructions to be emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8f5e8c1cd69fa77bea20140a7132ee2dea166c6d |
|
17-Feb-2012 |
Jia Liu <proljc@gmail.com> |
add Emacs tag and fix some comment error in file headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6c2cf8b1fbcf70fd9db6fe44032c1ceaa2299760 |
|
03-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3f5b107a4b48e469899267238dcb7e204963ce0e |
|
02-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Set the correct stack pointer register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 590baca06c1e87a18070d606b36e0985e9b61afc |
|
02-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and
selector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 25dae8f4a30634c1f9cd483b13995ecf44fecec6 |
|
25-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
which is what N32/64 does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 08067b26f7fd0e8e3c4141c5a48da32af616a760 |
|
24-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Pass CCState by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b0e7af779732c5ff3c054c837a4b04ad6089d0ac |
|
04-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Enable -soft-float for MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cb9dd72fdc9adc6daed870429cb412bcdb39a6d3 |
|
04-Jan-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Have getRegForInlineAsmConstraint return the correct register class when target
is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c79507a4dd0c64e3d96fee6c57d0b2e3d14f4b77 |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
case for DCLO and DCLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7f162743fc7d68b19a6e21bba2a0aa810fc7897f |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand 64-bit CTPOP and CTTZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9aed504c8287ca864de375c58a0de67d6fa2e5e9 |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Expand 64-bit atomic load and store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c0ea04389c9fc0b73d0cbd90ec3a5bc076d25d7b |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definition of DSBH (Double Swap Bytes within Halfwords) and
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e1bcd6b5c67968910d0262cd9bebd39db6887357 |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit uint-fp conversion nodes are expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9388383b345abf7ebc192f62b016f6511777a63b |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Enable custom lowering DYNAMIC_STACKALLOC nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 056a1bc40f8775ee2d9ad3b143bc0d0985b818ba |
|
21-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Set the correct stack pointer register that should be saved or restored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 82099683060abb1f74453d06e78a3729a75ef7ee |
|
19-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Tidy up. Simplify logic. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3faac0a78c7a70d3dcd2af102a132bb9da2d639c |
|
14-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
emission is not supported yet, but a patch that adds the support should follow
soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 63974b2144c87c962effdc0508c27643c8ad98b6 |
|
13-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bfcb83fa328422d59945cbf3d72c0721e3f2f385 |
|
12-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5eccf674928a050be09d60d1b5d2a843eff5f2ed |
|
11-Dec-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Mips: Don't create a dangling IR function just to get the address of a symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6df7e23f0c9e9e4aa5560f3b0ecb2bb7d53f7d81 |
|
09-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Rename WrapperPIC. It is now used for both pic and static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0dca9456c55787cd5a5f11b388aa76586b4fcdf6 |
|
09-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
jalr should use t9 ($25) for indirect calls regardless of the relocation model
specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7a7194b5294661809ab37270c8ee5e94f8cdee18 |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ca0747917d3daa85287fd7ea6f91349b8d5a5b29 |
|
08-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement 64-bit support for thread local storage handling.
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7398bf01c2f88253a342737cc82d3a367611f117 |
|
07-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Modify LowerFCOPYSIGN to handle Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e3d3572e282733bd7aa5ac14115ed0804174e426 |
|
07-Dec-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add a few moreLocal/Global R_MIPS_GOT related fixups and
make the addend fixup code a bit more generic
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d6bc5237d8c961949fbc57dfa1a07f5833262388 |
|
05-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of 64-bit extract and insert instrucions and make
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2bf08ec854de4f393914057287d57ea2fd5d456d |
|
05-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
O32 with relocation-model=pic too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 620db8947a10ad1b7d2e2a814aba3633621ce575 |
|
16-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Lower 64-bit constant pool node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9b944a8da25a954fff1b108ea6aa9b2b03621d0e |
|
16-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Lower 64-bit block address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 160408546cce8243ea5d8e2e447eeafcf94539af |
|
15-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Simplify function PassByValArg64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6296ee3ee25a41f4d36d4fd61181598cd165235a |
|
14-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Unbreak Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4961709688be9e21985e413e296e84e391ae92ac |
|
14-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
AnalyzeCallOperands function for N32/64.
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bad53f41c298d251de98e3c864b08f6b9125345c |
|
14-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 47a4ab84fe2535e6d8d77456c08eb52de20caaee |
|
14-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Remove variable that keeps the size of area used to save byval or variable
argument registers on the callee's stack frame, along with functions that set
and get it.
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7386612a1635090acf010aaa4c7f68b181fcfe65 |
|
12-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6df3e7b1620372cf89b31eb5ff007fc4d1e721cf |
|
12-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement Mips64's handling of byval arguments in LowerCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3a5257de21216125bddaa0e5f87c00d32e054cd0 |
|
12-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Implement Mips64's handling of byval arguments in LowerFormalArguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2c5d65202e690bd46f69aa142342c0d61b7ac42a |
|
12-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Function for handling byval arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 47b92f3d8362518596d57269dc53d985bc13323a |
|
11-Nov-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Mips MC object code emission improvements:
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e184fec550ea249d00e058cfba34ec6913951895 |
|
11-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 59068067cb37322c50463102bbd6929df34c039e |
|
11-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
64-bit atomic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 46ac4399b13d46baa9e6280d540c468d8feba8ad |
|
11-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c742e4fc9016b4987dbd06af4670d7759392d08d |
|
11-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d752e0f7e64585839cb3a458ef52456eaebbea3c |
|
08-Nov-2011 |
Pete Cooper <peter_cooper@apple.com> |
Added invariant field to the DAG.getLoad method and changed all calls.
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| feaa4c316f125144b6978073885fbd25c8b369aa |
|
28-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Make changes necessary in LowerFormalArguments to support Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e42f33bd159413e48d75c4c4783e52224c0b5532 |
|
28-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Make changes necessary in LowerCall to support Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2ec69faf2615ccdffffacff9033b2228c589971c |
|
28-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add variable IsO32 to MipsTargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0851a29b6d592f6510b5ff17e7607bb3f492fca1 |
|
18-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix misc warnings. Patch by Joe Abbey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8ae330ac90a46a1c40086ea0f1a99acb4ff96e2d |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of conditional moves with 64-bit operands. Comment out code for
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a5903acd6bc15c6aa511068f8b79c79014c1b5d4 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Modify lowering of GlobalAddress so that correct code is emitted when target is
Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7bd19bd519311dacc8c00ac21f873d2cf900285e |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
zextloadi32 for which there is no corresponding pseudo or real instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dda4a07cd818fdfe2b49412e32e0e12d9e566e31 |
|
03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for 64-bit divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c7bafe9241c0742e71f7fd1b83e0c5b3acee0dac |
|
30-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of Mips64 rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f40de9d287cb57dd0449c46f91fa10c8784427da |
|
26-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Set register class of a register according to value of HasMips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8b4198da9d5884f9e33c54a9537b9a8eed4deff7 |
|
26-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Define variable HasMips64 in MipsTargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 09dd60feef61bc59a71585e05580c142a15bbcf0 |
|
26-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
In single float mode, double precision FP arguments are passed in integer
registers, so there is no need to check here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140568 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 95934844e3614adf949b09085be21f41ea4218ce |
|
24-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Preparation for adding simple Mips64 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 792016bc2202d34d0a3d0b5d12985eca5528c24c |
|
23-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Make FGR64RegisterClass available if target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 373e3a4091c85d62eb2ee10dd106ddb4d28be566 |
|
23-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Do not rely on the enum values of argument registers A0-A3 being consecutive.
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c56f5ea4c36aff16bd87c67e95f8a9be7424b286 |
|
22-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Remove unnecessary condition check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 56633441271106376b39a47bbe5b59f85144b64d |
|
21-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change the names of functions isMips* to hasMips*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| da7f5f1c1df1869460bffaa358bf5a607781388b |
|
19-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't
yet legal according to comments in LegalizeDAG.cpp:227.
Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.
The two failing tests reported in PR10876 pass after applying this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb |
|
29-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 854a7db117707658625c22e546810d564f3e20ea |
|
20-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
needed for Mips32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5ac8547a412d1b42c5ff333fc0becd56b98b74cb |
|
19-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Use subword loads instead of a 4-byte load when the size of a structure (or a
piece of it) that is being passed by value is smaller than a word.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dbe9a316834c79a2a3404fd484424e6c4bf49f5f |
|
18-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Make IsShiftedMask a static function rather than defining it in an
anonymous namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 667645f814523a65cb4c775b06b97234a7b002d7 |
|
18-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Changed definition of EXT and INS per Bruno's comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 511961a44ce4f1947ebb1e476f5cb38c223d4833 |
|
17-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add support for half-word unaligned loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 77b85b647432765e61b9099a3560a3601cb950b7 |
|
17-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bb15e117d328bd991b0723dd1b586c8437d9dced |
|
17-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add support for ext and ins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5c21c9e78ebbb5b766fac31bf30433926dcc2a5d |
|
12-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Define unaligned load and store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 26689ac37ebec3b358588089415509285e558de9 |
|
03-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 14648468011c92a4210f8118721d58c25043daf8 |
|
28-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| db54826f20c6cbcb9b195c4b49c946d6488156dd |
|
20-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Lower memory barriers to sync instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bdd83fe382d6c3d6fc73aa7142e73f30cbd4dfad |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change variable name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cc7ecc72909fe3f2a3eba9e7ac79cd1a13b3e8f2 |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
ANDi, when the instruction does not have any immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4061da1403d8b4e00065a52606eb984f1abd5471 |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Use descriptive variable names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 29af0918ce0795e13f602baba455daeb6faebf0d |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 70564a9c194aa7c86c94227639de4037bbc3cbe8 |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Remove redundant instructions.
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 81b441151fcbf998862adec79540bed049bbfa81 |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Separate code that modifies control flow from code that adds instruction to
basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135490 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 939ece1b5c6c2f142476b477daa573046fa1b8da |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Make EmitAtomic functions return the correct MachineBasicBlocks so that
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a308c670b44f068a660309d6daff7b35d531ddc4 |
|
19-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Do not insert instructions in reverse order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a921164f39d8bb035325db3564b8f2a6acc053dc |
|
18-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Do not treat atomic.load.sub differently than other atomic binary intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0d7d0b5cb7e41173b6fff2f0c2fbdcbebc9693fe |
|
18-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 45473c1b15fcaa7ee29278ec0976667bbfba7234 |
|
18-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change destination register operands of SC instructions so that unique
virtual registers are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
|
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 33390848a7eca75301d04a59b89b516d83e19ee0 |
|
08-Jul-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 794bf17cbe0bac301ef9e52fb4a0295bfdfe0cab |
|
08-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Lower MachineInstr to MC Inst and print to .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d3ac47f80551d95c64cb41c3f94e888d7e13275b |
|
07-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 38d642652320ae84bfd948ab1bfc2fd4b8399bba |
|
29-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Update comment for getRegForInlineAsmConstraint for Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 314aff1474034140a4c5bf3a855963d5259bf90d |
|
29-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Remove getRegClassForInlineAsmConstraint for Mips.
Part of rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 25eba399cb7b4f9691cc63cb3829a00286c70bc4 |
|
24-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change the chain input of nodes that load the address of a function. This change
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5f7451ff6e6967553588716d8630ef3bf8e78120 |
|
21-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Coding style fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 21afc63ea7b8227ccb1b735255be55bf422136d6 |
|
21-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e0b5cfcae88190bd45778e11d20bc676823098a7 |
|
16-Jun-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Silence warnings in non assert builds. Patch by David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6f3661fdcd10a33d225502f8b112dc5b7968ef74 |
|
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 471e4224809f51652c71f319532697a879a75a0d |
|
09-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Add a parameter to CCState so that it can access the MachineFunction.
No functional change.
Part of PR6965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 69b9044c668dfb92038385a96c030778de64edfd |
|
08-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
dynamically allocated stack area was not set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3d21c2495d481f42bab9f8313b46e7bcf0e2d7ac |
|
08-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reorganize code in MipsTargetLowering::LowerCall to improve readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 14487d4f66c3127b29408aae46c1a948d348ec59 |
|
07-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0f843821385213b33116eaecf0c13e987139f6a5 |
|
07-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Coding style fixes.
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2e591477af1ef8e3c5ba6d51e8aeee8c99c7fa8e |
|
02-Jun-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cada2d0966b649b8f04a78f35b9d6d9b4330ce74 |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix uninitialized variables and silence warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4e694c96f1c0c2d09a287ff69bab5896e04dd3fd |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d979686bb47f2dcdca60f0a088f59d1964346453 |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch implements the thread local storage. Implemented are General
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 342837d0dcf4c47765bbd3f9c031418824b12747 |
|
28-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
Need this to prevent emitting illegal conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 33458fedb607e64c46af6797057fbf0b4973a6f6 |
|
26-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
a function has any function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cf0cd8005c81853ddea3ce26b71491c48dc4984e |
|
26-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add support for C++ exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d85b3ecbb36b6ab6cce3c41ef1606108bd8d809d |
|
25-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already
been defined in MipsInstrFPU.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9c3d57c45e0ea788d9c6351345b91d2b8dea0a82 |
|
25-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Custom-lower FCOPYSIGN nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4c62f765a308543577d7e0094020d8d9362a8bcb |
|
25-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Update MaxCallFrameSize regardless of the relocation model selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f15f49850768f5889c2e12aeb273e158597a1223 |
|
25-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should
return 0 if there are no function calls made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| edacba83dc6b34676fe2be60e0bac487a6d1152d |
|
25-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Coding style fixes. Added comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 053546c31e4752e3d76e1f0915ddd6c8a3280351 |
|
25-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix lowering of DYNAMIC_STACKALLOC nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4231c7ea6d278b6a07ce51c28d7e00e1d300d210 |
|
24-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Implement byval structure argument passing. The following limitations or
deficiencies exist:
- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b4d8d31e59b11e7a4d560c01377ce02f1245f056 |
|
24-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Simplify offset calculation of stack frame objects for $gp restore location and
variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 46da136ec79f484decce7c6cfeef42fb25888996 |
|
24-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Expand f64 FPOW.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bdd2ce9741643bab00ba2869852f6babbe072cf0 |
|
23-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fixes related to coding style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 69c19f7316ed8e545c7339421b910543eb8e9eef |
|
23-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change StackDirection from StackGrowsUp to StackGrowsDown.
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 43299776d7cae9843b354b9fcc08186437516d68 |
|
21-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Change the order fixed objects are created in MipsTargetLowering::LowerCall in
preparation for reversing StackDirection.
Fixed objects are created in the following order:
1. Incoming arguments passed on stack.
2. va_arg objects (include both arguments that are passed in registers and
pointer to the location of the first va_arg argument).
3. $gp restore slot.
4. Outgoing arguments passed on stack.
5. Pointer to alloca'd space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d37776d1c15977d9d86cab08250b6cfd847b7cae |
|
20-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
In CC_MipsO32, allocate a stack space regardless of whether the argument is
passed in register or on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 17a1e8775119db75ece41e041eeb6480793696ff |
|
20-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
saving and restoring them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| cd0f90f8317c8b59ed11256f8b0eeb54b3cc22e2 |
|
20-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d992f6c6661e35b1a186a415667cbd3a91d37711 |
|
20-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Remove code that creates unnecessary frame objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a1a7ba838230b4b77604cc9a9fbd22f40f354ba2 |
|
19-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Align i64 arguments to 64 bit boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 95b8ae190ef8ee00d0d5aa7e26cdda9cc9ed6717 |
|
19-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
|
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6b7588e6c4f6f1a9ab2b5182fafaa95eeb56ca8d |
|
04-May-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f48eb533d56ee57afdfdf62fec6a74aa0b3bbf27 |
|
25-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Lower BlockAddress node when relocation-model is static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4552c9a3b34ad9b2085635266348d0d9b95514a6 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0bf3dfbef60e36827df9c7e12b62503f1e345cd0 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 99a2e98eddf00c4afd3817564cb8c914a6f66ae9 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9777e7afd4a9a348f043e914192d491b620659f1 |
|
07-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix handling of functions with internal linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f49fde28772cf73502d31e2755b7c75c0e90a05c |
|
04-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ad8ffad60ae33e834c18072a37b6b30fe45efdf6 |
|
02-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Undo changes mistakenly made in revision 128750.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dc1652fd311073492a169101b8b6e1d725dca280 |
|
02-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Insert space before ';' to prevent warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e2e436a6bc44deb2f989a39514f482b4932b93bc |
|
01-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Simplifies logic for printing target flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1d6b38d9d37d5de471f5954b23b46dac58136fec |
|
31-Mar-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 81bd78b89779704aeb762f51c6c19b06d542b6d6 |
|
30-Mar-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
fixed typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 109d6dbe50753f102566cd4895b69fd13f62efa4 |
|
11-Mar-2011 |
Chris Lattner <sabre@nondot.org> |
silence a conditional assignment -Wuninitialized warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 954dac0f88bcb27c06ce467c43e913ff0aa511bb |
|
09-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Improve varags handling, with testcases. Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 38b5e86b9c67f601f354f8bcc11f5a515e200315 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Improve div/rem node handling on mips. Patch by Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c42fb5f81c80c0d2713ca34d2216ced764ff8b14 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ca8a2aa921ec8966b1f0708d77e4dc0a6f1a32f8 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5d6fb5db908c90fde727b6d07c4f0b8be7d91797 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Expands FCOS and FSIN nodes when type is f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8e826e69db035f5e6c00393ff3f1ebc4c582b2fb |
|
10-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka with some small modifications by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6b9028251cfc5ae93431838dfa6db4750e6b67f4 |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Negative zero is not legal on mips. Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b1fce0a01618da2e3ff41e7ee9ff71924533d646 |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8be76112454e736db1815e6159644bf56ce04ac0 |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 908b6ddad6dac40c4c0453d690f0db9422b48b10 |
|
09-Dec-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bd3af09cef3e628afa480be4923040c29a91d0a3 |
|
07-Dec-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bf17cfa3f904e488e898ac2e3af706fd1a892f08 |
|
23-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1e96bab329eb23e4ce8a0dc3cc6b33a3f03d15bf |
|
04-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
In the calling convention logic, ValVT is always a legal type,
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1440e8b918d7116c3587cb95f4f7ac7a0a0b65ad |
|
03-Nov-2010 |
Duncan Sands <baldrick@free.fr> |
Inside the calling convention logic LocVT is always a simple
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 44ab89eb376af838d1123293a79975aede501464 |
|
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8026a9d3eef3ae30d4ec16a17b7d60d287ddf25d |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate some uses of the getStore overload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d1c24ed81c43635d00ff099844a9d0614021a72b |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert the targets off the non-MachinePointerInfo of getLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 46773793cbf18fa0fa4643c91d3b6f5c5bf15dd9 |
|
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR7174, a couple o Mips fixes:
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.
Patch by stetorvs@gmail.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 29e9daa75019e6ee7b3305f7ef11a2cd85b96b55 |
|
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix Mips PR7473. Patch by stetorvs@gmail.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0d881dabc1a4e1aefad6dd38de166d8358285638 |
|
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Propagate debug loc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 14152b480d09c7ca912af7c06d00b0ff3912e4f5 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert r107655.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b81c771c0d9ab5a980caf3383932b051eafd1a39 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ed2ae136d29dd36122d2476801e7d7a86e8301e3 |
|
03-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f6fa186cf944ad50dcb2f963b2f25d68fbf11d61 |
|
15-Feb-2010 |
David Greene <greened@obbligato.org> |
Remove an assumption of default arguments. This is in anticipation of a
change to SelectionDAG build APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6059b8551dc1ddc24bb5830426bf7e11d394a426 |
|
06-Feb-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add suport for VASTART on Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b37a742333b9d624f2c42b737352a30fd02fbd98 |
|
06-Feb-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
First step towards varargs support in Mips:
- o32 cc must pass all arguments in A0...A3 and stack regardless
if its type (but respect the alignment).
- Store all variable arguments back to the caller stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
|
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3ed6f876c8c30d82dceccfdd7e3f1774a85adc7c |
|
30-Jan-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR6144. Reload GP before the emission of CALLSEQ_END to guarantee the right reload order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f1214cbf3c2d151d3a2353d82143da186313a42a |
|
26-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the TargetLowering::UsesGlobalOffsetTable bool, which is
subsumed by TargetLowering::getJumpTableEncoding(). Change uses of
it to be more specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d71cebf57591e2dc27930d3002848dddc76c3f92 |
|
25-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support PIC loading of constant pool entries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 735afe14eea8049bf69210ce8a3512e391fc643f |
|
24-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bef8888a9197655512f156e50b10799da7240252 |
|
21-Nov-2009 |
Devang Patel <dpatel@apple.com> |
We are not using DBG_STOPPOINT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6e0b658dadc15aecc4e8503b39741148cf18ee1f |
|
16-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Fix a small bug while handling target constant pools (one param was missing).
- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 3f2bf85d14759cc4b28a86805f566ac805a54d00 |
|
12-Nov-2009 |
David Greene <greened@obbligato.org> |
Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a1eaa3c52b75d4fe2bcd4f7c52e56c405ee91d3c |
|
28-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a second ValueType argument to isFPImmLegal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| eb2f969a4ddfb0bc8fdcb5bce3b52e53abff321d |
|
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ce31910eae5bd4896fa6c27798e7b26885691d3b |
|
19-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
|
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c517cb006553320875544f39655c3299124be3ea |
|
01-Sep-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply 80278
Add MO flags to simplify the printing of relocations.
Remove the support for printing large code model relocs (which
aren't supported anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0c80be59c7ccbd844b5dee71b038090052cac07b |
|
27-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert 80278 for now, it caused a lot of MIPS tests to fail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| dcace5c6209bdcb66d6b030b461b07a15ee569c9 |
|
27-Aug-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revamp our friend Mips :)
Add MO flags to simplify the printing of relocations.
Remove the support for printing large code model relocs (which
aren't supported anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b71b909bc76f48377fc96547d53a088346852600 |
|
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
reintroduce support for Mips "small" section handling. This is
implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e3736f86caae62b691ad5be960e724fe0bf52dbd |
|
13-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Restore some "small section" support code, reverting my patch from r76936.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 77547befdc430633aaedf4130ddf17d953ed552e |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
|
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e2c74081998af2e64ed498d65cf501704796ccc0 |
|
03-Aug-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove -disable-mips-abicall and -enable-mips-absolute-call command-line
options, which don't appear to be useful. -enable-mips-absolute-call is
completely unused (and unless I'm mistaken, is supposed to have the
same effect that -relocation-model=dynamic-no-pic should have),
and -disable-mips-abicall appears to be effectively a
synonym for -relocation-model=static. Adjust the few users of hasABICall
to checks which seem more appropriate. Update MipsSubtarget,
MipsTargetMachine, and MipselTargetMachine to synchronize with recent
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f0144127b98425d214e59e4a1a4b342b78e3642b |
|
28-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d94061f1239cf6c9f8a841f8b208158be134a814 |
|
24-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove more remnants of small section support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e922c0201916e0b980ab3cfe91e1413e68d55647 |
|
22-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Get rid of the Pass+Context magic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6055a6adb792f857fe04d8880a6cfb8914828046 |
|
17-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
One more operation expansion for MIPS, from test/CodeGen/Generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 10a365910158a1c3749cd614f29109f78d62beec |
|
17-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Expand a bunch of illegal operations on MIPS (found by
inspection and running over CodeGen/Generic).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1ca29d318a6632c115b9f62c791077b575494e42 |
|
13-Jul-2009 |
Owen Anderson <resistor@mac.com> |
As Chris pointed out, this doesn't actually need an LLVMContext to operate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0a5372ed3e8cda10d724feda3c1a1c998db05ca0 |
|
13-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Begin the painful process of tearing apart the rat'ss nest that is Constants.cpp and ConstantFold.cpp.
This involves temporarily hard wiring some parts to use the global context. This isn't ideal, but it's
the only way I could figure out to make this process vaguely incremental.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d1474d09cbe5fdeec8ba0d6c6b52f316f3422532 |
|
09-Jul-2009 |
Owen Anderson <resistor@mac.com> |
Thread LLVMContext through MVT and related parts of SDISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6314ac2bca0dfad6951931862b75a4586c9c8249 |
|
16-Jun-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Misc accumulated tweaks to legalization logic for various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9911405183f8596fe9d521467f83f6652a296cf4 |
|
03-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Convert Alpha and Mips to use a MachineFunctionInfo subclass to
carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This
eliminates the need for them to search through the
MachineRegisterInfo livein list in order to identify these
virtual registers. EmitLiveInCopies is now the only user of the
virtual register portion of MachineRegisterInfo's livein data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d3bdf19ce7a37e23a6c4d877fb681eb010be74f7 |
|
27-May-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for fround, fextend and FP_TO_SINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 777d2306b36816a53bc1ae1244c0dc7d998ae691 |
|
09-May-2009 |
Duncan Sands <baldrick@free.fr> |
Rename PaddedSize to AllocSize, in the hope that this
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| fc1665793e62eb4f26d24b8a19eecf59cd872e2a |
|
10-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Remove the obsolete SelectionDAG::getNodeValueTypes and simplify
code that uses it by using SelectionDAG::getVTList instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d4015074e47a6716e7dc0d82296a9d2e55437987 |
|
26-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
fix an apparently real bug exposed by a warning in -asserts mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bdfbb74d34dafba3c5638fdddd561043823ebdd2 |
|
21-Mar-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Removed AFGR32 register class
Handle odd registers allocation in FGR32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b53db4fb321823a8a1f6abc372bdc7c36ef1447f |
|
19-Mar-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for Mips O32 Calling Convention
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 948175785d1e5e7d3d627d11dbb0392b976d135d |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of BuildMI from IA64, Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1fdbc1dd4e9cb42c79a30e8dc308c322e923cc52 |
|
07-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
ScheduleDAG's TLI member to use const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b300d2aa3ef08b5074449e2c05804717f488f4e4 |
|
07-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of the last non-DebugLoc versions of getNode!
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| de06470330260f5937e7ca558f5f5b3e171f2ee5 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a05dca4f9e051fad19fe9b5f6cce2715c1e5d505 |
|
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 33c960f523f2308482d5b2816af46a7ec90a6d3d |
|
04-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of getLoad and getStore.
Adjust the many callers of those versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5bf4b7556f025587a8d1a14bd0fb39c12fc9c170 |
|
26-Jan-2009 |
Nate Begeman <natebegeman@mac.com> |
Fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bb46f52027416598a662dc1c58f48d9d56b1a65b |
|
15-Jan-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add the private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ceb4d1aecb9deffe59b3dcdc9a783ffde8477be9 |
|
12-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5480c0469e5c0323ffb12f1ead2abd169d6cc0e7 |
|
01-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| aaffa05d0a652dd3eae76a941d02d6b0469fa821 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60349 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 03228089d5235f8c90477f88809139464e9c6ea5 |
|
23-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC,
however the concept is more general.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6520e20e4fb31f2e65e25c38b372b19d33a83df4 |
|
18-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f522068412218cd14b2c2df74a3437717d255381 |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0329466b6b4927f4e6f5d144891fef06a027fec5 |
|
14-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rename LoadX to LoadExt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e563bbc312f8b11ecfe12b8187176f667df1dff3 |
|
12-Oct-2008 |
Chris Lattner <sabre@nondot.org> |
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 056292fd738924f3f7703725d8f630983794b5a5 |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 9468a9b6beed640eca64274c8dcc5aed3b94450b |
|
16-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 095cc29f321382e1f7d295e262a28197f92c5491 |
|
13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 99a6cb92d173c142073416c81efe6d3daeb80b49 |
|
27-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
disallow direct access to SDValue::ResNo, provide a getter instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 739e441311410796d66e6d72426ef0344e0be98f |
|
13-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT node
is lowered properly and covers everything LowerSELECT_CC did.
Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This
avoid the ugly instruction by instruction checking in printOperand.
Added a swap instruction present in the allegrex core.
Added two conditional instructions present in the allegrex core : MOVZ and MOVN.
They both allow a more efficient SELECT operation for integers.
Also added SELECT patterns to optimize MOVZ and MOVN usage.
The brcond and setcc patterns were cleaned: redundant and suboptimal patterns
were
removed. The suboptimals were replaced by more efficient ones.
Fixed some instructions that were using immZExt16 instead of immSExt16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 65ad452536526fe9a80023abc3703a7cc7987858 |
|
08-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support added for ctlz intrinsic, test case added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7da151cd5deb9f77ea68806633f3a1ccc3e7c903 |
|
07-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added Mips support for DYNAMIC_STACKALLOC
Fixed bug in adjustMipsStackFrame, which was breaking
while trying to access a dead stack object index. Also added
one more alignment before fixing the callee saved registers
stack offset adjustment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f7f3b50cd8c10c20f68045c5322f134bd83b06c7 |
|
04-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Mips ISelLowering cleanup : Removed old LowerCALL and FORMAL_ARGS helpers, they
aren't used anyway, they also used to broke compiling when fastcc was specified for a
function, but not anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ea9d4d6ab0e3e37e2c0d62e4981df79b82d7ef96 |
|
04-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Handle i32->f32 bitconvert results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1906c5a63b1b6f32c3f5a0ed9261144bc1ddbc3a |
|
02-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Apply the same pattern used in 'and' lowering for 'or'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7bd7182e21dfbbb163802db0068b994de1def7da |
|
31-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Expand fcopysign
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 772837778b831a52231ff33ef42d7970e9aa8467 |
|
31-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Handle more SELECT corner cases considering legalize types, probabily wont work with
the default legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7030ae7728fb7d5f937f72943d73fc69c4d451c0 |
|
30-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added pattern for floating point zero immediate (avoiding a constant pool
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4b877ca1c5f13f19c9b7c8142a4f7a23383b8b6a |
|
30-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixed bug in global address lowering for functions and in Brcond lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 97843cdb0b63735a4ade07cf7270c9a2198e0dc7 |
|
29-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Changed some methods order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 6d399bdea269658a03b63de850595fbfdd487098 |
|
29-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added floating point lowering for select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f33bc43c9a2a903e1cccefb616ed07d5a2ae4204 |
|
28-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Disable gp_rel relocation for constant pools access for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 85e31e3a5301c31947e35258dce7efa8e788bd51 |
|
28-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added floating point lowering for setcc and brcond.
Fixed COMM asm directive usage.
ConstantPool using custom FourByteConstantSection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 92e87f23791851efb8f6a13c29bffe48f2850527 |
|
23-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Minor fixes.
Added ConstantPool support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| feb95cc7e3e557f6d803a8c03a0b37ec4691d474 |
|
22-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added small section asm emition logic for mips.
Fixed small bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 91fd532eb9a18c0fd8d91b975226ef6b41c772ec |
|
21-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added initial support for small sections on Mips.
Added gp_rel relocations to support addressing small section contents.
Added command line to specify small section threshold in bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| b27cb55923024907f7dba43d24ec37408ef1f574 |
|
15-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixed call stack alignment. Improved AsmPrinter alignment issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 06b8c199573c6f9031cc42f8073ae1781c3f2f19 |
|
09-Jul-2008 |
Bill Wendling <isanbard@gmail.com> |
Silence warning by initializing variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7728f7e890fd326af6948c52092fc9ea4f38c986 |
|
09-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixed features usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7b76da145be2b3b7518ca42b43a903eabd52e1b7 |
|
09-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixe typos and 80 column size problems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 97c2537269e8c654bc9b3c471ebab927e9cf0b2a |
|
09-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
MipsTargetLowering cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 1512642973f8b86e8375d93f6b30a2930e68d224 |
|
08-Jul-2008 |
Duncan Sands <baldrick@free.fr> |
Pacify gcc-4.3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
|
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 85e9212fcdd63d8b796d09c87f99eae5153a6c8a |
|
07-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
fixed 32-bit fp_to_sint pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 225ca9cdd70de3d12641b0aba7daf6cb568a7ebd |
|
05-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4406604047423576e36657c7ede266ca42e79642 |
|
01-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7f460203b0c5350e9b2c592f438e40f7a7de6e45 |
|
30-Jun-2008 |
Dan Gohman <gohman@apple.com> |
Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect its
purpose, and give it a custom SDNode subclass so that it doesn't
need to have line number, column number, filename string, and
directory string, all existing as individual SDNodes to be the
operands.
This was the only user of ISD::STRING, StringSDNode, etc., so
remove those and some associated code.
This makes stop-points considerably easier to read in
-view-legalize-dags output, and reduces overhead (creating new
nodes and copying std::strings into them) on code containing
debugging information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f9516208e57364ab1e7d8748af1f59a2ea5fb572 |
|
30-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 07cec75913b74d04df40ff7fecf51f87175076c1 |
|
06-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added custom SELECT_CC lowering
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d2947ee33e810b24a016b944b375d34910f8f5dd |
|
04-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Some Mips minor fixes
Added support for mips little endian arch => mipsel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| bdbb750afeb66f3c32aca479119867e44f1da60b |
|
01-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixed flag issue that was generating infinite loop while in list scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
|
12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d27c991cebe48fdf82b5d9eec6c2a1a244f82622 |
|
30-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| e0b1215a9299119f064245db1b28bfde55e8950a |
|
17-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
minor cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d2cde68855125b6815b1575f29cd96927614b0cd |
|
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Default ISD::PREFETCH to expand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 5b8f82e35b51bf007de07a7ca9347d804084ddf8 |
|
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 27b7db549e4c5bff4579d209304de5628513edeb |
|
08-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| d497d9fab6e90499c703f3e672ec001dbfa074f9 |
|
16-Feb-2008 |
Andrew Lenharth <andrewl@lenharth.org> |
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| ddf89566a93081cb230bb9406a72ab2d3eada4a7 |
|
17-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50 |
|
13-Nov-2007 |
Bill Wendling <isanbard@gmail.com> |
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 753a98740bfe3164fd0961a1959306c46135cf19 |
|
12-Nov-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added JumpTable support
Fixed some AsmPrinter issues
Added GLOBAL_OFFSET_TABLE Node handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| c7db5618f9e5e708b87d9ae6595b3fd510a2a0c0 |
|
05-Nov-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for PIC code with "explicit relocations" *only*.
Removed all macro code for PIC (goodbye "la").
Support tested with shootout bench.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 8262df3aa49feaae18a86d21ed8a20427d638218 |
|
09-Oct-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Position Independent Code (PIC) support [3]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| f7331b3dd72409e644833ecaf62a0f6db03c97ee |
|
11-Sep-2007 |
Duncan Sands <baldrick@free.fr> |
Fold the adjust_trampoline intrinsic into
init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| a2b1bb5296624d32a200f9c53d6f26c0c9c3bddc |
|
28-Aug-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Changed stack allocation On LowerFORMAL_ARGUMENTS.
Added comments about new stack allocation.
Expand SelectCC for i32 results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 84f47c52fd3c13a781134a8df6cfb918dce0033a |
|
21-Aug-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
InlineAsm asm support for integer registers added
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 7ff6fa25037d207e31f65bedc8616a90f61abc25 |
|
18-Aug-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress
fixed to generate instructions (add, lui) glued!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 36397f50343639ce9a25996f2d790c656791ab92 |
|
27-Jul-2007 |
Duncan Sands <baldrick@free.fr> |
Support for trampolines, except for X86 codegen which is
still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 2ab22d1b9313dea627162309fb434b990d4dd6d6 |
|
12-Jul-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixed AddLiveOut issues
FI's created the write way to represent Mips stack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 75ce010f7b6a47d9656e546b5db4a9cd77ba1dee |
|
11-Jul-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Assert when TLS is not implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|
| 972f5896e417d8e81cf400083fab15a37b6d4277 |
|
06-Jun-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial Mips support, here we go! =)
- Modifications from the last patch included
(issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsISelLowering.cpp
|