History log of /external/llvm/lib/Target/R600/R600ISelLowering.cpp
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2c3e0051c31c3f5b2328b447eadf1cf9c4427442 06-May-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r235153

Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
c6a4f5e819217e1e12c458aed8e7b122e23a3a58 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
19a99df130f5747da950faf4ca5170d71f05594c 15-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600: Fix scheduling of instructions that use the LDS output queue

The LDS output queue is accessed via the OQAP register. The OQAP
register cannot be live across clauses, so if value is written to the
output queue, it must be retrieved before the end of the clause.
With the machine scheduler, we cannot statisfy this constraint, because
it lacks proper alias analysis and it will mark some LDS accesses as
having a chain dependency on vertex fetches. Since vertex fetches
require a new clauses, the dependency may end up spiltting OQAP uses and
defs so the end up in different clauses. See the lds-output-queue.ll
test for a more detailed explanation.

To work around this issue, we now combine the LDS read and the OQAP
copy into one instruction and expand it after register allocation.

This patch also adds some checks to the EmitClauseMarker pass, so that
it doesn't end a clause with a value still in the output queue and
removes AR.X and OQAP handling from the scheduler (AR.X uses and defs
were already being expanded post-RA, so the scheduler will never see
them).

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
a2b4eb6d15a13de257319ac6231b5ab622cd02b1 14-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Add support for private address space load/store

Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
29f1788de96cbf88ab87e3da130cf626b2e8e029 13-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600: Fix selection failure on EXTLOAD

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
837dd95d6c8cb4f23df4e54eac027eb289991629 12-Nov-2013 Vincent Lejeune <vljn@ovi.com> R600: Reenable llvm.R600.load.input/interp.input for compatibility

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
70a7d5ddb4f00bbb61afe7b536c6f599f771ab9a 11-Nov-2013 Vincent Lejeune <vljn@ovi.com> R600: Use function inputs to represent data stored in gpr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
7a59defe70257302e2f68daba2fb8e1735e7cd0e 01-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Use isa<> instead of dyn_cast<> with unused value

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
dbd936f6ccd2588e8e232d9843d45d3697dce1c3 31-Oct-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Fix a few typos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
1fe9069d53f586963d61523f7c5a7d41d80a9d8b 28-Oct-2013 NAKAMURA Takumi <geek4civic@gmail.com> Prune utf8 chars in comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
661bd3df7518a3d984dada66473602a0401618ba 28-Oct-2013 NAKAMURA Takumi <geek4civic@gmail.com> Target/R600: Un-tab-ify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f95b1621887e3409ceec2db47e1b44271d934735 23-Oct-2013 Tom Stellard <thomas.stellard@amd.com> R600: Fix handling of vector kernel arguments

The SelectionDAGBuilder was promoting vector kernel arguments to legal
types, but this won't work for R600 and SI since kernel arguments are
stored in memory and can't be promoted. In order to handle vector
arguments correctly we need to look at the original types from the LLVM IR
function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f2b3a569ae25dbba264cef93602b4147d2a723d6 13-Oct-2013 Vincent Lejeune <vljn@ovi.com> R600: Use masked read sel for texture instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
91ec4b0cac7a7476a9d30d6f1adbf218ee6673a0 13-Oct-2013 Vincent Lejeune <vljn@ovi.com> R600: fix swizzle export

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
a2f1317f09ac6b4a7239b033fabd216d71b77629 02-Oct-2013 Vincent Lejeune <vljn@ovi.com> R600: Add a ldptr intrinsic to support MSAA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
9c598cfebcc3387676995873e65ae4fed96b3edc 28-Sep-2013 Tom Stellard <thomas.stellard@amd.com> R600: Fix handling of NAN in comparison instructions

We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
bbafe422d6f9036b03992ee5eacb5d09644c3267 28-Sep-2013 Tom Stellard <thomas.stellard@amd.com> SelectionDAG: Improve legalization of SELECT_CC with illegal condition codes

SelectionDAG will now attempt to inverse an illegal conditon in order to
find a legal one and if that doesn't work, it will attempt to swap the
operands using the inverted condition.

There are no new test cases for this, but a nubmer of the existing R600
tests hit this path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
12d43f9baf83b6a2cc444c89bb688ebfe01a9fa1 28-Sep-2013 Tom Stellard <thomas.stellard@amd.com> SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()

This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.

There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
5251d180f4af15414a9c7ae5723dd48bc938576b 13-Sep-2013 Vincent Lejeune <vljn@ovi.com> R600: Move clamp handling code to R600IselLowering.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f57d692c11f0ff6e9c45d2c48c5f362f4c575cf7 13-Sep-2013 Vincent Lejeune <vljn@ovi.com> R600: Move code handling literal folding into R600ISelLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
fe7831861432d71de47ce502e799fb7264b9f24c 13-Sep-2013 Vincent Lejeune <vljn@ovi.com> R600: Move fabs/fneg/sel folding logic into PostProcessIsel

This move makes possible to correctly handle multiples instructions
from a single pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
79916948e1fd176a3898b596b679cc9dba3d40a8 05-Sep-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add support for local memory atomic add

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
756f382ac116d1d935fe5c01f2c07c19c0aac77a 05-Sep-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand SELECT nodes rather than custom lowering them

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
d08a9303614355cfdcac5f2c27c09ce809565423 26-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add support for vector local memory loads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
a01cdea9c660dc8b295782a4ab560d0039ff7571 26-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add support for i8 and i16 local memory loads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
7a0282daeb214f14d75249cc2d90302c44586c4e 26-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add support for v4i32 and v2i32 local stores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
0991c314d7c1a2052963dc89af1d2f07134488b6 17-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand vector float operations for both SI and R600

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
4c52d450dc3968267d1f089d36397fc785dcc7b4 16-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add support for global vector stores with elements less than 32-bits

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
ec484277dd04399d7b2ea37508e39fc4998bc9a7 16-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add support for i16 and i8 global stores

Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f15dfe4eb48e8e2ff02a30bc8ba9112108f9b83d 13-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Set scheduling preference to Sched::Source

R600 doesn't need to do any scheduling on the SelectionDAG now that it
has a very good MachineScheduler. Also, using the VLIW SelectionDAG
scheduler was having a major impact on compile times. For example with
the phatk kernel here are the LLVM IR to machine code compile times:

With Sched::VLIW

Total Compile Time: 1.4890 Seconds (User + System)
SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System)

With Sched::Source

Total Compile Time: 0.3330 Seconds (User + System)
SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System)

The code ouput was identical with both schedulers. This may not be true
for all programs, but it gives me confidence that there won't be much
reduction, if any, in code quality by using Sched::Source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
692ee102ebef535d311c35d53457028083e5c5be 01-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add 64-bit float load/store support

* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
e3d60ac33421a69545e2989b890899d76a918d2f 30-Jul-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Expand vector fp <-> int conversions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
15d1b85094cf4c1520fdfd12db2111cd36a194db 30-Jul-2013 Quentin Colombet <qcolombet@apple.com> [R600] Replicate old DAGCombiner behavior in target specific DAG combine.

build_vector is lowered to REG_SEQUENCE, which is something the register
allocator does a good job at optimizing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
58d3335cb9d2a40bd15c29a12ba045163295190e 23-Jul-2013 Tom Stellard <thomas.stellard@amd.com> R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()

This increases the number of opportunites we have for folding. With the
previous implementation we were unable to fold into any instructions
other than the first when multiple instructions were selected from a
single SDNode.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
a7eea0568c16f8e25b9e3ba9b7b73ae506738b63 23-Jul-2013 Tom Stellard <thomas.stellard@amd.com> R600: Use KCache for kernel arguments

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f502c292f6edd6b0562a93cc67cd241f52a57d54 23-Jul-2013 Tom Stellard <thomas.stellard@amd.com> R600: Use the same compute kernel calling convention for all GPUs

A side-effect of this is that now the compiler expects kernel arguments
to be 4-byte aligned.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
5864284d71ed89a4280e5171c389ad83fe183db7 23-Jul-2013 Tom Stellard <thomas.stellard@amd.com> R600: Use correct LoadExtType when lowering kernel arguments

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
2bb20fd2bf37d9a608a89b7253881a59686ed2e4 23-Jul-2013 Tom Stellard <thomas.stellard@amd.com> R600: Clean up extended load patterns

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f5660aab413539bd94cfea8cd88fed80c54cd984 18-Jul-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand VSELECT for all types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
a3e39dc7055486cbf514ccd868cfabc69d7f6f4e 10-Jul-2013 Michel Danzer <michel.daenzer@amd.com> R600/SI: Initial local memory support

Enough for the radeonsi driver to use it for calculating derivatives.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f4bdec2ebeb1306a77e9377583c5799199775f88 09-Jul-2013 Vincent Lejeune <vljn@ovi.com> R600: Fix a rare bug where swizzle optimization returns wrong values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
c6f13db656c7649f933c74c4f90c09ff74de52a8 09-Jul-2013 Vincent Lejeune <vljn@ovi.com> R600: Use DAG lowering pass to handle fcos/fsin

NOTE: This is a candidate for the stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
e3d4cbc7d25061441adafa47450a31571c87bf85 28-Jun-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add local memory support via LDS

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0 25-Jun-2013 Tom Stellard <thomas.stellard@amd.com> R600: Use new getNamedOperandIdx function generated by TableGen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f97c7fef52098bbd6a7ccc69657d112a36d77660 25-Jun-2013 Aaron Watry <awatry@gmail.com> R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI

By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
e80978f9dd6bd8951d968fd2e85ec4c0996b62f5 25-Jun-2013 Aaron Watry <awatry@gmail.com> R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG

Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
eb3aa070c9b3984c375ef65ef6e5f113efd7e968 20-Jun-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand v2i32 load/store instead of custom lowering

The custom lowering causes llc to crash with a segfault.

Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
6c59c7a6fdc5b58de4f3c349b59a567c239818e4 11-Jun-2013 Benjamin Kramer <benny.kra@googlemail.com> R600: Make helper functions static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
b5632b5b456db647b42239cbd4d8b58c82290c4e 07-Jun-2013 Bill Wendling <isanbard@gmail.com> Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
98017a015bb862afce4f90d432eded4e28fe1d26 04-Jun-2013 Vincent Lejeune <vljn@ovi.com> R600: Swizzle texture/export instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
0962e147a439785279c3665379189017e980e0cc 03-Jun-2013 Vincent Lejeune <vljn@ovi.com> R600: Constraints input regs of interp_xy,_zw

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
ac6d9bec671252dd1e596fa71180ff6b39d06b5d 25-May-2013 Andrew Trick <atrick@apple.com> Track IR ordering of SelectionDAG nodes 2/4.

Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
7849728485570f34bb100baef613a80d84450b08 22-May-2013 NAKAMURA Takumi <geek4civic@gmail.com> R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Specify namespaces explicitly here.

MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
51c2e124e3a559d5728acb4b6cd130e2129b4135 22-May-2013 NAKAMURA Takumi <geek4civic@gmail.com> R600: Whitespace and untabify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
ba534c21437ba133cb9d6b3f9dae80fa9c4f0cb7 20-May-2013 Tom Stellard <thomas.stellard@amd.com> R600: Swap the legality of rotl and rotr

The hardware supports rotr and not rotl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
225ed7069caae9ece32d8bd3d15c6e41e21cc04b 18-May-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Add LLVMContext argument to getSetCCResultType

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
df98ad3959f164b8b06de4a7eaa5ffe41c4c017c 17-May-2013 Vincent Lejeune <vljn@ovi.com> R600: Lower int_load_input to copyFromReg instead of Register node

It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
4ed9917147b1d1f2616f7c941bbe6999b979f510 17-May-2013 Vincent Lejeune <vljn@ovi.com> R600: Relax some vector constraints on Dot4.

Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
d3293b49f9c7af741d2edd3062499fb50db0e89b 17-May-2013 Vincent Lejeune <vljn@ovi.com> R600: Improve texture handling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
dde683645672b5832ec189cd27123857183e70bb 10-May-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand SUB for v2i32/v4i32

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
6c40d40d709d987dd2674a7c44dcd4c53a80fc23 10-May-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand MUL for v4i32/v2i32

Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
4fca5c1440a9310045a9bc1e1c778a1c7eca864e 10-May-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand SRA for v4i32/v2i32

v2: Add v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
bdd9b1e89f22d11d38012bfec8101b063efb4549 10-May-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand vselect for v4i32 and v2i32

v2: Add vselect v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
19301d5d1234d032d42f20deb6f3076c972fd5f4 03-May-2013 Tom Stellard <thomas.stellard@amd.com> R600: Expand vector or, shl, srl, and xor nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
aa6deab60871d251bf121c2b894105e68f349ba5 25-Apr-2013 Tom Stellard <thomas.stellard@amd.com> R600: Initialize BooleanVectorContents

Fixes test/CodeGen/R600/setcc.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
45b14e341a8a85e877d001bbd43f5e2b25b61cb8 27-Mar-2013 Christian Konig <christian.koenig@amd.com> R600/SI: add mulhu/mulhs patterns

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
c446baa0be1ed2a3bf157519f89a65d348aad17c 22-Mar-2013 Michel Danzer <michel.daenzer@amd.com> R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics

Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g.
manifested by failure of two piglit/glean tests and intermittent black
patches in many apps.

Tested on SI and RS880.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g]

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
fd49dac48fee6da580157515dec55ed2f2d8f2b3 11-Mar-2013 Vincent Lejeune <vljn@ovi.com> R600: Fix JUMP handling so that MachineInstr verification can occur

This allows R600 Target to use the newly created -verify-misched llc flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
7893d29c62146baddf43c4d9d42678d246a52fea 08-Mar-2013 Tom Stellard <thomas.stellard@amd.com> R600: Optimize another selectcc case

fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
selectcc x, y, a, b, cc

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
1454cb86be54a8703fca396752be71c50c805b88 08-Mar-2013 Tom Stellard <thomas.stellard@amd.com> R600: Improve custom lowering of select_cc

Two changes:
1. Prefer SET* instructions when possible
2. Handle the CND*_INT case with floating-point args

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
d41650590669bf561d8f3bcae1204f11354954dc 08-Mar-2013 Tom Stellard <thomas.stellard@amd.com> R600: Change operation action from Custom to Expand for BR_CC

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
9c6b0b0ccebf9d9bf0f357a1c72ef941c5bbb2b2 08-Mar-2013 Tom Stellard <thomas.stellard@amd.com> R600: Change operation action from Custom to Expand for SETCC

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
ff1ccdf9c58d12b142b3ab7473ac531cc5728a06 08-Mar-2013 Tom Stellard <thomas.stellard@amd.com> R600: Set BooleanContents to ZeroOrNegativeOneBooleanContent

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
ff408c07282309a8a3d4daca7c7e127d2fce01ed 07-Mar-2013 Christian Konig <christian.koenig@amd.com> R600/SI: remove SGPR address space v2

v2: fix R600 regressions

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
c3c169c8844db7f8934fbb3a411290dc3cdcb543 07-Mar-2013 Christian Konig <christian.koenig@amd.com> R600/SI: remove shader type intrinsic

Just encode the type as target specific attribute.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
d4c3e566922e04296c29cc4a1695e06a2b53bcb7 05-Mar-2013 Vincent Lejeune <vljn@ovi.com> R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.

Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case
and taking them in account for scheduling is difficult for no real benefit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
3f7f8e814ef49b79b9c41e75df40be3bdb3612f5 05-Mar-2013 Vincent Lejeune <vljn@ovi.com> R600: Add support for indirect addressing of non default const buffer

NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
23339b68e224cedac1e7025ba8bca3e3eb127fab 19-Feb-2013 Tom Stellard <thomas.stellard@amd.com> R600: Fix scheduler crash caused by invalid MachinePointerInfo

Kernel function arguments are lowered to loads from the PARAM_I address
space. When creating these load instructions, we were initializing
their MachinePointerInfo with an Arguement object that was not attached
to any function. This was causing the MachineScheduler to crash when
it tried to access the parent of the Arguement.

This has been fixed by initializing the MachinePointerInfo with a
UndefValue instead.

NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
abfd5f6154b10cc5801bc9e1b8e8221df0113c68 14-Feb-2013 Vincent Lejeune <vljn@ovi.com> R600: Fold zero/one in export instructions

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
1234c9be42b4ebd4b398df461123205dccf3706c 07-Feb-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add support for SET*_DX10 instructions

These instructions compare two floating point values and return an
integer true (-1) or false (0) value.

When compiling code generated by the Mesa GLSL frontend, the SET*_DX10
instructions save us four instructions for most branch decisions that
use floating-point comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8 06-Feb-2013 Tom Stellard <thomas.stellard@amd.com> R600: Support for indirect addressing v4

Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.

At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.

v2:
- Add support for i8 zext load from stack.
- Coding style fixes

v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.

v4:
- Fix 64-bit defines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
a499d2bcef0c1001c60d752d356e50eed2402ca8 05-Feb-2013 Jakob Stoklund Olesen <stoklund@2pi.dk> Don't use MRI liveouts in R600.

Something very strange is going on with the output registers in this
target. Its ISelLowering code is inserting dangling CopyToReg nodes,
hoping that those physregs won't get clobbered before the RETURN.

This patch adds the output registers as implicit uses on RETURN
instructions in the custom emission pass. I'd much prefer to have those
CopyToReg nodes glued to the RETURNs, but I don't see how.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
29b15a378045762ce09642ab9dd741ece41f59a3 05-Feb-2013 Tom Stellard <thomas.stellard@amd.com> R600: improve inputs/interpolation handling

Use one intrinsic for all sorts of interpolation.
Use two separate unexpanded instructions to represent INTERP_XY and _ZW -
this will allow to eliminate one part if it's not used.
Track liveness of special interpolation regs instead of reserving them -
this will allow to reuse those regs, lowering reg pressure.

Patch By: Vadim Girlin

v2[Vincent Lejeune]: Rebased against current llvm master

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
cacbcb0f2c60d45618dee0e10ded2ed2052166a6 31-Jan-2013 Tom Stellard <thomas.stellard@amd.com> R600: Consider bitcast when folding const_address node.

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
254a83e46c0ffb08c5c77d99f64d6e86db550c6f 23-Jan-2013 Tom Stellard <thomas.stellard@amd.com> R600: Add a llvm.R600.store.swizzle intrinsics

This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its
name. It is used to store vs/fs outputs

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
2a3e0d7e76079289e2b007a15c311c51218f0b89 23-Jan-2013 Tom Stellard <thomas.stellard@amd.com> R600: Simplify stream outputs intrinsic

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
9f7818d9bdfce2e9c7a2cbe31490a135aa6d1211 23-Jan-2013 Tom Stellard <thomas.stellard@amd.com> R600: rework handling of the constants

Remove Cxxx registers, add new special register - "ALU_CONST" and new
operand for each alu src - "sel". ALU_CONST is used to designate that the
new operand contains the value to override src.sel, src.kc_bank, src.chan
for constants in the driver.

Patch by: Vadim Girlin

Vincent Lejeune:
- Use pointers for constants
- Fold CONST_ADDRESS when possible

Tom Stellard:
- Give CONSTANT_BUFFER_0 its own address space
- Use integer types for constant loads

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
0b8c9a80f20772c3793201ab5b251d3520b9cea3 02-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
58a2cbef4aac9ee7d530dfb690c78d6fc11a2371 02-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600ISelLowering.cpp
519b456fe1eae633854584f54c8804498b256381 21-Dec-2012 Tom Stellard <thomas.stellard@amd.com> R600: Expand vec4 INT <-> FP conversions

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/external/llvm/lib/Target/R600/R600ISelLowering.cpp
08f2d9379c486a0e4b950e476913ee97b38ec333 13-Dec-2012 Tom Stellard <thomas.stellard@amd.com> Fix warnings with -DNDEBUG

Patch by: NAKAMURA Takumi

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/external/llvm/lib/Target/R600/R600ISelLowering.cpp
f98f2ce29e6e2996fa58f38979143eceaa818335 11-Dec-2012 Tom Stellard <thomas.stellard@amd.com> Add R600 backend

A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

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/external/llvm/lib/Target/R600/R600ISelLowering.cpp