History log of /external/llvm/lib/Target/R600/SIRegisterInfo.cpp
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4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
c6a4f5e819217e1e12c458aed8e7b122e23a3a58 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
3560dd2dcd67d42eeb8e59975581d598d71669df 18-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> R600/SI: Fix moveToVALU when the first operand is VSrc.

Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
5cddda6d13ab66c462ccbd61255ad6e6f95e9f6f 15-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()

This fixes a crash with GNOME settings manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
a2b4eb6d15a13de257319ac6231b5ab622cd02b1 14-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Add support for private address space load/store

Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
b52bf6a3b31596a309f4b12884522e9b4a344654 14-Nov-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Prefer SALU instructions for bit shift operations

All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
9988ad4ae684caa566773d3eda4d55707b92c0cd 10-Nov-2013 Matt Arsenault <Matthew.Arsenault@amd.com> Make method static

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
219e788dc6e38120266d366a51286739fa33123b 10-Oct-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Mark the EXEC register as reserved

This prevents the machine verifier from complaining about uses of
an undefined physical register.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
636298ba64fd07d4ddcae6005e7fc1db43eb5335 15-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Choose the correct MOV instruction for copying immediates

The instruction selector will now try to infer the destination register
so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying
immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
3406d882c02a6cd1e16f4636351c23dcb68d785f 07-Aug-2013 Tom Stellard <thomas.stellard@amd.com> R600/SI: Add more special cases for opcodes to ensureSRegLimit()

Also factor out the register class lookup to its own function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
b5632b5b456db647b42239cbd4d8b58c82290c4e 07-Jun-2013 Bill Wendling <isanbard@gmail.com> Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
c53270f885e8d778cfe0e741e07d7def2b66884a 26-Mar-2013 Christian Konig <christian.koenig@amd.com> R600/SI: switch back to RegPressure scheduling

Signed-off-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp
f98f2ce29e6e2996fa58f38979143eceaa818335 11-Dec-2012 Tom Stellard <thomas.stellard@amd.com> Add R600 backend

A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIRegisterInfo.cpp