| 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 |
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
Arch64/arm64-elf-reloc-condbr.s
Arch64/arm64-fp-encoding-error.s
Arch64/armv8.1a-lor.s
Arch64/armv8.1a-pan.s
Arch64/armv8.1a-rdma.s
Arch64/armv8.1a-vhe.s
Arch64/elf-extern.s
Arch64/elf-globaladdress.ll
Arch64/elf-reloc-addsubimm.s
Arch64/elf-reloc-ldrlit.s
Arch64/elf-reloc-ldstunsimm.s
Arch64/elf-reloc-movw.s
Arch64/elf-reloc-pcreladdressing.s
Arch64/elf-reloc-tstb.s
Arch64/elf-reloc-uncondbrimm.s
Arch64/tls-relocs.s
RM/2010-11-30-reloc-movt.s
RM/arm-elf-symver.s
RM/basic-arm-instructions-v8.1a.s
RM/eh-compact-pr0.s
RM/eh-directive-handlerdata.s
RM/eh-directive-personality.s
RM/eh-directive-personalityindex.s
RM/eh-directive-section-multiple-func.s
RM/eh-directive-section.s
RM/eh-link.s
RM/elf-movt.s
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-reloc-condcall.s
RM/elf-thumbfunc-reloc.ll
RM/elf-thumbfunc-reloc.s
RM/thumb1-relax-adr.s
RM/thumb1-relax-bcc.s
RM/thumb1-relax-br.s
RM/thumb1-relax-ldrlit.s
RM/thumb2-bxj-v8.s
RM/thumb2-bxj.s
isassembler/AArch64/arm64-advsimd.txt
isassembler/AArch64/armv8.1a-lor.txt
isassembler/AArch64/armv8.1a-pan.txt
isassembler/AArch64/armv8.1a-rdma.txt
isassembler/AArch64/armv8.1a-vhe.txt
isassembler/ARM/armv8.1a.txt
isassembler/ARM/thumb-v8.1a.txt
isassembler/PowerPC/ppc64-encoding.txt
isassembler/PowerPC/vsx.txt
isassembler/SystemZ/insns.txt
isassembler/X86/x86-16.txt
LF/alias.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-escape.s
LF/cfi-offset.s
LF/cfi-register.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-restore.s
LF/cfi-same-value.s
LF/cfi-undefined.s
LF/cfi-window-save.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/common.s
LF/compression.s
LF/debug-line.s
LF/ifunc-reloc.s
LF/local-reloc.s
LF/merge.s
LF/pr19582.s
LF/relocation-386.s
LF/relocation-pc.s
LF/rename.s
LF/section-sym2.s
LF/section-unique-err1.s
LF/section-unique-err2.s
LF/section-unique-err3.s
LF/section-unique-err4.s
LF/section-unique.s
LF/symver-msvc.s
LF/symver.s
LF/tls.s
LF/weak-diff2.s
LF/weakref.s
exagon/inst_select.ll
achO/ARM/aliased-symbols.s
ips/elf-tls.s
ips/insn-directive.s
ips/micromips-alias.s
ips/mips-expansions-bad.s
ips/mips-expansions.s
ips/mips-jump-delay-slots.s
ips/mips1/valid.s
ips/mips2/valid.s
ips/mips3/valid.s
ips/mips32/valid.s
ips/mips32r2/valid.s
ips/mips32r3/valid.s
ips/mips32r5/valid.s
ips/mips32r6/valid.s
ips/mips4/valid.s
ips/mips5/valid.s
ips/mips64/valid.s
ips/mips64r2/valid.s
ips/mips64r3/valid.s
ips/mips64r5/valid.s
ips/mips64r6/valid.s
ips/set-defined-symbol.s
ips/sort-relocation-table.s
ips/xgot.s
owerPC/ppc-reloc.s
owerPC/ppc64-encoding.s
owerPC/tls-gd-obj.s
owerPC/tls-ie-obj.s
owerPC/tls-ld-obj.s
owerPC/vsx.s
600/ds-err.s
600/ds.s
600/mubuf.s
600/smrd.s
600/sop1-err.s
600/sop1.s
600/sop2.s
600/sopc.s
600/sopk.s
600/sopp.s
600/vop1.s
600/vop2-err.s
600/vop2.s
600/vop3.s
600/vopc.s
ystemZ/insn-bad-z196.s
ystemZ/insn-bad-zEC12.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
ystemZ/insn-good-zEC12.s
86/AlignedBundling/bundle-group-too-large-error.s
86/AlignedBundling/different-sections.s
86/AlignedBundling/labeloffset.s
86/AlignedBundling/long-nop-pad.s
86/AlignedBundling/nesting.s
86/AlignedBundling/pad-align-to-bundle-end.s
86/AlignedBundling/pad-bundle-groups.s
86/AlignedBundling/relax-at-bundle-end.s
86/AlignedBundling/relax-in-bundle-group.s
86/AlignedBundling/single-inst-bundling.s
86/expand-var.s
86/reloc-undef-global.s
86/stackmap-nops.ll
86/x86-16.s
86/x86-32.s
86/x86-64.s
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
Arch64/elf-globaladdress.ll
RM/arm11-hint-instr.s
RM/basic-arm-instructions-v8.1a.s
RM/coff-debugging-secrel.ll
RM/data-in-code.ll
RM/directive-arch-armv6k.s
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/thumb-diagnostics.s
smParser/ifeqs-diagnostics.s
smParser/ifnes.s
smParser/rename.s
OFF/global_ctors_dtors.ll
OFF/ir-to-imgrel.ll
OFF/linker-options.ll
OFF/tricky-names.ll
isassembler/ARM/armv8.1a.txt
isassembler/ARM/invalid-armv8.1a.txt
isassembler/ARM/invalid-thumbv8.1a.txt
isassembler/ARM/neont2.txt
isassembler/ARM/thumb-v8.1a.txt
isassembler/PowerPC/ppc64-encoding-bookII.txt
isassembler/PowerPC/ppc64-encoding-vmx.txt
isassembler/X86/avx-512.txt
LF/alias.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-version.ll
LF/entsize.ll
LF/gen-dwarf.s
LF/relocation-386.s
LF/relocation.s
LF/size.s
LF/weak-diff.s
achO/AArch64/cstexpr-gotpcrel.ll
achO/ARM/cstexpr-gotpcrel.ll
achO/cstexpr-gotpcrel-32.ll
achO/cstexpr-gotpcrel-64.ll
achO/tlv-bss.ll
achO/x86-data-in-code.ll
ips/elf-bigendian.ll
ips/mips-abi-bad.s
ips/mips1/valid.s
ips/mips2/valid.s
ips/mips3/valid.s
ips/mips32/valid.s
ips/mips32r2/valid.s
ips/mips32r3/valid.s
ips/mips32r5/valid.s
ips/mips32r6/valid.s
ips/mips4/valid.s
ips/mips5/valid.s
ips/mips64/valid.s
ips/mips64r2/valid.s
ips/mips64r3/valid.s
ips/mips64r5/valid.s
ips/mips64r6/valid.s
ips/module-directive-bad.s
ips/sym-offset.ll
owerPC/htm.s
owerPC/ppc64-encoding-bookII.s
owerPC/ppc64-encoding-vmx.s
86/cstexpr-gotpcrel.ll
86/expand-var.s
86/i386-darwin-frame-register.ll
86/intel-syntax-avx512.s
86/invalid-sleb.s
86/x86-64-avx512bw.s
86/x86-64-avx512bw_vl.s
86/x86-64-avx512f_vl.s
86/x86_64-avx-encoding.s
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Arch64/adrp-relocation.s
Arch64/arm64-elf-relocs.s
Arch64/arm64-tls-relocs.s
Arch64/dot-req.s
Arch64/inline-asm-modifiers.s
Arch64/tls-relocs.s
RM/Windows/invalid-relocation.s
RM/arm-elf-relocation-diagnostics.s
RM/arm-elf-relocations.s
RM/arm-load-store-multiple-deprecated.s
RM/arm-thumb-cpus.s
RM/basic-arm-instructions.s
RM/coff-debugging-secrel.ll
RM/cpu-test.s
RM/diagnostics.s
RM/directive-arch-iwmmxt.s
RM/directive-arch-iwmmxt2.s
RM/directive-cpu.s
RM/directive-eabi_attribute-diagnostics.s
RM/directive-eabi_attribute-overwrite.s
RM/directive-eabi_attribute.s
RM/directive-fpu-diagnostics.s
RM/dot-req.s
RM/ldr-pseudo-parse-errors.s
RM/move-banked-regs.s
RM/pr22395-2.s
RM/pr22395.s
RM/thumb-diagnostics.s
RM/thumb-load-store-multiple.s
RM/thumb2-diagnostics.s
RM/thumb2-dsp-diag.s
RM/v8_IT_manual.s
RM/virtexts-arm.s
RM/virtexts-thumb.s
smParser/directive_set.s
OFF/bss_section.ll
OFF/const-gv-with-rel-init.ll
OFF/diff.s
OFF/directive-section-characteristics.ll
OFF/global_ctors_dtors.ll
OFF/initialised-data.ll
OFF/linker-options.ll
OFF/section-passthru-flags.s
OFF/seh-section.s
OFF/weak-symbol.ll
isassembler/ARM/arm-tests.txt
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/invalid-virtexts.arm.txt
isassembler/ARM/move-banked-regs-arm.txt
isassembler/ARM/virtexts-arm.txt
isassembler/ARM/virtexts-thumb.txt
isassembler/Hexagon/alu32_alu.txt
isassembler/Hexagon/alu32_perm.txt
isassembler/Hexagon/alu32_pred.txt
isassembler/Hexagon/cr.txt
isassembler/Hexagon/j.txt
isassembler/Hexagon/jr.txt
isassembler/Hexagon/ld.txt
isassembler/Hexagon/lit.local.cfg
isassembler/Hexagon/memop.txt
isassembler/Hexagon/nv_j.txt
isassembler/Hexagon/nv_st.txt
isassembler/Hexagon/st.txt
isassembler/Hexagon/system_user.txt
isassembler/Hexagon/xtype_alu.txt
isassembler/Hexagon/xtype_bit.txt
isassembler/Hexagon/xtype_complex.txt
isassembler/Hexagon/xtype_fp.txt
isassembler/Hexagon/xtype_mpy.txt
isassembler/Hexagon/xtype_perm.txt
isassembler/Hexagon/xtype_pred.txt
isassembler/Hexagon/xtype_shift.txt
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
isassembler/Mips/mips1/valid-mips1-el.txt
isassembler/Mips/mips1/valid-mips1.txt
isassembler/Mips/mips1/valid-xfail.txt
isassembler/Mips/mips2/valid-mips2-el.txt
isassembler/Mips/mips2/valid-mips2.txt
isassembler/Mips/mips3/valid-mips3-el.txt
isassembler/Mips/mips3/valid-mips3.txt
isassembler/Mips/mips32/valid-mips32-el.txt
isassembler/Mips/mips32/valid-mips32.txt
isassembler/Mips/mips32/valid-xfail-mips32.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2/valid-mips32r2-le.txt
isassembler/Mips/mips32r2/valid-mips32r2.txt
isassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips32r3/valid-mips32r3-le.txt
isassembler/Mips/mips32r3/valid-mips32r3.txt
isassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
isassembler/Mips/mips32r5/valid-mips32r5-le.txt
isassembler/Mips/mips32r5/valid-mips32r5.txt
isassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
isassembler/Mips/mips32r6/valid-mips32r6-el.txt
isassembler/Mips/mips32r6/valid-mips32r6.txt
isassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
isassembler/Mips/mips4/valid-mips4-el.txt
isassembler/Mips/mips4/valid-mips4.txt
isassembler/Mips/mips4/valid-xfail-mips4.txt
isassembler/Mips/mips64/valid-mips64-el.txt
isassembler/Mips/mips64/valid-mips64-xfail.txt
isassembler/Mips/mips64/valid-mips64.txt
isassembler/Mips/mips64r2/valid-mips64r2-el.txt
isassembler/Mips/mips64r2/valid-mips64r2.txt
isassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
isassembler/Mips/mips64r3/valid-mips64r3-el.txt
isassembler/Mips/mips64r3/valid-mips64r3.txt
isassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
isassembler/Mips/mips64r5/valid-mips64r5-el.txt
isassembler/Mips/mips64r5/valid-mips64r5.txt
isassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
isassembler/Mips/mips64r6/valid-mips64r6-el.txt
isassembler/Mips/mips64r6/valid-mips64r6.txt
isassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
isassembler/PowerPC/ppc64-encoding-ext.txt
isassembler/PowerPC/ppc64-encoding-fp.txt
isassembler/PowerPC/ppc64-encoding-vmx.txt
isassembler/PowerPC/ppc64-encoding.txt
isassembler/PowerPC/qpx.txt
isassembler/PowerPC/vsx.txt
isassembler/X86/avx-512.txt
isassembler/X86/intel-syntax-32.txt
isassembler/X86/intel-syntax.txt
isassembler/X86/invalid-cmp-imm.txt
isassembler/X86/moffs.txt
isassembler/X86/prefixes.txt
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
isassembler/X86/x86-64.txt
LF/alias.s
LF/cfi-large-model.s
LF/cfi-version.ll
LF/common-error1.s
LF/common-error2.s
LF/relocation-386.s
LF/section-unique.s
LF/symver-msvc.s
LF/type.s
LF/uleb.s
exagon/inst_add.ll
exagon/inst_add64.ll
exagon/inst_and.ll
exagon/inst_and64.ll
exagon/inst_aslh.ll
exagon/inst_asrh.ll
exagon/inst_cmp_eq.ll
exagon/inst_cmp_eqi.ll
exagon/inst_cmp_gt.ll
exagon/inst_cmp_gti.ll
exagon/inst_cmp_lt.ll
exagon/inst_cmp_ugt.ll
exagon/inst_cmp_ugti.ll
exagon/inst_cmp_ult.ll
exagon/inst_or.ll
exagon/inst_or64.ll
exagon/inst_select.ll
exagon/inst_sub.ll
exagon/inst_sub64.ll
exagon/inst_sxtb.ll
exagon/inst_sxth.ll
exagon/inst_xor.ll
exagon/inst_xor64.ll
exagon/inst_zxtb.ll
exagon/inst_zxth.ll
achO/AArch64/cfstring.s
achO/AArch64/classrefs.s
achO/AArch64/darwin-ARM64-reloc.s
achO/AArch64/mergeable.s
achO/AArch64/reloc-crash.s
achO/AArch64/reloc-crash2.s
achO/ARM/static-movt-relocs.s
achO/darwin-x86_64-reloc.s
achO/linker-options.ll
achO/reloc.s
achO/x86_64-mergeable.s
achO/x86_64-symbols.s
ips/cpload.s
ips/cpsetup-bad.s
ips/cpsetup.s
ips/do_switch3.s
ips/elf_eflags.s
ips/elf_reginfo.s
ips/micromips-16-bit-instructions.s
ips/micromips-alu-instructions.s
ips/micromips-bad-branches.s
ips/micromips-branch-fixup.s
ips/micromips-branch-instructions.s
ips/micromips-branch16.s
ips/micromips-control-instructions.s
ips/micromips-diagnostic-fixup.s
ips/micromips-func-addr.s
ips/micromips-invalid.s
ips/micromips-jump-instructions.s
ips/micromips-loadstore-instructions.s
ips/mips-abi-bad.s
ips/mips-noat.s
ips/mips-reginfo-fp64.s
ips/mips32r2/valid-xfail.s
ips/mips32r2/valid.s
ips/mips32r3/abiflags.s
ips/mips32r3/invalid-mips64r2.s
ips/mips32r3/invalid.s
ips/mips32r3/valid-xfail.s
ips/mips32r3/valid.s
ips/mips32r5/abiflags.s
ips/mips32r5/invalid-mips64r2.s
ips/mips32r5/invalid.s
ips/mips32r5/valid-xfail.s
ips/mips32r5/valid.s
ips/mips4/invalid-mips64r2.s
ips/mips4/valid-xfail.s
ips/mips4/valid.s
ips/mips5/invalid-mips64r2.s
ips/mips5/valid-xfail.s
ips/mips5/valid.s
ips/mips64-register-names-n32-n64.s
ips/mips64-register-names-o32.s
ips/mips64/invalid-mips64r2.s
ips/mips64/valid-xfail.s
ips/mips64/valid.s
ips/mips64extins.ll
ips/mips64r2/abi-bad.s
ips/mips64r2/valid-xfail.s
ips/mips64r3/abi-bad.s
ips/mips64r3/abiflags.s
ips/mips64r3/invalid.s
ips/mips64r3/valid-xfail.s
ips/mips64r3/valid.s
ips/mips64r5/abi-bad.s
ips/mips64r5/abiflags.s
ips/mips64r5/invalid.s
ips/mips64r5/valid-xfail.s
ips/mips64r5/valid.s
ips/nabi-regs.s
ips/nooddspreg-cmdarg.s
ips/nooddspreg.s
ips/octeon-instructions.s
ips/oddspreg.s
ips/set-arch.s
ips/set-at-directive-explicit-at.s
ips/set-at-directive.s
ips/set-at-noat-bad-syntax.s
ips/set-mips-directives-bad.s
ips/set-mips-directives.s
owerPC/ppc-reloc.s
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding-fp.s
owerPC/ppc64-encoding-vmx.s
owerPC/ppc64-encoding.s
owerPC/ppc64-localentry.s
owerPC/qpx.s
owerPC/vsx.s
600/sopp.s
ystemZ/fixups.s
86/avx512-encodings.s
86/avx512bw-encoding.s
86/avx512vl-encoding.s
86/compact-unwind.s
86/cstexpr-gotpcrel.ll
86/i386-darwin-frame-register.ll
86/intel-syntax-unsized-memory.s
86/intel-syntax.s
86/shuffle-comments.s
86/validate-inst-att.s
86/validate-inst-intel.s
86/x86-32-avx.s
86/x86-32-coverage.s
86/x86-32.s
86/x86-64-avx512bw.s
86/x86-64-avx512bw_vl.s
86/x86-64-avx512f_vl.s
86/x86_64-avx-encoding.s
86/x86_64-encoding.s
86/x86_64-xop-encoding.s
86/x86_errors.s
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Arch64/arm64-be-datalayout.s
Arch64/arm64-diags.s
Arch64/arm64-system-encoding.s
Arch64/basic-a64-diagnostics.s
Arch64/basic-a64-instructions.s
Arch64/elf_osabi_flags.s
Arch64/inst-directive-diagnostic.s
Arch64/inst-directive.s
Arch64/ldr-pseudo-diagnostics.s
Arch64/ldr-pseudo.s
Arch64/single-slash.s
RM/arm_instructions.s
RM/coff-debugging-secrel.ll
RM/coff-file.s
RM/coproc-diag.s
RM/cps.s
RM/d16.s
RM/diagnostics.s
RM/directive-arch_extension-crc.s
RM/directive-arch_extension-fp.s
RM/directive-arch_extension-idiv.s
RM/directive-arch_extension-mode-switch.s
RM/directive-arch_extension-simd.s
RM/directive-arch_extension-toggle.s
RM/directive-eabi_attribute-2.s
RM/directive-eabi_attribute.s
RM/directive-fpu-instrs.s
RM/directive-thumb_func.s
RM/directive-unsupported.s
RM/dwarf-asm-multiple-sections-dwarf-2.s
RM/dwarf-asm-multiple-sections.s
RM/ldr-pseudo-darwin.s
RM/ltorg-darwin.s
RM/move-banked-regs.s
RM/neon-bitwise-encoding.s
RM/neon-mov-vfp.s
RM/symbol-variants.s
RM/thumb-diagnostics.s
RM/thumb-not-mclass.s
RM/thumb2-bxj.s
RM/thumb2-exception-return-mclass.s
RM/thumb2-ldrb-ldrh.s
RM/thumb2-ldrexd-strexd.s
RM/thumb2-mclass.s
RM/thumb_rewrites.s
RM/thumbv7em.s
RM/vfp4.s
RM/vorr-vbic-illegal-cases.s
smParser/comments-x86-darwin.s
smParser/directive-warning.s
smParser/macro-exitm.s
smParser/macros-darwin-vararg.s
OFF/alias.s
OFF/basic-coff-64.s
OFF/basic-coff.s
OFF/bigobj.py
OFF/bss_section.ll
OFF/comm-align.s
OFF/comm.ll
OFF/comm.s
OFF/const-gv-with-rel-init.ll
OFF/feat00.s
OFF/file.s
OFF/ir-to-imgrel.ll
OFF/linker-options.ll
OFF/lset0.s
OFF/secidx.s
OFF/section-invalid-flags.s
OFF/section-name-encoding.s
OFF/section-passthru-flags.s
OFF/seh-linkonce.s
OFF/simple-fixups.s
OFF/symbol-fragment-offset-64.s
OFF/symbol-fragment-offset.s
OFF/weak.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/d16.txt
isassembler/ARM/invalid-thumb-MSR-MClass.txt
isassembler/ARM/move-banked-regs-arm.txt
isassembler/ARM/move-banked-regs-thumb.txt
isassembler/ARM/thumb-MSR-MClass.txt
isassembler/ARM/thumb-tests.txt
isassembler/ARM/thumb2-preloads.txt
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
isassembler/Mips/mips2.txt
isassembler/Mips/mips32.txt
isassembler/Mips/mips64.txt
isassembler/PowerPC/ppc64-encoding-4xx.txt
isassembler/PowerPC/ppc64-encoding-6xx.txt
isassembler/PowerPC/ppc64-encoding-bookII.txt
isassembler/PowerPC/ppc64-encoding-bookIII.txt
isassembler/PowerPC/ppc64-encoding-e500.txt
isassembler/PowerPC/ppc64-encoding-ext.txt
isassembler/PowerPC/ppc64-encoding.txt
isassembler/X86/avx-512.txt
isassembler/X86/x86-32.txt
LF/cfi-version.ll
LF/comdat.s
LF/reloc-same-name-section.s
LF/section-sym-err.s
LF/section-sym.s
LF/section-sym2.s
exagon/basic.ll
exagon/inst_add.ll
exagon/inst_and.ll
exagon/inst_or.ll
exagon/inst_sub.ll
exagon/inst_xor.ll
exagon/lit.local.cfg
achO/ARM/aliased-symbols.s
achO/ARM/darwin-ARM-reloc.s
achO/ARM/ios-version-min-load-command.s
achO/absolute.s
achO/absolutize.s
achO/bad-darwin-x86_64-reloc-expr1.s
achO/bad-darwin-x86_64-reloc-expr2.s
achO/comm-1.s
achO/darwin-complex-difference.s
achO/darwin-x86_64-diff-reloc-assign-2.s
achO/darwin-x86_64-diff-relocs.s
achO/darwin-x86_64-reloc.s
achO/eh-frame-reloc.s
achO/empty-dwarf-lines.s
achO/file.s
achO/gen-dwarf.s
achO/indirect-symbols.s
achO/lcomm-attributes.s
achO/osx-version-min-load-command.s
achO/reloc.s
achO/section-align-2.s
achO/string-table.s
achO/symbol-diff.s
achO/symbol-flags.s
achO/symbol-indirect.s
achO/symbols-1.s
achO/tbss.s
achO/tls.s
achO/tlv-reloc.s
achO/variable-exprs.s
achO/x86_32-symbols.s
achO/x86_64-symbols.s
achO/zerofill-3.s
ips/cpload-bad.s
ips/cpload.s
ips/elf-objdump.s
ips/elf_eflags.s
ips/elf_eflags_abicalls.s
ips/elf_eflags_micromips.s
ips/elf_eflags_mips16.s
ips/elf_eflags_nan2008.s
ips/elf_eflags_nanlegacy.s
ips/elf_eflags_noreorder.s
ips/elf_eflags_pic0.s
ips/elf_eflags_pic2.s
ips/elf_reginfo.s
ips/micromips-16-bit-instructions.s
ips/micromips-branch-instructions.s
ips/micromips-control-instructions.s
ips/micromips-fpu-instructions.s
ips/micromips-invalid.s
ips/micromips-jump-instructions.s
ips/micromips-label-test-sections.s
ips/micromips-label-test.s
ips/micromips-loadstore-instructions.s
ips/mips-expansions-bad.s
ips/mips-expansions.s
ips/mips-hwr-register-names.s
ips/mips-jump-delay-slots.s
ips/mips-noat.s
ips/mips-pdr-bad.s
ips/mips-pdr.s
ips/mips-reginfo-fp32.s
ips/mips-reginfo-fp64.s
ips/mips1/invalid-mips2.s
ips/mips1/invalid-mips3.s
ips/mips1/invalid-mips32r2.s
ips/mips1/invalid-mips4-wrong-error.s
ips/mips1/invalid-mips5-wrong-error.s
ips/mips1/valid.s
ips/mips2/invalid-mips3.s
ips/mips2/invalid-mips32r2.s
ips/mips2/invalid-mips4-wrong-error.s
ips/mips2/invalid-mips5-wrong-error.s
ips/mips2/valid.s
ips/mips3/invalid-mips32r2.s
ips/mips3/invalid-mips4-wrong-error.s
ips/mips3/invalid-mips5-wrong-error.s
ips/mips3/valid.s
ips/mips32/abiflags.s
ips/mips32/invalid-mips32r2.s
ips/mips32/valid.s
ips/mips32r2/abiflags.s
ips/mips32r2/valid.s
ips/mips32r6/invalid-mips1-wrong-error.s
ips/mips32r6/invalid-mips1.s
ips/mips32r6/invalid-mips2-wrong-error.s
ips/mips32r6/invalid-mips2.s
ips/mips32r6/invalid-mips32-wrong-error.s
ips/mips32r6/invalid-mips32.s
ips/mips32r6/invalid-mips4-wrong-error.s
ips/mips32r6/invalid-mips4.s
ips/mips32r6/invalid-mips5-wrong-error.s
ips/mips32r6/valid.s
ips/mips4/invalid-mips32r2.s
ips/mips4/invalid-mips5-wrong-error.s
ips/mips4/valid.s
ips/mips5/invalid-mips32r2.s
ips/mips5/valid.s
ips/mips64-register-names-n32-n64.s
ips/mips64/abiflags.s
ips/mips64/invalid-mips32r2.s
ips/mips64/valid.s
ips/mips64r2/abiflags.s
ips/mips64r2/valid.s
ips/mips64r6/invalid-mips1-wrong-error.s
ips/mips64r6/invalid-mips1.s
ips/mips64r6/invalid-mips2.s
ips/mips64r6/invalid-mips3-wrong-error.s
ips/mips64r6/invalid-mips32-wrong-error.s
ips/mips64r6/invalid-mips4-wrong-error.s
ips/mips64r6/invalid-mips4.s
ips/mips64r6/invalid-mips5-wrong-error.s
ips/mips64r6/valid.s
ips/mips_abi_flags_xx.s
ips/mips_abi_flags_xx_set.s
ips/mips_directives_bad.s
ips/msa/abiflags.s
ips/msa/set-msa-directive-bad.s
ips/msa/set-msa-directive.s
ips/nacl-mask.s
ips/nooddspreg-cmdarg.s
ips/nooddspreg.s
ips/octeon-instructions.s
ips/oddspreg.s
ips/set-arch.s
ips/set-at-directive-explicit-at.s
ips/set-mips-directives-bad.s
ips/set-mips-directives.s
ips/set-mips0-directive.s
ips/set-mips16-directive.s
ips/set-nodsp.s
ips/set-push-pop-directives-bad.s
ips/set-push-pop-directives.s
ips/unaligned-nops.s
owerPC/lcomm.s
owerPC/ppc-reloc.s
owerPC/ppc32-ba.s
owerPC/ppc64-abiversion.s
owerPC/ppc64-encoding-4xx.s
owerPC/ppc64-encoding-6xx.s
owerPC/ppc64-encoding-bookII.s
owerPC/ppc64-encoding-bookIII.s
owerPC/ppc64-encoding-e500.s
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding-spe.s
owerPC/ppc64-encoding.s
owerPC/ppc64-fixup-apply.s
owerPC/ppc64-fixups.s
owerPC/ppc64-localentry-error1.s
owerPC/ppc64-localentry-error2.s
owerPC/ppc64-localentry.s
owerPC/vsx.s
600/lit.local.cfg
600/sopp.s
ystemZ/lit.local.cfg
86/AlignedBundling/labeloffset.s
86/AlignedBundling/long-nop-pad.s
86/AlignedBundling/nesting.s
86/avx512-encodings.s
86/intel-syntax-2.s
86/intel-syntax-ambiguous.s
86/intel-syntax-error.s
86/intel-syntax-ptr-sized.s
86/intel-syntax.s
86/macho-uleb.s
86/reloc-macho.s
86/sgx-encoding.s
86/stackmap-nops.ll
86/x86-32-coverage.s
86/x86-32-ms-inline-asm.s
86/x86-64-avx512bw.s
86/x86-64-avx512bw_vl.s
86/x86-64-avx512dq.s
86/x86-64-avx512dq_vl.s
86/x86-64-avx512f_vl.s
86/x86-itanium.ll
86/x86-windows-itanium-libcalls.ll
86/x86_errors.s
86/x86_operands.s
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
Arch64/alias-logicalimm.s
Arch64/arm64-leaf-compact-unwind.s
Arch64/arm64-system-encoding.s
Arch64/basic-a64-diagnostics.s
Arch64/basic-a64-instructions.s
Arch64/dot-req-case-insensitive.s
Arch64/dot-req-diagnostics.s
Arch64/dot-req.s
Arch64/ldr-pseudo-obj-errors.s
Arch64/ldr-pseudo.s
Arch64/lit.local.cfg
RM/AlignedBundling/lit.local.cfg
RM/Windows/multiple-text-sections.s
RM/Windows/text-attributes.s
RM/diagnostics.s
RM/dwarf-asm-multiple-sections.s
RM/dwarf-asm-no-code.s
RM/dwarf-asm-nonstandard-section.s
RM/dwarf-asm-single-section.s
RM/gas-compl-copr-reg.s
RM/lit.local.cfg
RM/macho-relocs-with-addend.s
RM/thumb-types.s
smParser/cfi-invalid-startproc.s
smParser/conditional_asm.s
smParser/directive_file.s
smParser/directive_line.s
smParser/directive_loc.s
smParser/directive_seh.s
smParser/if-diagnostics.s
smParser/lit.local.cfg
smParser/vararg.s
OFF/alias.s
OFF/basic-coff-64.s
OFF/basic-coff.s
OFF/early-dce.s
OFF/global_ctors_dtors.ll
OFF/linker-options.ll
OFF/linkonce-invalid.s
OFF/linkonce.s
OFF/lit.local.cfg
OFF/lset0.s
OFF/section-comdat-conflict.s
OFF/section-comdat-conflict2.s
OFF/section-comdat.s
OFF/section-name-encoding.s
OFF/seh-stackalloc-zero.s
OFF/seh.s
OFF/symbol-fragment-offset-64.s
OFF/symbol-fragment-offset.s
isassembler/AArch64/basic-a64-instructions.txt
isassembler/AArch64/lit.local.cfg
isassembler/ARM/hex-immediates.txt
isassembler/ARM/lit.local.cfg
isassembler/Mips/lit.local.cfg
isassembler/Mips/mips32r6.txt
isassembler/Mips/mips64r6.txt
isassembler/PowerPC/lit.local.cfg
isassembler/Sparc/lit.local.cfg
isassembler/SystemZ/insns.txt
isassembler/SystemZ/lit.local.cfg
isassembler/X86/avx-512.txt
isassembler/X86/hex-immediates.txt
isassembler/X86/lit.local.cfg
isassembler/X86/moffs.txt
isassembler/XCore/lit.local.cfg
LF/ARM/bss-non-zero-value.s
LF/ARM/gnu-type-hash-diagnostics.s
LF/ARM/gnu-type-hash.s
LF/ARM/lit.local.cfg
LF/cfi-adjust-cfa-offset.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-escape.s
LF/cfi-offset.s
LF/cfi-register.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-restore.s
LF/cfi-same-value.s
LF/cfi-sections.s
LF/cfi-signal-frame.s
LF/cfi-undefined.s
LF/cfi-version.ll
LF/cfi-window-save.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/gnu-type-diagnostics.s
LF/gnu-type.s
LF/lit.local.cfg
LF/no-reloc.s
LF/pr19430.s
achO/AArch64/lit.local.cfg
achO/ARM/aliased-symbols.s
achO/ARM/lit.local.cfg
achO/eh-frame-reloc.s
achO/eh-symbols.s
achO/eh_symbol.s
achO/lit.local.cfg
achO/pr19185.s
achO/variable-exprs.s
ips/cpsetup-bad.s
ips/eh-frame.s
ips/elf_eflags.s
ips/lit.local.cfg
ips/mips-abi-bad.s
ips/mips-data-directives.s
ips/mips-expansions-bad.s
ips/mips-expansions.s
ips/mips-noat.s
ips/mips1/invalid-mips2.s
ips/mips1/invalid-mips32.s
ips/mips1/invalid-mips4.s
ips/mips1/invalid-mips5.s
ips/mips1/valid.s
ips/mips2/invalid-mips3-wrong-error.s
ips/mips2/invalid-mips3.s
ips/mips2/invalid-mips32.s
ips/mips2/invalid-mips32r2.s
ips/mips2/invalid-mips4.s
ips/mips2/invalid-mips5.s
ips/mips2/valid.s
ips/mips3/invalid-mips32.s
ips/mips3/invalid-mips4.s
ips/mips3/invalid-mips5.s
ips/mips3/valid.s
ips/mips32/abiflags.s
ips/mips32/valid.s
ips/mips32r2/abiflags.s
ips/mips32r2/invalid.s
ips/mips32r2/valid.s
ips/mips32r6/invalid-mips1-wrong-error.s
ips/mips32r6/invalid-mips1.s
ips/mips32r6/invalid-mips2.s
ips/mips32r6/invalid-mips32-wrong-error.s
ips/mips32r6/invalid-mips32.s
ips/mips32r6/invalid-mips32r2.s
ips/mips32r6/invalid-mips4-wrong-error.s
ips/mips32r6/invalid-mips4.s
ips/mips32r6/invalid-mips5-wrong-error.s
ips/mips32r6/invalid-mips5.s
ips/mips32r6/invalid.s
ips/mips32r6/relocations.s
ips/mips32r6/valid.s
ips/mips4/invalid-mips32.s
ips/mips4/valid.s
ips/mips5/invalid-mips32.s
ips/mips5/invalid-mips64.s
ips/mips5/valid.s
ips/mips64-expansions.s
ips/mips64/abiflags.s
ips/mips64/valid.s
ips/mips64r2/abi-bad.s
ips/mips64r2/abiflags.s
ips/mips64r2/invalid.s
ips/mips64r2/valid.s
ips/mips64r6/invalid-mips1-wrong-error.s
ips/mips64r6/invalid-mips1.s
ips/mips64r6/invalid-mips2.s
ips/mips64r6/invalid-mips3.s
ips/mips64r6/invalid-mips32-wrong-error.s
ips/mips64r6/invalid-mips4-wrong-error.s
ips/mips64r6/invalid-mips4.s
ips/mips64r6/invalid-mips5-wrong-error.s
ips/mips64r6/invalid-mips5.s
ips/mips64r6/invalid-mips64.s
ips/mips64r6/invalid.s
ips/mips64r6/relocations.s
ips/mips64r6/valid.s
ips/mips_abi_flags_xx.s
ips/mips_abi_flags_xx_set.s
ips/msa/abiflags.s
ips/nacl-mask.s
ips/nooddspreg-cmdarg.s
ips/nooddspreg-error.s
ips/nooddspreg.s
ips/oddspreg.s
owerPC/lit.local.cfg
owerPC/ppc64-initial-cfa.s
parc/lit.local.cfg
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
ystemZ/lit.local.cfg
86/AlignedBundling/lit.local.cfg
86/avx512-encodings.s
86/intel-syntax.s
86/lit.local.cfg
86/no-elf-compact-unwind.s
86/x86_long_nop.s
86/x86_nop.s
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Arch64/arm64-adr.s
Arch64/arm64-advsimd.s
Arch64/arm64-aliases.s
Arch64/arm64-arithmetic-encoding.s
Arch64/arm64-arm64-fixup.s
Arch64/arm64-basic-a64-instructions.s
Arch64/arm64-be-datalayout.s
Arch64/arm64-bitfield-encoding.s
Arch64/arm64-branch-encoding.s
Arch64/arm64-condbr-without-dots.s
Arch64/arm64-crypto.s
Arch64/arm64-diagno-predicate.s
Arch64/arm64-diags.s
Arch64/arm64-directive_loh.s
Arch64/arm64-elf-reloc-condbr.s
Arch64/arm64-elf-relocs.s
Arch64/arm64-fp-encoding.s
Arch64/arm64-large-relocs.s
Arch64/arm64-leaf-compact-unwind.s
Arch64/arm64-logical-encoding.s
Arch64/arm64-mapping-across-sections.s
Arch64/arm64-mapping-within-section.s
Arch64/arm64-memory.s
Arch64/arm64-nv-cond.s
Arch64/arm64-optional-hash.s
Arch64/arm64-separator.s
Arch64/arm64-simd-ldst.s
Arch64/arm64-small-data-fixups.s
Arch64/arm64-spsel-sysreg.s
Arch64/arm64-system-encoding.s
Arch64/arm64-target-specific-sysreg.s
Arch64/arm64-tls-modifiers-darwin.s
Arch64/arm64-tls-relocs.s
Arch64/arm64-v128_lo-diagnostics.s
Arch64/arm64-variable-exprs.s
Arch64/arm64-vector-lists.s
Arch64/arm64-verbose-vector-case.s
Arch64/basic-a64-diagnostics.s
Arch64/basic-a64-instructions.s
Arch64/elf-globaladdress.ll
Arch64/elf-reloc-addend.s
Arch64/elf-reloc-condbr.s
Arch64/gicv3-regs.s
Arch64/lit.local.cfg
Arch64/neon-2velem.s
Arch64/neon-3vdiff.s
Arch64/neon-across.s
Arch64/neon-compare-instructions.s
Arch64/neon-crypto.s
Arch64/neon-diagnostics.s
Arch64/neon-extract.s
Arch64/neon-mov.s
Arch64/neon-perm.s
Arch64/neon-scalar-compare.s
Arch64/neon-scalar-dup.s
Arch64/neon-simd-copy.s
Arch64/neon-simd-ldst-multi-elem.s
Arch64/neon-simd-ldst-one-elem.s
Arch64/neon-simd-misc.s
Arch64/neon-simd-post-ldst-multi-elem.s
Arch64/neon-tbl.s
Arch64/noneon-diagnostics.s
Arch64/optional-hash.s
Arch64/tls-relocs.s
Arch64/trace-regs.s
RM/Windows/mov32t-range.s
RM/arm-thumb-cpus-default.s
RM/arm-thumb-cpus.s
RM/arm_fixups.s
RM/basic-thumb2-instructions.s
RM/big-endian-arm-fixup.s
RM/big-endian-thumb-fixup.s
RM/big-endian-thumb2-fixup.s
RM/coff-debugging-secrel.ll
RM/coff-file.s
RM/coff-function-type-info.ll
RM/coff-relocations.s
RM/complex-operands.s
RM/diagnostics.s
RM/dwarf-cfi-initial-state.s
RM/eh-directive-save-diagnoatics.s
RM/eh-directive-save-diagnostics.s
RM/elf-thumbfunc-reloc.s
RM/elf-thumbfunc.s
RM/ldrd-strd-gnu-arm-bad-imm.s
RM/ldrd-strd-gnu-arm.s
RM/ldrd-strd-gnu-thumb-bad-regs.s
RM/ldrd-strd-gnu-thumb.s
RM/neon-vld-encoding.s
RM/neon-vld-vst-align.s
RM/pool.s
RM/symbol-variants.s
RM/thumb2-diagnostics.s
RM/thumb2-strd.s
RM/thumb2be-b.w-encoding.s
RM/thumb2be-beq.w-encoding.s
RM/thumb2be-movt-encoding.s
RM/thumb2be-movw-encoding.s
RM/thumb_set.s
RM/udf-arm-diagnostics.s
RM/udf-arm.s
RM/udf-thumb-2-diagnostics.s
RM/udf-thumb-2.s
RM/udf-thumb-diagnostics.s
RM/udf-thumb.s
RM/vmov-vmvn-byte-replicate.s
RM/vmov-vmvn-illegal-cases.s
RM/vorr-vbic-illegal-cases.s
RM64/advsimd.s
RM64/aliases.s
RM64/arithmetic-encoding.s
RM64/arm64-fixup.s
RM64/basic-a64-instructions.s
RM64/bitfield-encoding.s
RM64/branch-encoding.s
RM64/crypto.s
RM64/diags.s
RM64/directive_loh.s
RM64/elf-relocs.s
RM64/fp-encoding.s
RM64/large-relocs.s
RM64/lit.local.cfg
RM64/logical-encoding.s
RM64/mapping-across-sections.s
RM64/mapping-within-section.s
RM64/memory.s
RM64/separator.s
RM64/simd-ldst.s
RM64/small-data-fixups.s
RM64/system-encoding.s
RM64/tls-modifiers-darwin.s
RM64/tls-relocs.s
RM64/variable-exprs.s
smParser/cfi-invalid-startproc.s
smParser/directive_seh.s
smParser/invalid-input-assertion.s
smParser/macros-darwin-vararg.s
smParser/vararg-default-value.s
smParser/vararg.s
OFF/alias.s
OFF/comm.ll
OFF/comm.s
OFF/directive-section-characteristics.ll
OFF/file.s
OFF/global_ctors_dtors.ll
OFF/initialised-data.ll
OFF/invalid-def.s
OFF/invalid-endef.s
OFF/invalid-scl-range.s
OFF/invalid-scl.s
OFF/invalid-type-range.s
OFF/invalid-type.s
OFF/offset.s
OFF/symbol-alias.s
OFF/weak-symbol.ll
isassembler/AArch64/a64-ignored-fields.txt
isassembler/AArch64/arm64-advsimd.txt
isassembler/AArch64/arm64-arithmetic.txt
isassembler/AArch64/arm64-basic-a64-undefined.txt
isassembler/AArch64/arm64-bitfield.txt
isassembler/AArch64/arm64-branch.txt
isassembler/AArch64/arm64-canonical-form.txt
isassembler/AArch64/arm64-crc32.txt
isassembler/AArch64/arm64-crypto.txt
isassembler/AArch64/arm64-invalid-logical.txt
isassembler/AArch64/arm64-logical.txt
isassembler/AArch64/arm64-memory.txt
isassembler/AArch64/arm64-non-apple-fmov.txt
isassembler/AArch64/arm64-scalar-fp.txt
isassembler/AArch64/arm64-system.txt
isassembler/AArch64/basic-a64-instructions.txt
isassembler/AArch64/basic-a64-undefined.txt
isassembler/AArch64/basic-a64-unpredictable.txt
isassembler/AArch64/gicv3-regs.txt
isassembler/AArch64/ldp-offset-predictable.txt
isassembler/AArch64/ldp-postind.predictable.txt
isassembler/AArch64/ldp-preind.predictable.txt
isassembler/AArch64/lit.local.cfg
isassembler/AArch64/neon-instructions.txt
isassembler/AArch64/trace-regs.txt
isassembler/ARM/invalid-thumbv7.txt
isassembler/ARM64/advsimd.txt
isassembler/ARM64/arithmetic.txt
isassembler/ARM64/bitfield.txt
isassembler/ARM64/branch.txt
isassembler/ARM64/crc32.txt
isassembler/ARM64/crypto.txt
isassembler/ARM64/invalid-logical.txt
isassembler/ARM64/lit.local.cfg
isassembler/ARM64/logical.txt
isassembler/ARM64/memory.txt
isassembler/ARM64/scalar-fp.txt
isassembler/ARM64/system.txt
isassembler/Mips/mips32r6.txt
isassembler/Mips/mips64r6.txt
isassembler/Mips/msa/test_2r.txt
isassembler/Mips/msa/test_2r_msa64.txt
isassembler/Mips/msa/test_2rf.txt
isassembler/Mips/msa/test_3r.txt
isassembler/Mips/msa/test_3rf.txt
isassembler/Mips/msa/test_bit.txt
isassembler/Mips/msa/test_ctrlregs.txt
isassembler/Mips/msa/test_dlsa.txt
isassembler/Mips/msa/test_elm.txt
isassembler/Mips/msa/test_elm_insert.txt
isassembler/Mips/msa/test_elm_insert_msa64.txt
isassembler/Mips/msa/test_elm_insve.txt
isassembler/Mips/msa/test_elm_msa64.txt
isassembler/Mips/msa/test_i10.txt
isassembler/Mips/msa/test_i5.txt
isassembler/Mips/msa/test_i8.txt
isassembler/Mips/msa/test_lsa.txt
isassembler/Mips/msa/test_mi10.txt
isassembler/Mips/msa/test_vec.txt
isassembler/Sparc/sparc-fp.txt
isassembler/X86/prefixes.txt
isassembler/X86/x86-32.txt
LF/comdat.s
LF/common.s
LF/comp-dir.s
LF/compression.s
LF/file-double.s
LF/gen-dwarf.s
LF/lcomm.s
LF/many-sections-2.s
LF/noexec.s
LF/offset.s
LF/pic-diff.s
LF/pr9292.s
LF/relocation-386.s
LF/relocation.s
LF/set.s
LF/strtab-suffix-opt.s
LF/subtraction-error.s
LF/symref.s
LF/symver.s
LF/tls-i386.s
LF/tls.s
LF/type.s
LF/undef.s
LF/weakref.s
achO/AArch64/darwin-ARM64-local-label-diff.s
achO/AArch64/darwin-ARM64-reloc.s
achO/AArch64/lit.local.cfg
achO/ARM/bad-darwin-directives.s
achO/ARM64/darwin-ARM64-local-label-diff.s
achO/ARM64/darwin-ARM64-reloc.s
achO/ARM64/lit.local.cfg
achO/bad-darwin-x86_64-reloc-expr.s
achO/debug_frame.s
achO/temp-labels.s
ips/cpload-bad.s
ips/cpload.s
ips/cpsetup.s
ips/elf-N64.s
ips/elf-gprel-32-64.s
ips/elf_eflags.s
ips/elf_eflags_nan2008.s
ips/elf_eflags_nanlegacy.s
ips/llvm-mc-fixup-endianness.s
ips/micromips-control-instructions.s
ips/micromips-el-fixup-data.s
ips/mips-control-instructions.s
ips/mips1/invalid-mips2-wrong-error.s
ips/mips1/invalid-mips2.s
ips/mips1/invalid-mips3-wrong-error.s
ips/mips1/invalid-mips3.s
ips/mips1/invalid-mips4-wrong-error.s
ips/mips1/invalid-mips4.s
ips/mips1/invalid-mips5-wrong-error.s
ips/mips1/invalid-mips5.s
ips/mips1/valid-xfail.s
ips/mips1/valid.s
ips/mips2/invalid-mips3-wrong-error.s
ips/mips2/invalid-mips3.s
ips/mips2/invalid-mips32.s
ips/mips2/invalid-mips32r2-xfail.s
ips/mips2/invalid-mips32r2.s
ips/mips2/invalid-mips4-wrong-error.s
ips/mips2/invalid-mips4.s
ips/mips2/invalid-mips5-wrong-error.s
ips/mips2/invalid-mips5.s
ips/mips2/valid-xfail.s
ips/mips2/valid.s
ips/mips3/invalid-mips4.s
ips/mips3/invalid-mips5-wrong-error.s
ips/mips3/invalid-mips5.s
ips/mips3/valid-xfail.s
ips/mips3/valid.s
ips/mips32/invalid-mips32r2-xfail.s
ips/mips32/invalid-mips32r2.s
ips/mips32/invalid-mips64.s
ips/mips32/valid-xfail.s
ips/mips32/valid.s
ips/mips32r2/invalid-mips64r2.s
ips/mips32r2/valid-xfail.s
ips/mips32r2/valid.s
ips/mips32r6/invalid-mips1-wrong-error.s
ips/mips32r6/invalid-mips1.s
ips/mips32r6/invalid-mips2-wrong-error.s
ips/mips32r6/invalid-mips2.s
ips/mips32r6/invalid-mips32-wrong-error.s
ips/mips32r6/relocations.s
ips/mips32r6/valid-xfail.s
ips/mips32r6/valid.s
ips/mips4/invalid-mips5-wrong-error.s
ips/mips4/invalid-mips5.s
ips/mips4/invalid-mips64-xfail.s
ips/mips4/invalid-mips64.s
ips/mips4/invalid-mips64r2-xfail.s
ips/mips4/invalid-mips64r2.s
ips/mips4/valid-xfail.s
ips/mips4/valid.s
ips/mips5/invalid-mips64.s
ips/mips5/invalid-mips64r2-xfail.s
ips/mips5/invalid-mips64r2.s
ips/mips5/valid-xfail.s
ips/mips5/valid.s
ips/mips64/invalid-mips64r2-xfail.s
ips/mips64/invalid-mips64r2.s
ips/mips64/valid-xfail.s
ips/mips64/valid.s
ips/mips64r2/valid-xfail.s
ips/mips64r2/valid.s
ips/mips64r6/invalid-mips1-wrong-error.s
ips/mips64r6/invalid-mips1.s
ips/mips64r6/invalid-mips2.s
ips/mips64r6/invalid-mips3-wrong-error.s
ips/mips64r6/invalid-mips3.s
ips/mips64r6/invalid-mips5-wrong-error.s
ips/mips64r6/relocations.s
ips/mips64r6/valid-xfail.s
ips/mips64r6/valid.s
ips/mips_directives.s
ips/mips_gprel16.s
ips/msa/test_2r.s
ips/msa/test_2r_msa64.s
ips/msa/test_2rf.s
ips/msa/test_3r.s
ips/msa/test_3rf.s
ips/msa/test_bit.s
ips/msa/test_cbranch.s
ips/msa/test_ctrlregs.s
ips/msa/test_dlsa.s
ips/msa/test_elm.s
ips/msa/test_elm_insert.s
ips/msa/test_elm_insert_msa64.s
ips/msa/test_elm_insve.s
ips/msa/test_elm_msa64.s
ips/msa/test_i10.s
ips/msa/test_i5.s
ips/msa/test_i8.s
ips/msa/test_lsa.s
ips/msa/test_mi10.s
ips/msa/test_vec.s
ips/octeon-instructions.s
owerPC/ppc64-initial-cfa.s
parc/sparc-alu-instructions.s
parc/sparc-fp-instructions.s
86/avx512-encodings.s
86/x86-64.s
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Arch64/basic-a64-diagnostics.s
Arch64/basic-a64-instructions.s
Arch64/neon-compare-instructions.s
Arch64/neon-diagnostics.s
Arch64/neon-scalar-fp-compare.s
Arch64/neon-sxtl.s
Arch64/neon-uxtl.s
Arch64/optional-hash.s
RM/2013-03-18-Br-to-label-named-like-reg.s
RM/arm-elf-symver.s
RM/arm-ldrd.s
RM/arm-memory-instructions.s
RM/arm-qualifier-diagnostics.s
RM/arm_addrmode2.s
RM/arm_fixups.s
RM/arm_word_directive.s
RM/basic-arm-instructions.s
RM/basic-thumb-instructions.s
RM/basic-thumb2-instructions.s
RM/bkpt.s
RM/cmp-immediate-fixup-error.s
RM/cmp-immediate-fixup-error2.s
RM/cmp-immediate-fixup.s
RM/cmp-immediate-fixup2.s
RM/comment.s
RM/complex-operands.s
RM/data-in-code.ll
RM/directive-align.s
RM/directive-arch-armv2.s
RM/directive-arch-armv2a.s
RM/directive-arch-armv3.s
RM/directive-arch-armv3m.s
RM/directive-arch-armv4.s
RM/directive-arch-armv4t.s
RM/directive-arch-armv5.s
RM/directive-arch-armv5t.s
RM/directive-arch-armv5te.s
RM/directive-arch-armv6-m.s
RM/directive-arch-armv6.s
RM/directive-arch-armv6j.s
RM/directive-arch-armv6t2.s
RM/directive-arch-armv6z.s
RM/directive-arch-armv6zk.s
RM/directive-arch-armv7-a.s
RM/directive-arch-armv7-m.s
RM/directive-arch-armv7-r.s
RM/directive-arch-armv7.s
RM/directive-arch-armv7a.s
RM/directive-arch-armv7m.s
RM/directive-arch-armv7r.s
RM/directive-arch-armv8-a.s
RM/directive-arch-armv8a.s
RM/directive-arch-iwmmxt.s
RM/directive-arch-iwmmxt2.s
RM/directive-arch_extension-crc.s
RM/directive-arch_extension-crypto.s
RM/directive-arch_extension-fp.s
RM/directive-arch_extension-idiv.s
RM/directive-arch_extension-mp.s
RM/directive-arch_extension-sec.s
RM/directive-arch_extension-simd.s
RM/directive-eabi_attribute-2.s
RM/directive-eabi_attribute-diagnostics.s
RM/directive-eabi_attribute-overwrite.s
RM/directive-even.s
RM/directive-fpu-multiple.s
RM/directive-fpu-softvfp.s
RM/directive-literals.s
RM/directive-object_arch-2.s
RM/directive-object_arch-3.s
RM/directive-object_arch-diagnostics.s
RM/directive-object_arch.s
RM/directive-tlsdescseq-diagnostics.s
RM/directive-tlsdescseq.s
RM/directive-word-diagnostics.s
RM/dot-req-case-insensitive.s
RM/dwarf-cfi-initial-state.s
RM/eh-directive-cantunwind-diagnostics.s
RM/eh-directive-fnstart-diagnostics.s
RM/eh-directive-movsp-diagnostics.s
RM/eh-directive-movsp.s
RM/eh-directive-personalityindex-diagnostics.s
RM/eh-directive-personalityindex.s
RM/eh-directive-setfp.s
RM/eh-directive-unwind_raw-diagnostics.s
RM/eh-directive-unwind_raw.s
RM/elf-jump24-fixup.s
RM/elf-thumbfunc-reloc.ll
RM/fconst.s
RM/fixup-cpu-mode.s
RM/fp-const-errors.s
RM/inst-arm-suffixes.s
RM/inst-constant-required.s
RM/inst-directive-emit.s
RM/inst-directive.s
RM/inst-overflow.s
RM/inst-thumb-overflow-2.s
RM/inst-thumb-overflow.s
RM/inst-thumb-suffixes.s
RM/invalid-vector-index.s
RM/ldr-pseudo-darwin.s
RM/ldr-pseudo-obj-errors.s
RM/ldr-pseudo-parse-errors.s
RM/ldr-pseudo.s
RM/ldrd-strd-gnu-sp.s
RM/ltorg-darwin.s
RM/ltorg.s
RM/mul-v4.s
RM/neon-vld-encoding.s
RM/not-armv4.s
RM/pool.s
RM/simple-fp-encoding.s
RM/symbol-variants-errors.s
RM/symbol-variants.s
RM/target-expressions.s
RM/thumb-far-jump.s
RM/thumb-st_other.s
RM/thumb-types.s
RM/thumb2-cbn-to-next-inst.s
RM/thumb2-ldrd.s
RM/thumb2-mclass.s
RM/thumb_set-diagnostics.s
RM/thumb_set.s
RM/thumbv7m.s
RM/unwind-stack-diagnostics.s
RM/variant-diagnostics.s
RM/vfp-aliases-diagnostics.s
RM/vfp-aliases.s
RM/xscale-attributes.ll
RM64/advsimd.s
RM64/aliases.s
RM64/arithmetic-encoding.s
RM64/arm64-fixup.s
RM64/basic-a64-instructions.s
RM64/bitfield-encoding.s
RM64/branch-encoding.s
RM64/crypto.s
RM64/diags.s
RM64/directive_loh.s
RM64/elf-relocs.s
RM64/fp-encoding.s
RM64/large-relocs.s
RM64/lit.local.cfg
RM64/logical-encoding.s
RM64/mapping-across-sections.s
RM64/mapping-within-section.s
RM64/memory.s
RM64/separator.s
RM64/simd-ldst.s
RM64/small-data-fixups.s
RM64/system-encoding.s
RM64/tls-modifiers-darwin.s
RM64/tls-relocs.s
RM64/variable-exprs.s
smParser/conditional_asm.s
smParser/directive-err-diagnostics.s
smParser/directive-err.s
smParser/directive_end-2.s
smParser/directive_end.s
smParser/directive_fill.s
smParser/directive_loc.s
smParser/directive_rept-diagnostics.s
smParser/directive_rept.s
smParser/directive_values.s
smParser/dot-symbol-assignment-backwards.s
smParser/dot-symbol-assignment.s
smParser/dot-symbol-non-absolute.s
smParser/dot-symbol.s
smParser/exprs.s
smParser/ifc.s
smParser/ifeqs-diagnostics.s
smParser/ifeqs.s
smParser/macro-def-in-instantiation.s
smParser/macro-err1.s
smParser/macro-irp.s
smParser/macro-qualifier-diagnostics.s
smParser/macro-qualifier.s
smParser/macros-argument-parsing-diagnostics.s
smParser/macros-argument-parsing.s
smParser/macros-darwin.s
smParser/macros-gas.s
smParser/macros.s
OFF/bad-expr.s
OFF/bss.s
OFF/bss_section.ll
OFF/comm.s
OFF/feat00.s
OFF/ir-to-imgrel.ll
OFF/secidx-diagnostic.s
OFF/secidx.s
OFF/section-name-encoding.s
OFF/timestamp.s
OFF/tricky-names.ll
OFF/weak-symbol.ll
OFF/weak.s
isassembler/ARM/addrmode2-reencoding.txt
isassembler/ARM64/advsimd.txt
isassembler/ARM64/arithmetic.txt
isassembler/ARM64/bitfield.txt
isassembler/ARM64/branch.txt
isassembler/ARM64/crc32.txt
isassembler/ARM64/crypto.txt
isassembler/ARM64/invalid-logical.txt
isassembler/ARM64/lit.local.cfg
isassembler/ARM64/logical.txt
isassembler/ARM64/memory.txt
isassembler/ARM64/scalar-fp.txt
isassembler/ARM64/system.txt
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/PowerPC/lit.local.cfg
isassembler/PowerPC/ppc64-encoding-bookII.txt
isassembler/PowerPC/ppc64-encoding-bookIII.txt
isassembler/PowerPC/ppc64-encoding-ext.txt
isassembler/PowerPC/ppc64-encoding-fp.txt
isassembler/PowerPC/ppc64-encoding-vmx.txt
isassembler/PowerPC/ppc64-encoding.txt
isassembler/PowerPC/ppc64-operands.txt
isassembler/PowerPC/vsx.txt
isassembler/Sparc/lit.local.cfg
isassembler/Sparc/sparc-fp.txt
isassembler/Sparc/sparc-mem.txt
isassembler/Sparc/sparc.txt
isassembler/SystemZ/insns.txt
isassembler/X86/avx-512.txt
isassembler/X86/fp-stack.txt
isassembler/X86/missing-sib.txt
isassembler/X86/moffs.txt
isassembler/X86/padlock.txt
isassembler/X86/simple-tests.txt
isassembler/X86/x86-16.txt
isassembler/X86/x86-32.txt
isassembler/X86/x86-64.txt
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/bad-expr.s
LF/bad-expr2.s
LF/bad-expr3.s
LF/basic-elf-32.s
LF/cfi.s
LF/comdat.s
LF/common.s
LF/compression.s
LF/discriminator.s
LF/dot-symbol-assignment.s
LF/file-double.s
LF/file.s
LF/gen-dwarf.s
LF/ifunc-reloc.s
LF/local-reloc.s
LF/many-section.s
LF/many-sections-2.s
LF/many-sections.s
LF/merge.s
LF/nocompression.s
LF/offset.s
LF/pic-diff.s
LF/pr9292.s
LF/relocation-386.s
LF/relocation-pc.s
LF/relocation.s
LF/set.s
LF/symref.s
LF/tls-i386.s
LF/tls.s
LF/type-propagate.s
LF/type.s
LF/undef.s
LF/weak.s
LF/weakref-reloc.s
LF/weakref.s
achO/ARM/bad-darwin-ARM-reloc.s
achO/ARM/bad-darwin-directives.s
achO/ARM/ios-version-min-load-command.s
achO/ARM/version-min-diagnostics.s
achO/ARM/version-min.s
achO/ARM64/darwin-ARM64-local-label-diff.s
achO/ARM64/darwin-ARM64-reloc.s
achO/ARM64/lit.local.cfg
achO/bss.s
achO/eh-frame-reloc.s
achO/eh-symbols.s
achO/eh_symbol.s
achO/gen-dwarf-cpp.s
achO/gen-dwarf.s
achO/osx-version-min-load-command.s
achO/x86_32-scattered-reloc-fallback.s
ips/abicalls.ll
ips/cfi.s
ips/cpsetup.s
ips/do_switch.ll
ips/do_switch1.s
ips/do_switch2.s
ips/do_switch3.s
ips/elf-N64.ll
ips/elf-N64.s
ips/elf-gprel-32-64.ll
ips/elf-gprel-32-64.s
ips/elf-reginfo.ll
ips/elf-relsym.ll
ips/elf-relsym.s
ips/elf-tls.ll
ips/elf-tls.s
ips/elf_eflags.ll
ips/elf_eflags.s
ips/elf_eflags_abicalls.s
ips/elf_eflags_micromips.s
ips/elf_eflags_mips16.s
ips/elf_eflags_noreorder.s
ips/elf_eflags_pic0.s
ips/elf_eflags_pic2.s
ips/elf_reginfo.s
ips/elf_st_other.ll
ips/elf_st_other.s
ips/higher-highest-addressing.s
ips/higher_highest.ll
ips/hilo-addressing.s
ips/lea_64.ll
ips/micromips-16-bit-instructions.s
ips/micromips-alias.s
ips/micromips-alu-instructions.s
ips/micromips-bad-branches.s
ips/micromips-control-instructions.s
ips/micromips-diagnostic-fixup.s
ips/micromips-el-fixup-data.s
ips/micromips-fpu-instructions.s
ips/micromips-jump-instructions.s
ips/micromips-loadstore-instructions.s
ips/micromips-long-branch.ll
ips/micromips-pc16-fixup.s
ips/micromips-relocations.s
ips/mips-alu-instructions.s
ips/mips-bad-branches.s
ips/mips-data-directives.s
ips/mips-diagnostic-fixup.s
ips/mips-jump-instructions.s
ips/mips-noat.s
ips/mips-pc16-fixup.s
ips/mips-register-names-invalid.s
ips/mips-register-names-o32.s
ips/mips-register-names.s
ips/mips1/valid-xfail.s
ips/mips1/valid.s
ips/mips2/valid-xfail.s
ips/mips2/valid.s
ips/mips3/valid-xfail.s
ips/mips3/valid.s
ips/mips32/invalid-mips32r2-xfail.s
ips/mips32/invalid-mips32r2.s
ips/mips32/valid-xfail.s
ips/mips32/valid.s
ips/mips32r2/valid-xfail.s
ips/mips32r2/valid.s
ips/mips4/invalid-mips64-xfail.s
ips/mips4/invalid-mips64.s
ips/mips4/invalid-mips64r2-xfail.s
ips/mips4/invalid-mips64r2.s
ips/mips4/valid-xfail.s
ips/mips4/valid.s
ips/mips5/valid-xfail.s
ips/mips5/valid.s
ips/mips64-alu-instructions.s
ips/mips64-register-names-n32-n64.s
ips/mips64-register-names-o32.s
ips/mips64-register-names.s
ips/mips64/invalid-mips64r2-xfail.s
ips/mips64/invalid-mips64r2.s
ips/mips64/valid-xfail.s
ips/mips64/valid.s
ips/mips64eb-fixups.s
ips/mips64r2/valid-xfail.s
ips/mips64r2/valid.s
ips/mips_directives.s
ips/mips_directives_bad.s
ips/mips_gprel16.ll
ips/mips_gprel16.s
ips/msa/test_2r.s
ips/msa/test_2r_msa64.s
ips/msa/test_2rf.s
ips/msa/test_3r.s
ips/msa/test_3rf.s
ips/msa/test_bit.s
ips/msa/test_cbranch.s
ips/msa/test_ctrlregs.s
ips/msa/test_dlsa.s
ips/msa/test_elm.s
ips/msa/test_elm_insert.s
ips/msa/test_elm_insert_msa64.s
ips/msa/test_elm_insve.s
ips/msa/test_elm_msa64.s
ips/msa/test_i10.s
ips/msa/test_i5.s
ips/msa/test_i8.s
ips/msa/test_lsa.s
ips/msa/test_mi10.s
ips/msa/test_vec.s
ips/nabi-regs.s
ips/nacl-mask.s
ips/octeon-instructions.s
ips/r-mips-got-disp.ll
ips/r-mips-got-disp.s
ips/set-at-directive-explicit-at.s
ips/set-at-directive.s
ips/sym-expr.s
ips/xgot.ll
ips/xgot.s
owerPC/deprecated-p7.s
owerPC/ppc-llong.s
owerPC/ppc-machine.s
owerPC/ppc-nop.s
owerPC/ppc-word.s
owerPC/ppc64-encoding-bookII.s
owerPC/ppc64-encoding-bookIII.s
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding-fp.s
owerPC/ppc64-encoding-vmx.s
owerPC/ppc64-encoding.s
owerPC/ppc64-errors.s
owerPC/ppc64-fixup-apply.s
owerPC/ppc64-fixup-explicit.s
owerPC/ppc64-fixups.s
owerPC/ppc64-initial-cfa.s
owerPC/ppc64-operands.s
owerPC/ppc64-regs.s
owerPC/vsx.s
parc/lit.local.cfg
parc/sparc-alu-instructions.s
parc/sparc-atomic-instructions.s
parc/sparc-ctrl-instructions.s
parc/sparc-directive-xword.s
parc/sparc-directives.s
parc/sparc-fp-instructions.s
parc/sparc-mem-instructions.s
parc/sparc-nop-data.s
parc/sparc-pic.s
parc/sparc-relocations.s
parc/sparc-vis.s
parc/sparc64-alu-instructions.s
parc/sparc64-ctrl-instructions.s
parc/sparcv8-instructions.s
parc/sparcv9-instructions.s
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
86/address-size.s
86/avx512-encodings.s
86/fixup-cpu-mode.s
86/index-operations.s
86/intel-syntax-avx512.s
86/intel-syntax-bitwise-ops.s
86/intel-syntax-directional-label.s
86/intel-syntax-invalid-basereg.s
86/intel-syntax-invalid-scale.s
86/intel-syntax.s
86/no-elf-compact-unwind.s
86/padlock.s
86/relax-insn.s
86/reloc-undef-global.s
86/ret.s
86/stackmap-nops.ll
86/variant-diagnostics.s
86/x86-16.s
86/x86-32.s
86/x86-64.s
86/x86-target-directives.s
86/x86_64-avx-encoding.s
86/x86_64-signed-reloc.s
86/x86_64-tbm-encoding.s
86/x86_errors.s
|
| cdf67d5791d044a5f217114e18eb8d6242222b98 |
02-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196104:
------------------------------------------------------------------------
r196104 | rafael | 2013-12-02 06:59:34 -0800 (Mon, 02 Dec 2013) | 1 line
Output .eh_frames on COFF too now that the integrated as is used on mingw.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196137 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/eh-frame.s
|
| 88fc0183be1b1fc94375421c48f8e0ef6fa9139e |
01-Dec-2013 |
Daniel Sanders <daniel.sanders@imgtec.com> |
Merged from r195975 and r195976.
------------------------------------------------------------------------
r195975 | zjovanovic | 2013-11-30 19:12:28 +0000 (Sat, 30 Nov 2013) | 1 line
Fixed issue with microMIPS long branch.
------------------------------------------------------------------------
r195976 | zjovanovic | 2013-11-30 19:13:15 +0000 (Sat, 30 Nov 2013) | 1 line
Test case for issue with microMIPS long branch.
------------------------------------------------------------------------
To expand on those commit messages:
The immediate in a MIPS branch is multiplied by the instruction size before use
as an offset. For many MIPS ISA's this is 4 bytes, but for microMIPS it is 2
bytes. This commit corrects the scale factor used for microMIPS so that attempts
to use large offsets result in a valid sequence of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196043 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-long-branch.ll
|
| d0cf77ad590633c0e10336e4c59b509140328042 |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
--- Reverse-merging r195823 into '.':
U lib/MC/MCSectionCOFF.cpp
U lib/CodeGen/TargetLoweringObjectFileImpl.cpp
U test/MC/COFF/weak-symbol.ll
U test/MC/COFF/tricky-names.ll
G .
--- Recording mergeinfo for reverse merge of r195823 into '.':
G .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196036 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/tricky-names.ll
OFF/weak-symbol.ll
|
| ffafab019600347714602ff8a5ed38ce7d740ee4 |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195936:
------------------------------------------------------------------------
r195936 | kevinqin | 2013-11-28 17:29:16 -0800 (Thu, 28 Nov 2013) | 1 line
[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196028 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/AArch64/neon-instructions.txt
|
| ae38e1a9b485dcbeddac0ac9530c195e387cafe3 |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195903:
------------------------------------------------------------------------
r195903 | haoliu | 2013-11-27 17:07:45 -0800 (Wed, 27 Nov 2013) | 2 lines
AArch64: Fix a bug about disassembling post-index load single element to 4 vectors
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196025 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/AArch64/neon-instructions.txt
|
| 06866a72b0117e15463b0706d994270b3e20948d |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195677:
------------------------------------------------------------------------
r195677 | dpeixott | 2013-11-25 11:11:13 -0800 (Mon, 25 Nov 2013) | 41 lines
ARM integrated assembler generates incorrect nop opcode
This patch fixes a bug in the assembler that was causing bad code to
be emitted. When switching modes in an assembly file (e.g. arm to
thumb mode) we would always emit the opcode from the original mode.
Consider this small example:
$ cat align.s
.code 16
foo:
add r0, r0
.align 3
add r0, r0
$ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o
$ llvm-objdump -triple thumbv7 -d t.o
Disassembly of section .text:
foo:
0: 00 44 add r0, r0
2: 00 f0 20 e3 blx #4195904
6: 00 00 movs r0, r0
8: 00 44 add r0, r0
This shows that we have actually emitted an arm nop (e320f000)
instead of a thumb nop. Unfortunately, this encodes to a thumb
branch which causes bad things to happen when compiling assembly
code with align directives.
The fix is to notify the ARMAsmBackend when we switch mode. The
MCMachOStreamer was already doing this correctly. This patch makes
the same change for the MCElfStreamer.
There is still a bug in the way nops are emitted for alignment
because the MCAlignment fragment does not store the correct mode.
The ARMAsmBackend will emit nops for the last mode it knew about. In
the example above, we still generate an arm nop if we add a `.code
32` to the end of the file.
PR18019
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196001 91177308-0d34-0410-b5e6-96231b3b80d8
RM/align_arm_2_thumb.s
RM/align_thumb_2_arm.s
|
| 5f1f4773d95560b68a9c75856563e45e3a4d57e3 |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195803:
------------------------------------------------------------------------
r195803 | mcrosier | 2013-11-26 17:45:58 -0800 (Tue, 26 Nov 2013) | 1 line
[AArch64] Add support for NEON scalar floating-point absolute difference.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195994 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-abs.s
isassembler/AArch64/neon-instructions.txt
|
| 2527bdac885f5822bb2b9a805fc9d80b35dd8f8b |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195788:
------------------------------------------------------------------------
r195788 | mcrosier | 2013-11-26 14:17:37 -0800 (Tue, 26 Nov 2013) | 2 lines
[AArch64] Add support for NEON scalar floating-point to integer convert
instructions.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195993 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-cvt.s
isassembler/AArch64/neon-instructions.txt
|
| 38af06736e6d46ef3d417e40b9843ca1658fc8e7 |
27-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195798:
------------------------------------------------------------------------
r195798 | rafael | 2013-11-26 17:18:37 -0800 (Tue, 26 Nov 2013) | 9 lines
Use simple section names for COMDAT sections on COFF.
With this patch we use simple names for COMDAT sections (like .text or .bss).
This matches the MSVC behavior.
When merging it is the COMDAT symbol that is used to decide if two sections
should be merged, so there is no point in building a fancy name.
This survived a bootstrap on mingw32.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195823 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/tricky-names.ll
OFF/weak-symbol.ll
|
| 0ae07098f7d2ad5a1868d448d0b1b4eef2a3b091 |
27-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195148:
------------------------------------------------------------------------
r195148 | rafael | 2013-11-19 11:52:52 -0800 (Tue, 19 Nov 2013) | 15 lines
Support multiple COFF sections with the same name but different COMDAT.
This is the first step to fix pr17918.
It extends the .section directive a bit, inspired by what the ELF one looks
like. The problem with using linkonce is that given
.section foo
.linkonce....
.section foo
.linkonce
we would already have switched sections when getting to .linkonce. The cleanest
solution seems to be to add the comdat information in the .section itself.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195822 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/section-comdat.s
|
| b5c8cf3ccd7a3cf27044a0f1c160bb4133b42eea |
26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195682:
------------------------------------------------------------------------
r195682 | rafael | 2013-11-25 12:46:18 -0800 (Mon, 25 Nov 2013) | 1 line
Use -triple to fix the test on non-ELF hosts.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195745 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_nop.s
|
| 9ed81d16f71b60c246a7b8e9ed4fdd58a48ce4b9 |
26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195679:
------------------------------------------------------------------------
r195679 | rafael | 2013-11-25 12:15:14 -0800 (Mon, 25 Nov 2013) | 12 lines
Don't use nopl in cpus that don't support it.
Patch by Mikulas Patocka. I added the test. I checked that for cpu names that
gas knows about, it also doesn't generate nopl.
The modified cpus:
i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta
Crusoe, Microsoft VirtualBox - see
https://bbs.archlinux.org/viewtopic.php?pid=775414
k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs
via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that
Via c3 and c3-Nehemiah don't have nopl
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195730 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_nop.s
|
| c844be242228e2966851658a784a367ff5e249ca |
25-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195591:
------------------------------------------------------------------------
r195591 | haoliu | 2013-11-24 17:53:26 -0800 (Sun, 24 Nov 2013) | 5 lines
Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195619 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/AArch64/neon-instructions.txt
|
| e8bb6e26b83e08631ad336bb0d8076787b858c34 |
25-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195330:
------------------------------------------------------------------------
r195330 | apazos | 2013-11-21 00:16:15 -0800 (Thu, 21 Nov 2013) | 5 lines
Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195612 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-scalar-dup.s
|
| a87a147ee7bb9adb4caea631ff0ba7e66bb9b0b5 |
20-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195152:
------------------------------------------------------------------------
r195152 | jacksprat | 2013-11-19 12:53:28 -0800 (Tue, 19 Nov 2013) | 1 line
reverts 195057 per request
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195220 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_eflags.ll
ips/elf_eflags.s
ips/elf_st_other.ll
ips/elf_st_other.s
|
| 36c7806f4eacd676932ba630246f88e0e37b1cd4 |
19-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-simd-ldst-one-elem.s
isassembler/AArch64/neon-instructions.txt
|
| 282a979dddff8d06a744c1b686fb3b7a7619d0f4 |
19-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-3vdiff.s
Arch64/neon-diagnostics.s
|
| 01dd5728cc897777da95a7f4672b5a2540d52564 |
19-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Add predicate for AArch64 crypto instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-crypto.s
|
| e53969b4758274ee833ce3acef37134bcf6554ea |
19-Nov-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips] Support for MicroMips STO refactoring.
No true functional changes.
Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.
Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.
XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_eflags.ll
ips/elf_eflags.s
ips/elf_st_other.ll
ips/elf_st_other.s
|
| a7b7a7d629c3101f6f6c87e6848e865734e0238c |
19-Nov-2013 |
Reid Kleckner <reid@kleckner.net> |
Revert "COFF: Emit all MCSymbols rather than filtering out some of them"
This reverts commit r190888, to fix PR17967. The original change wasn't
the right way to get @feat.00 into the object file. The right fix is to
make @feat.00 be a global symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/alias.s
OFF/feat00.s
OFF/lset0.s
|
| 26651c7a6602626cf13ff3cda13f3ec2401bf790 |
18-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_cbranch.s
|
| 95adf91f29980e374bf094e15bc3f2764ef9baf4 |
18-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_lsa.s
|
| 69b2447b6a3fcc303e03cba8c7c50d745b0284d2 |
18-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
[AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-simd-copy.s
|
| 42cb3abaddfcff16ab18b114c3de034839c85e05 |
15-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Use instr mapping for microMIPS in llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-trap-instructions.s
|
| 27df434c5e8c78e8b3e6e9596b55a6a6bd8d5116 |
14-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Add test case for AArch64 NEON instruction set misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-simd-misc.s
|
| a08063a000cfc7499f08a472d85f14e7a5e90f8d |
14-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction class SIMD misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
|
| 082ac99cc86b17c7cd2a1f2a6faa2d1adc184e17 |
14-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 NEON instruction set AdvSIMD (table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-tbl.s
isassembler/AArch64/neon-instructions.txt
|
| 541c5de2fb57b2f459f0ec49f33a0ecce3532acd |
13-Nov-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add the general form of BCR
At the moment this is just the MC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| c0fad4d9fdb1aebe029bcb54311fad7059b1a9e5 |
13-Nov-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Fix bug in .gpword directive parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 1206f1968b0886ab41739aebe113dd4813f3fc46 |
13-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS trap instruction with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
ips/micromips-trap-instructions.s
|
| c7ebe502765fecc2af047ced115845936e8ed58e |
13-Nov-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| 59e648e3c8966e0678902a2994558f25c8573ce4 |
12-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).
(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| 13c83a2a09a0842ff57ec020fe3f534de766ccd1 |
12-Nov-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases.
Patch by Ana Pazos <apazos@codeaurora.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-3vdiff.s
Arch64/neon-diagnostics.s
Arch64/neon-scalar-by-elem-mla.s
Arch64/neon-scalar-by-elem-mul.s
Arch64/neon-scalar-by-elem-saturating-mla.s
Arch64/neon-scalar-by-elem-saturating-mul.s
Arch64/neon-scalar-dup.s
Arch64/neon-simd-copy.s
Arch64/neon-simd-shift.s
isassembler/AArch64/neon-instructions.txt
|
| ef572e31e210a03c0669e3ed2ed7cf2d789f8599 |
11-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Add support for MVFR2 which is new in ARMv8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
RM/fp-armv8.s
isassembler/ARM/fp-armv8.txt
isassembler/ARM/invalid-because-armv7.txt
|
| 30b2a19f3be840da1bc4aefcaabcbddd2e0130fc |
11-Nov-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-cvt.s
isassembler/AArch64/neon-instructions.txt
|
| dc7eb3e023e34adc9d40e93626467cfe22756f4c |
08-Nov-2013 |
Jim Grosbach <grosbach@apple.com> |
X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.
rdar://15406518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
86/cfi_def_cfa-crash.s
|
| 2b01682aa7b9509e9fa1865ebed3d0a7928f5b7a |
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
RM/v8_IT_manual.s
isassembler/ARM/invalid-thumbv8.txt
isassembler/ARM/thumb2-v8.txt
|
| c5c991bf314fb0b9f3b591a0c18d4a45efcfe392 |
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-armv8.txt
|
| fa840ba402806d978c18401c6bea1c808607d944 |
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/basic-arm-instructions-v8.txt
|
| c9af1add85658763d34dea1abb49be49eb71bb13 |
08-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Test for microMIPS trap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-trap-instructions.s
|
| de712386cdde314ee18ea44b733d48a30d63de10 |
08-Nov-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_i10.s
|
| 1b91231347c00bf1be46bdd5b27ae8c45fdc0d0c |
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
RM/diagnostics.s
RM/thumb-only-conditionals.s
|
| 9f471750fa6f34120d4758d5d14f54f899e34a54 |
07-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS trap instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
|
| 2263a2ca72e21206d45a69532004a0b17881e733 |
06-Nov-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 8458f371b84ee0cd22c4a433059d53ea6e3ec4f4 |
06-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-perm.s
isassembler/AArch64/neon-instructions.txt
|
| 258115258f8fe15e9d74b5fb524f90b75bb917d1 |
06-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-extract.s
isassembler/AArch64/neon-instructions.txt
|
| f635ab8eabb06a41fa791d897ebf32eb338688a0 |
05-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-hints.s
|
| 3ff3a8aa7511bede13e836303a083af37fec4f4e |
05-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-crypto.s
Arch64/neon-diagnostics.s
|
| 591c2f738a3e12026ff5504a486d54fc21fb3049 |
05-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-simd-post-ldst-multi-elem.s
isassembler/AArch64/neon-instructions.txt
|
| 5c042162beb3c2dd556e00aab84c4278a69cd5b1 |
04-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
ips/micromips-branch-instructions.s
ips/micromips-branch16.s
|
| 1a035dd6df1d953af57656491eda28ceef9ad4a3 |
31-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-cvt.s
isassembler/AArch64/neon-instructions.txt
|
| f7ba4897302bf930f7ec4682a296ff4cd736a0e3 |
31-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193798 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
|
| 1d28917dc39f38847f5c69c0a60cd1491430bdad |
31-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar shift immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-shift-imm.s
isassembler/AArch64/neon-instructions.txt
|
| c2884320feebc543d2ce51151d5418dfc18da9e4 |
31-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-a64-instructions.s
Arch64/elf-reloc-ldstunsimm.s
Arch64/inline-asm-modifiers.s
isassembler/AArch64/a64-ignored-fields.txt
isassembler/AArch64/basic-a64-instructions.txt
isassembler/AArch64/basic-a64-unpredictable.txt
isassembler/AArch64/ldp-postind.predictable.txt
isassembler/AArch64/ldp-preind.predictable.txt
|
| 4ca9a2a0adf01ae1aaad2c7fa499501b58183991 |
30-Oct-2013 |
Tom Roeder <tmroeder@google.com> |
This commit adds some (but not all) of the x86-64 relocations that are not
currently supported in the ELF object writer, along with a simple test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193709 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 3f04b5068619ca0411521c9871f4bfc6b04f951f |
30-Oct-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] NEON instructions were erroneously decoded from certain invalid encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-neon-crypto.txt
|
| f853a034a1fdccd194da04ca1e2e1aa8bcbd16b4 |
30-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar floating-point compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-fp-compare.s
isassembler/AArch64/neon-instructions.txt
|
| 1aaf43c2a2ec0fd4c8dbfe56558237219c5f8af7 |
29-Oct-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
ips/micromips-jump-instructions.s
ips/micromips-jump26.s
ips/micromips-tailr.s
|
| c777b2e58c0df1b8e7a8c0c8e78eb53d83549186 |
29-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
Test cleanup for v8 instructions
Add some missing tests, factor out a test not specific to v8 into
its own file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions-v8.s
RM/basic-thumb2-instructions-v8.s
RM/invalid-barrier.s
|
| 47c6d17b1cce85ba30471b2270419e35ba3d5653 |
29-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.
Differential Revision: http://llvm-reviews.chandlerc.com/D2036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
RM/crc32-thumb.s
RM/crc32.s
|
| 72580780a98cb8b0019b7ec4ed88e3f3328b9969 |
29-Oct-2013 |
Joerg Sonnenberger <joerg@bec.de> |
Move the STT_FILE symbols out of the normal symbol table processing for
ELF. They can overlap with the other symbols, e.g. if a source file
"foo.c" contains a function "foo" with a static variable "c".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193569 91177308-0d34-0410-b5e6-96231b3b80d8
LF/file-double.s
|
| 136660484d56ac5bb168e0c3a8f6fbc9d986723e |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193548 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/tls-ie-obj.s
|
| 61e4743913b68daec52460a8447cbe7e210626e9 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193547 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/tls-ld-obj.s
|
| 82c2703167bcc4132ff6eeff128268d8d13029a1 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193546 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/tls-gd-obj.s
|
| 1df3e17fdedab84fcc71413d43120f6780889abc |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193539 91177308-0d34-0410-b5e6-96231b3b80d8
RM/2010-11-30-reloc-movt.s
|
| 9540074467ca6af4098467261336edbe61f6deea |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193538 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/inline-asm-modifiers.s
|
| ade09c7fe7426dca21310911c8ebca17f738342f |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193537 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/jump-table.s
|
| e2f60cf7f10d8e732031a519b321e324b5277210 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193536 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/elf-extern.s
|
| 3d478aee8e2480661cb0d98b10da8ad2ebf59fcf |
28-Oct-2013 |
Lang Hames <lhames@gmail.com> |
Return early from getUnconditionalBranchTargetOpValue if the branch target is
an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.
When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.
Fixes <rdar://problem/15155975>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193535 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 164bd156fc92dc738e5f8dce5da263e1d17211c4 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert a llc -filetype=obj test into a llvm-mc test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193534 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-pic.s
|
| 23125d02d929758e1b0dbb30b13f1deff7a5ea4b |
28-Oct-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
RM/directive-cpu.s
RM/directive-eabi_attribute.s
RM/directive-fpu-multiple.s
RM/directive-fpu.s
|
| c8f4e5db29270fc7ed164af973ece7ba5921539b |
25-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow .thumb_func to be separated from symbol definition
When assembling, a .thumb_func directive is supposed to be applicable to the
next symbol definition, even if there are intervening directives. We were
racing ahead to try and find it, and this commit should fix the issue.
Patch by Gabor Ballabas
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193403 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc.s
|
| abe3aa35200e4319f20203b99ebfc4ab6880391c |
25-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: tweak test to pass on all platforms
A TableGen indeterminacy means that the reason for the failure can
vary, and Windows gets the other option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193394 91177308-0d34-0410-b5e6-96231b3b80d8
RM/single-precision-fp.s
|
| 44edc227c743052bd58e73a5e1402fa68ed728f0 |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.
No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.
rdar://problem/15302004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193354 91177308-0d34-0410-b5e6-96231b3b80d8
RM/single-precision-fp.s
RM/vfp4.s
|
| e2dee623e0eeb12c6e22add0e55139693ffb2dca |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add a couple more NEON predicates.
The fused multiply instructions were added in VFPv4 but are still NEON
instructions, in particular they shouldn't be available on a Cortex-M4 not
matter how floaty it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193342 91177308-0d34-0410-b5e6-96231b3b80d8
RM/vfp4.s
|
| eac623a18b1e7ad9e5a7da76a323039450b7d7ce |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.
This tidies up the obvious VFP and NEON cases I found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics-noneon.s
RM/diagnostics.s
|
| ef713e27b1b9f685adc1ae35526d92c6ad0324e5 |
24-Oct-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Added tests for microMIPS relocations 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193332 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-expansions.s
ips/micromips-expressions.s
ips/micromips-relocations.s
|
| cdd776d13f799da1aff4b2c9c58a236bee74ea2e |
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.
With some vigorous hand-waving in the error message both problems can be
fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193322 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
RM/thumb-diagnostics.s
|
| f7b6bac2629c09b5dcdf9dd926c02490d2c81cd2 |
23-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for the LSA instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193240 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_lsa.s
|
| b161955ffbda5ccb5293e0c76ef982acb6ec6661 |
23-Oct-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
Make ARM hint ranges consistent, and add tests for these ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
RM/invalid-hint-arm.s
RM/invalid-hint-thumb.s
isassembler/ARM/thumb2.txt
|
| 2b3ea3cdad927cb0e346dd24e9bf84f8eb83babf |
23-Oct-2013 |
David Blaikie <dblaikie@gmail.com> |
MC: Support multiple sections with the same name in the same comdat group
Code review by Eric Christopher and Rafael Espindola.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193209 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comdat-dup-group-name.s
|
| 01b0e94bb731310e72f66977e4b57cd3f3280ba4 |
22-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.
For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
RM/thumb-diagnostics.s
isassembler/ARM/invalid-thumbv7.txt
|
| 5cb5ff8b1478ed413a9e9fae43b1496f5a97a2dc |
22-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for conditional branches.
These branches have a 16-bit offset (R_MIPS_PC16).
List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193157 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_cbranch.s
|
| 348da8d6b5e002c3698c37aca26c508bc60a05bb |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for LD/ST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_mi10.s
|
| b14ad465492c472033e9ded65ab40e4a9c2c451a |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for LDI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193081 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_i10.s
|
| f6d4cff9b1cf1e3b57592d6a0e40f0026813aa7c |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for MOVE.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193080 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm.s
|
| 006cff8d7b60ddf632f8642f01693dace7827d8b |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon
as GAS starts accepting them by name as that would make the assembly easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_ctrlregs.s
|
| cebd4010222f28bb68c217047fd0b2c90498f7ca |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of SPLAT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193077 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_3r.s
|
| f89f66e61b26974bb73b5832d5825091873b51dc |
21-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Fix definition of SLD instruction.
The second parameter of the SLD intrinsic is the number of columns (GPR) to
slide left the source array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_3r.s
|
| e52fac1632dc43d0595e06baf5743608b173dfbc |
20-Oct-2013 |
Peter Collingbourne <peter@pcc.me.uk> |
Emit DWARF line entries for all data in the instruction stream.
r182712 attempted to do this, but it failed to handle data emitted via
EmitBytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193041 91177308-0d34-0410-b5e6-96231b3b80d8
LF/debug-line.s
|
| 22f9dd4591e8af6d6feed10a4b6e11a784582edc |
18-Oct-2013 |
Hans Wennborg <hans@hanshq.net> |
MC asm parser: allow ?'s in symbol names, and handle @'s in names in MS asm
This is another (final?) stab at making us able to parse our own asm output
on Windows.
Symbols on Windows often contain @'s and ?'s in their names. Our asm parser
didn't like this. ?'s were not allowed, and @'s were intepreted as trying to
reference PLT/GOT/etc.
We can't just add quotes around the bad names, since e.g. for MinGW, we use gas
to assemble, and it doesn't like quotes in some places (notably in .def
directives).
This commit makes us allow ?'s in symbol names, and @'s in symbol names for MS
assembly.
Differential Revision: http://llvm-reviews.chandlerc.com/D1978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193000 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/tricky-names.ll
LF/bad-relocation.s
LF/symbol-names.s
|
| 485333df7157d6e8681d910d85b271b0bc96b48e |
18-Oct-2013 |
Richard Barton <richard.barton@arm.com> |
Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
isassembler/ARM/invalid-thumbv7.txt
isassembler/ARM/thumb2.txt
|
| c439c205ba304c7ed1c88fb85c2009e49cfbd0c3 |
18-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar extract narrow instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-extract-narrow.s
isassembler/AArch64/neon-instructions.txt
|
| b1c480900bdc6486624a476b6ae25cb02a3b6276 |
18-Oct-2013 |
Silviu Baranga <silviu.baranga@arm.com> |
Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192963 91177308-0d34-0410-b5e6-96231b3b80d8
RM/idiv.s
RM/invalid-idiv.s
|
| ab887bf52c99c2c9a4346b6dea2b8118e18a4282 |
18-Oct-2013 |
Hans Wennborg <hans@hanshq.net> |
Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"
This caused the clang-native-mingw32-win7 buildbot to break.
The assembler was complaining about the following lines that were showing up
in the asm for CrashRecoveryContext.cpp:
movl $"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4", 4(%eax)
calll "_AddVectoredExceptionHandler@8"
.def "__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4";
"__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4":
calll "_RemoveVectoredExceptionHandler@4"
Reverting for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192940 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/quoted-names.ll
|
| 3b370a2ac433c4abfbfe8f47c63fee0dbcfcc9e6 |
17-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar three register different instruction
class. The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-mul.s
isassembler/AArch64/neon-instructions.txt
|
| b74b88edac9ab490ba428aef0bdebc957399bbd7 |
17-Oct-2013 |
Hans Wennborg <hans@hanshq.net> |
Re-commit r192758 - MC: quote tricky symbol names in asm output
The reason this got reverted was that the @feat.00 symbol which was emitted
for every TU became quoted, and on cygwin/mingw we use the gas assembler which
couldn't handle the quotes.
This commit fixes the problem by only emitting @feat.00 for win32, where we use
clang -cc1as to assemble. gas would just drop this symbol anyway, so there is no
loss there.
With @feat.00 gone, there shouldn't be quoted symbols showing up on cygwin since
it uses the Itanium ABI, which doesn't put these funny characters in symbols.
> Because of win32 mangling, we produce symbol and section names with
> funny characters in them, most notably @ characters.
>
> MC would choke on trying to parse its own assembly output. This patch addresses
> that by:
>
> - Making @ trigger quoting of symbol names
> - Also quote section names in the same way
> - Just parse section names like other identifiers (to allow for quotes)
> - Don't assume @ signifies a symbol variant if it is in a string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192859 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/quoted-names.ll
|
| dceac4c5a611f26ebcc88c75cc39075c7df2466e |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar negate instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-neg.s
isassembler/AArch64/neon-instructions.txt
|
| a249914462c7b8f0c25b21eca77df264455290ee |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar absolute value instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-abs.s
isassembler/AArch64/neon-instructions.txt
|
| 8225b23c6adcb1be605108425b7eb169b6439b64 |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-saturating-add-sub.s
isassembler/AArch64/neon-instructions.txt
|
| a2cd42a0a7c46d158714c09047a77b7bc1cf9d69 |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-saturating-add-sub.s
isassembler/AArch64/neon-instructions.txt
|
| 32c24da3730e8e5ea7df3ce7aeffa257b2e7f02f |
16-Oct-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Revert r192758 (and r192759), "MC: Better handling of tricky symbol and section names"
GNU AS didn't like quotes in symbol names.
Error: junk at end of line, first unrecognized character is `"'
.def "@feat.00";
"@feat.00" = 1
Reproduced on Cygwin's 2.23.52.20130309 and mingw32's 2.20.1.20100303.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192775 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/quoted-names.ll
|
| d910c469632a75ccb85bf0619a9c50a207914a2c |
16-Oct-2013 |
Hans Wennborg <hans@hanshq.net> |
dos2unix on quoted-names.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192759 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/quoted-names.ll
|
| 508d7b7330968c48e69f0da82c66bdcc0afe6190 |
16-Oct-2013 |
Hans Wennborg <hans@hanshq.net> |
MC: Better handling of tricky symbol and section names
Because of win32 mangling, we produce symbol and section names with
funny characters in them, most notably @ characters.
MC would choke on trying to parse its own assembly output. This patch addresses
that by:
- Making @ trigger quoting of symbol names
- Also quote section names in the same way
- Just parse section names like other identifiers (to allow for quotes)
- Don't assume @ signifies a symbol variant if it is in a string.
Differential Revision: http://llvm-reviews.chandlerc.com/D1945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192758 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/quoted-names.ll
|
| 1824bd0ef84bd162065f9d1fad4c325a39736248 |
15-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar signed saturating absolute value and
scalar signed saturating negate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-scalar-abs.s
Arch64/neon-scalar-neg.s
isassembler/AArch64/neon-instructions.txt
|
| b00491341778776a4d994846ca2f7fafe79c161d |
15-Oct-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set HI/LO registers' HWEncoding field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192661 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-dsp-instructions.s
|
| 942827b1139c432239648ef54d1df5074eac36ec |
14-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar integer compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-compare.s
isassembler/AArch64/neon-instructions.txt
|
| 7220572e74844aa37b1b492ef67a8c1b403a254f |
14-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
RM/invalid-fp-armv8.s
RM/invalid-neon-v8.s
|
| 9672a89c71f7b368455ed193bc23566f3bd4ed2b |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_bit.s
|
| e89c50acc8312c6cd4d3bdbf50e02ba88e54a663 |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192588 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_vec.s
|
| 01436ba3066b99547c1138edf5c36ef2ad467e71 |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm_insve.s
|
| 29adbe8464f74f17a7cf977ce21ef88d88d28b14 |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192586 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm.s
|
| 45ecbfc8e58923131068dced0cf89348ac61208f |
14-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm_insert.s
|
| c6f7c99809cece8c85e180c1b95e6159d8ea9613 |
14-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
86/x86_64-avx-encoding.s
86/x86_64-encoding.s
|
| 8e121843c19297205fe9acb9153570f596838eb9 |
14-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
|
| bae9f69d37a60aad0185cdf17434ec188c976e67 |
14-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-encoding.s
|
| 5af763cb2ad96f557f88acdb11a710e7c7256800 |
11-Oct-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Mips: Disassemble sign-extended 64 bit immediates properly.
This doesn't change the meaning of the output, but makes look right. PR17539.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips64.txt
|
| fc3dc102e0bef8ecb7cd13ceab77dc130175f792 |
11-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Fix FP ABI attributes with no VFP enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192458 91177308-0d34-0410-b5e6-96231b3b80d8
RM/xscale-attributes.ll
|
| 21d60f02c36c2362899109239d16824caa56d8ab |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
This reverts 192447 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm_insert.s
|
| abba71663eeebbea725eded5e23f273147824ed2 |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
This reverts r192449 because of compiler warning generated on darwin build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm.s
|
| 62a69eee5ad951502de28871ef27bb64dbf5508f |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm.s
|
| 6f36ea5c4778ac0519d821798b94aaac92ec1389 |
11-Oct-2013 |
Matheus Almeida <matheus.almeida@imgtec.com> |
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed.
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
general purpose register. The changes to parseMSARegs reflect that requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_elm_insert.s
|
| 767f816b926376bd850a62a28d35343ad0559c91 |
11-Oct-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (copy).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-simd-copy.s
|
| 6a5a667517160ca1b557002a29d08868ae029451 |
10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-simd-ldst-multi-elem.s
|
| 812ddcc50f8bc3ec6ce115863ff2263815906aaf |
10-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-simd-ldst-multi-elem.s
|
| d622bef31d11a5a6429fe7fad557c9b111e96f69 |
10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-simd-ldst-multi-elem.s
|
| 15de63cfdedc9a449217c841f8e084387b2159c8 |
10-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Allow non-AVX form of pmovmskb to take a GR64 operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-encoding.s
|
| ccb06ae8f3ef0135d4bddf4f0f61f619c3ce3f1e |
09-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: migrate ADRP relaxation test to be llvm-mc only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192281 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/adrp-relocation.s
|
| c97650079383110d66ab104ee60d03ded2be8e35 |
09-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-recip.s
isassembler/AArch64/neon-instructions.txt
|
| 3dfe644f7b6a560e1991b03d8c419c973ac7ed8d |
08-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-scalar-cvt.s
isassembler/AArch64/neon-instructions.txt
|
| b9bc43852ceb74c845d28b96594e1ef4ae41329f |
08-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
86/x86-64.s
86/x86_64-avx-encoding.s
|
| ca7b2d08d7b918e5e8e921a837623af962b27d00 |
07-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Improve build attributes emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
RM/xscale-attributes.ll
|
| 2aeb4771a6ca0ee253e4836edbab5705203d9bb4 |
07-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-scalar-mul.s
Arch64/neon-scalar-recip.s
isassembler/AArch64/neon-instructions.txt
|
| fbe4f5afce63b5487e57b4b32ecdf3cbc2fb0327 |
07-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add some disassembly tests for Thumb sevl/sevl.w
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192106 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2-v8.txt
|
| cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09 |
07-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.
rdar://problem/15144406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
RM/thumb-hints.s
RM/thumb-nop.s
|
| e778f82a1e33826ab012bb970a406c9acf37349b |
07-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
isassembler/X86/x86-64.txt
|
| 8fdba75d5b865246455c335adf439def1c3daaeb |
07-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-avx-encoding.s
|
| 36a9b31b981553350f5cc4adad9917656c20e96e |
07-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Add disassembler support for long encodings for INC/DEC in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
isassembler/X86/x86-64.txt
|
| 5e195a4c8d8cd4498ab7e0aa16a3b6f273daf457 |
05-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.
The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.
It was never the intention that targets would keep doing things like
if (hasRawTextSupport())
Set flags in one way.
else
Set flags in another way.
When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.
This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.
The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.
I will also try to implement a target streamer interface, so that we can
move this out of the common code.
In summary, for any new work, two rules of the thumb are
* Don't use "llc -filetype=obj" in tests.
* Don't add calls to hasRawTextSupport.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-eflags-eabi-cg.ll
ips/elf_eflags.ll
ips/elf_eflags.s
ips/elf_st_other.ll
ips/elf_st_other.s
|
| beb6afa84397a27e48a9d72ac1d588bc6fcaf564 |
05-Oct-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (Across).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-across.s
Arch64/neon-diagnostics.s
|
| 6d389f5ebae9aa08309c5795234cf155054b6b39 |
05-Oct-2013 |
Jack Carter <jack.carter@imgtec.com> |
reverting per request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191992 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 8e48edcf3dd7dea9fec58b05a6ace6fbd0260d7c |
04-Oct-2013 |
Jack Carter <jack.carter@imgtec.com> |
[MC][AsmParser] Hook for post assembly file processing
This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file
directive processing.
Mips assembly requires processing inline directives that directly and
indirectly affect the output ELF header flags. This patch handles one
".abicalls".
To process these directives we are following the model the code generator
uses by storing state in a container as we go through processing and when
we detect the end of input file processing, AsmParser is notified and we
update the ELF header flags through a MipsELFStreamer method with a call from
MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer).
This patch will allow other targets the same functionality.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191982 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| dd518bcc9dd9e4028b2a979ced09edd5b6becd07 |
04-Oct-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (3V elem).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-2velem.s
Arch64/neon-diagnostics.s
|
| 6eef361b73b457896b310d411251aedd5e72476a |
03-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
RM/deprecated-v8.s
RM/v8_IT_manual.s
|
| 279d28265dccc2a7c56f9ea04917c87dc50c1578 |
03-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Add XOP disassembler support. Fixes PR13933.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
86/avx512-encodings.s
|
| cf0bb134a053492c550e3083f3b556e98a58041f |
02-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add test I forgot to git add in r191824.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191831 91177308-0d34-0410-b5e6-96231b3b80d8
achO/bss.s
|
| e22c56d6d81b84d6f4ba24c2f5b0b203e7ddffe9 |
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add comparisons of high words and memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| 185ef05ad6fdcaad1e831020b1f88d0046dd15d6 |
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add comparisons of large immediates using high words
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191775 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| ad366a3f67679a56d25464dc2bcad3a0a6a51780 |
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add immediate addition involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191774 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| d1311ac171f9cb90cab4906a6c0e091b6b65b862 |
01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions-v8.s
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions-v8.s
RM/invalid-hint-arm.s
RM/invalid-hint-thumb.s
isassembler/ARM/basic-arm-instructions-v8.txt
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/invalid-armv7.txt
isassembler/ARM/invalid-thumbv7.txt
|
| 9813dbf396e63f6d4fd99fe0f6651e831cb7414b |
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add truncating high-word stores (STCH and STHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191743 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| 9a05f040e70494ab0092faa9ed10dc70ff1f4e66 |
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191742 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| ced450f0e6266eb8c2624fc1895cbc2749d715c3 |
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add sign-extending high-word loads (LBH and LHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| 7d0b89bedd5c8a53c71498663046b7e14bb96d6d |
01-Oct-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Reapply: Add definitions of LFH and STFH
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts. That should have been fixed by r191735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191738 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| d59ad8a8013fd76177fb61c741562af3024d34cd |
01-Oct-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
|
| 20546c697f301cd73b3d32d8e33f8a5ef3f9ff27 |
30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Fix Thumb(-2) diagnostic tests.
Changing the diagnostic message for out of range branch targets in 191686 broke the tests.
The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191691 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
RM/thumb2-diagnostics.s
|
| bdf8015cffb1860776e5a5f28014b023a32ab1bc |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_i8.s
|
| b0247157c6d44363c36cffd0aeea0e2fa83d9335 |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_i5.s
|
| 70f556140fca702ef6062b0c46b032908b9ae2a5 |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191685 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_2r.s
|
| 2641f5e412ba84255d8b97f5098e3f57bf990ff1 |
30-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_2r.s
|
| 2f184eaf89bb155b423603fa827976b6d2fa5df4 |
30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-ldrd.s
|
| 9724873c317d2b170cfea87cdf2a402fcd7c6c7d |
30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.
See ARM ARM A8.8.72.
Violating this constraint results in unpredictable behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-ldrd.s
|
| 6206a132a76d407fd276de17147d8c9c2c9e9e9d |
30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Assembler: Add more negative tests for ARM LDRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191664 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-ldrd.s
|
| 16658af535ed09169cb1079a474334dbf1cb8dc7 |
30-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Revert r191661: Add definitions of LFH and STFH
For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191663 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| e09bcad77c033392669b8d9cd3d93209064dfbc4 |
30-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add definitions of LFH and STFH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191661 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| 6b85c4e56102bbaa21a643cf0487b7e506c7f083 |
30-Sep-2013 |
Craig Topper <craig.topper@gmail.com> |
Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191650 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 92b45819531966f2d1365ab3564342a561f3b949 |
30-Sep-2013 |
Craig Topper <craig.topper@gmail.com> |
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 951fcc9ce8add9a3542eeb18b1c862ae31d418ec |
29-Sep-2013 |
Craig Topper <craig.topper@gmail.com> |
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191633 91177308-0d34-0410-b5e6-96231b3b80d8
86/avx512-encodings.s
|
| f63c806e110f84e7993eb59cf2976f7328f20733 |
29-Sep-2013 |
Craig Topper <craig.topper@gmail.com> |
Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191632 91177308-0d34-0410-b5e6-96231b3b80d8
86/avx512-encodings.s
|
| f80a63fa23862e578de919f4b44d4fcdee68fd0d |
28-Sep-2013 |
Robert Wilhelm <robert.wilhelm@gmx.net> |
Fix spelling intruction -> instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-armv7.txt
|
| 685707c28e2c7117f025fb4e95e6ca64ed179bb0 |
27-Sep-2013 |
Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> |
Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-tbm-encoding.s
|
| cca114611945332852094fcadfaa4ffbd012bfb3 |
27-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:
LDRD<c> <Rt>, <Rt2>, ...
(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)
If those two constraints are not met the result of executing the instruction will be unpredictable.
Constraint (b) was already enforced, this commit adds support for constraint (a).
Fixes rdar://14479793.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-ldrd.s
RM/arm-memory-instructions.s
|
| 6b968eccd79409b0986f394fa597101cf79433d8 |
27-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!
As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.
If this constraint is not met the result of executing the instruction will be unpredictable.
Fixes rdar://14479780.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2-ldrd.s
|
| d7f5fac1117613ff6dd0e49308d2954ac10b4f1f |
27-Sep-2013 |
Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> |
Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191481 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
86/intel-syntax.s
|
| deac137da710cd8566b857ee9d1e182d4fd35932 |
27-Sep-2013 |
Adrian Prantl <aprantl@apple.com> |
MCParser/Debug info: Accept line number 0 as a legitimate value, since
CFE produces it to indicate artificial locations.
c.f.: DWARF standard, Table 6.2:
line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191471 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_loc.s
|
| 1327c089221da78b1bfd61067162023e520085ed |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191461 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_3rf.s
|
| 83ba58e5f0a5afbb23d7d2092d817accded4455a |
26-Sep-2013 |
Venkatraman Govindaraju <venkatra@cs.wisc.edu> |
Implements parsing and emitting of .cfi_window_save in MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191431 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/cfi-window-save.s
LF/cfi-window-save.s
|
| 9637da60835a60f8ccd8289d04c60b2dcd4b9b5a |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros. This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.
N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate. If that behavior is needed,
we can change writeNopData() to behave in the same way.
This fixes PR17352.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc-nop.s
|
| 11c2b15c0a8282cfdc1c74968ebaba92f1fdae34 |
26-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.
This fixes PR17350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-fp.s
|
| 9fa81ab83898314d1a6608e8303dc57253292796 |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_3r.s
|
| 4167b88cf5754597e5a7e53aa0cbba26c18b6162 |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_2rf.s
|
| 42d9ca629934d0c20ac19949399ce4faa9a7bbb3 |
26-Sep-2013 |
Jack Carter <jack.carter@imgtec.com> |
[mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.
Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
ips/msa/test_2rf.s
|
| 3f22cc1df64a6dd6a3ecc5e7e261f15af083f806 |
25-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
MC: Add support for treating $ as a reference to the PC
The binutils assembler supports a mode called DOLLAR_DOT which treats
the dollar sign token as a reference to the current program counter if
the dollar sign doesn't precede a constant or identifier.
This commit adds a new MCAsmInfo flag stating whether or not a given
target supports this interpretation of the dollar sign token; by
default, this flag is not enabled.
Further, enable this flag for PPC. The system assembler for AIX and
binutils both support using the dollar sign in this manner.
This fixes PR17353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191368 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-operands.s
|
| 9c60710c8045f6f22151da1271e2d40d1f68bcfd |
24-Sep-2013 |
Roman Divacky <rdivacky@freebsd.org> |
Make the size and expr arguments of .fill directive optional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191318 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_fill.s
|
| 477fc628b3c9ce1c970d4a678dd5607b15242cc8 |
24-Sep-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Initial support for Neon scalar instructions.
Patch by Ana Pazos.
1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-add-pairwise.s
Arch64/neon-add-sub-instructions.s
Arch64/neon-diagnostics.s
Arch64/neon-rounding-shift.s
Arch64/neon-saturating-add-sub.s
Arch64/neon-saturating-rounding-shift.s
Arch64/neon-saturating-shift.s
Arch64/neon-scalar-add-sub.s
Arch64/neon-scalar-reduce-pairwise.s
Arch64/neon-scalar-rounding-shift.s
Arch64/neon-scalar-saturating-add-sub.s
Arch64/neon-scalar-saturating-rounding-shift.s
Arch64/neon-scalar-saturating-shift.s
Arch64/neon-scalar-shift.s
Arch64/neon-shift.s
|
| 7d7db75a55319f1d21f0d8336744f90a81b87ac7 |
22-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
X86: Use R_X86_64_TPOFF64 for FK_Data_8
Summary:
LLVM would crash when trying to come up with a relocation type for
assembly like:
movabsq $V@TPOFF, %rax
Instead, we say the relocation type is R_X86_64_TPOFF64.
Fixes PR17274.
Reviewers: dblaikie, nrieck, rafael
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191163 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 60c81c939755601931bea8dbde174ff52cd904dd |
21-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
ELF: Parse types in directives like binutils gas
Allow binutils .type and .section directives to take the following
forms:
- @<type>
- %<type>
- "<type>"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191134 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
LF/type.s
|
| 5df37dab763ce377095389c4ea1cff88db369954 |
19-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARMv8] Add support for the v8 cryptography extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
RM/invalid-neon-v8.s
RM/neon-crypto.s
RM/thumb-invalid-crypto.txt
RM/thumb-neon-crypto.s
isassembler/ARM/neon-crypto.txt
isassembler/ARM/thumb-neon-crypto.txt
|
| e2d6f91d63a2e8cf77b07794cda7d9ef72504769 |
18-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add unsigned compare-and-branch instructions
For some reason I never got around to adding these at the same time as
the signed versions. No idea why.
I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether
it should just be replaced with an "is normal" flag. I'll leave that
for later though.
There are some boundary conditions that can be tweaked, such as preferring
unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256",
but again I'll leave those for a separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190930 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns-pcrel.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 8634b0ee47be832fbf3fd6ceebb8ac9104106bc2 |
18-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
'svn add' the test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190929 91177308-0d34-0410-b5e6-96231b3b80d8
RM/crc32-thumb.s
RM/crc32.s
RM/invalid-crc32.s
isassembler/ARM/crc32-thumb.txt
isassembler/ARM/crc32.txt
|
| 28860823ad34d41d4f58561dc14a982fb0843fdd |
18-Sep-2013 |
Reid Kleckner <reid@kleckner.net> |
COFF: Ensure that objects produced by LLVM link with /safeseh
Summary:
We indicate that the object files are safe by emitting a @feat.00
absolute address symbol. The address is presumably interpreted as a
bitfield of features that the compiler would like to enable. Bit 0 is
documented in the PE COFF spec to opt in to "registered SEH", which is
what /safeseh enables.
LLVM's object files are safe by default because LLVM doesn't know how to
produce SEH handlers.
Reviewers: Bigcheese
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190898 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/feat00.s
|
| 3168868bb91ac871dbb83c879e763d39a39e607e |
17-Sep-2013 |
Reid Kleckner <reid@kleckner.net> |
COFF: Emit all MCSymbols rather than filtering out some of them
In particular, this means we emit non-external symbols defined to
variables, such as aliases or absolute addresses.
This is needed to implement /safeseh, and it appears there was some
confusion about what symbols to emit previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190888 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/alias.s
|
| dc0de80f24a83336cb26dcb9ed1fa030142a504d |
17-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190862 91177308-0d34-0410-b5e6-96231b3b80d8
RM/deprecated-v8.s
|
| e54360be01d1eaccd5ef27f510634927aaa887a4 |
17-Sep-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement 3 AArch64 neon instructions : umov smov ins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-simd-copy.s
|
| e925f7dbbf497412cd0cc3f67b9b96fed0cc3712 |
16-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| 766f25306af343fb2784350cb4d8cd9ca180f0d3 |
15-Sep-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
ELF: Add support for the exclude section bit for gas compat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190769 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| bcd9b3b6b119420edffd259e5e05c5e0cf5fbc6c |
15-Sep-2013 |
David Majnemer <david.majnemer@gmail.com> |
MC: Add support for '?' flags in .section directives
Summary:
The '?' flag uses the last section group if the last had a section
group. We treat combining an explicit section group and the '?' as a
hard error.
This fixes PR17198.
Reviewers: rafael, bkramer
Reviewed By: bkramer
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190768 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comdat.s
|
| c29a720b362790746ca899a0b44fa35a1b399a42 |
15-Sep-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Fix alignment of unwind data.
For alignment purposes, the instruction array will always have an even
number of entries, with the final entry potentially unused (in which
case the array will be one longer than indicated by the count of unwind
codes field).
Reviewed by Anton Korobeynikov, Charles Davis and Nico Rieck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190767 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh-align1.s
OFF/seh-align2.s
OFF/seh-align3.s
|
| 7185bdd88302a67618b2edf51c499d647e5ff492 |
15-Sep-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH
data structures.
The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB
instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding
the VK_COFF_IMGREL32 modifier to the symbol reference.
Change also references to start and end of the SEH range of a function
as offsets to start of the function.
Reviewed by Jim Grosbach, Charles Davis and Nico Rieck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190766 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| a247e9d42b03851be8425631e2716d4ff9f37c47 |
14-Sep-2013 |
Ben Langmuir <ben.langmuir@intel.com> |
Add the remaining Intel SHA instructions
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
86/x86_64-encoding.s
|
| dcc425c6301c088b4c0598696de50c01fbca5733 |
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Fixed bug when generating Load Upper Immediate microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
ips/micromips-alu-instructions.s
|
| ab48d10effb223de0c9516ccae616a80fef27df8 |
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS DIV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
ips/micromips-alu-instructions.s
|
| 47b33528d1b4298bf8cc5dcca8b531dfd0e704bb |
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for misc microMIPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
|
| 489b9b348dab51243f93d2f4bdd107c9db077609 |
13-Sep-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
Fix tests for hasFPARMv8 name change (r190692)
Patch by Bradley Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190694 91177308-0d34-0410-b5e6-96231b3b80d8
RM/fp-armv8.s
RM/invalid-fp-armv8.s
RM/invalid-v8fp.s
RM/thumb-fp-armv8.s
RM/thumb-v8fp.s
RM/v8fp.s
isassembler/ARM/fp-armv8.txt
isassembler/ARM/thumb-fp-armv8.txt
isassembler/ARM/thumb-v8fp.txt
isassembler/ARM/v8fp.txt
|
| 2a9af9f18eac90b0de739b6ceddf6c2209086303 |
13-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options
to be more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
RM/invalid-neon-v8.s
|
| 630c5e06d633fad142af4b145ee684e90754700e |
13-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: use RegisterOperand for NEON registers.
Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.
The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-mov.s
isassembler/AArch64/neon-instructions.txt
|
| ba7183bc5284a0e4254ad12b78e2ea61e291dd88 |
12-Sep-2013 |
Roman Divacky <rdivacky@freebsd.org> |
Implement asm support for a few PowerPC bookIII that are needed for assembling
FreeBSD kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190618 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookIII.s
|
| 1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f |
12-Sep-2013 |
Ben Langmuir <ben.langmuir@intel.com> |
Partial support for Intel SHA Extensions (sha1rnds4)
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.
Support for the remaining instructions will follow in a separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
86/x86_64-encoding.s
|
| c0b12dfd0a83081c1ebbb55a89c7a2c1f98f1842 |
12-Sep-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark PPC MFTB and DST (and friends) as deprecated
Use the new instruction deprecation feature to mark mftb (now replaced with
mfspr) and dst (along with the other Altivec cache control instructions) as
deprecated when targeting cores supporting at least ISA v2.03.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/deprecated-p7.s
|
| 25d25832d550c1844d27d2034cec1c8d507fa689 |
12-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
Somehow this important part of the patch, where I actually check the Mask,
got lost during my iterations of review.
Thanks to Hal for spotting it!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190604 91177308-0d34-0410-b5e6-96231b3b80d8
RM/deprecated-v8.s
|
| 715d98d657491b3fb8ea0e14643e9801b2f9628c |
12-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
RM/deprecated-v8.s
|
| f9d2d2dc89f0c2d39f597038ee723fb9c9af91da |
12-Sep-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: implemented extractelement with variable index.
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
86/avx512-encodings.s
|
| 299fdd814f4c2850d44387d24c440980c5377d3e |
10-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add TM and TMY
The main complication here is that TM and TMY (the memory forms) set
CC differently from the register forms. When the tested bits contain
some 0s and some 1s, the register forms set CC to 1 or 2 based on the
value the uppermost bit. The memory forms instead set CC to 1
regardless of the uppermost bit.
Until now, I've tried to make it so that a branch never tests for an
impossible CC value. E.g. NR only sets CC to 0 or 1, so branches on the
result will only test for 0 or 1. Originally I'd tried to do the same
thing for TM and TMY by using custom matching code in ISelDAGToDAG.
That ended up being very ugly though, and would have meant duplicating
some of the chain checks that the common isel code does.
I've therefore gone for the simpler alternative of adding an extra
operand to the TM DAG opcode to say whether a memory form would be OK.
This means that the inverse of a "TM;JE" is "TM;JNE" rather than the
more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE".
I suppose that's arguably less confusing though...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190400 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| b15da6dc09fdf2699146cd4317f3a43e70397553 |
10-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| 959cd8f49bb85c8dfe971eb5a8a648ff41ca8ebd |
09-Sep-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-3vdiff.s
Arch64/neon-diagnostics.s
isassembler/AArch64/neon-instructions.txt
|
| 1abf0afdd4d8e9d58518a878f30b9eede81303cc |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of instruction "drotr32" (double rotate right plus 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips64-alu-instructions.s
|
| 77e1ebd18fc558620b97fe38f3ebbf825533655f |
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Set instruction itineraries of loads, stores and conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
ips/xgot.ll
|
| 638382e6f169649eb86fa47a6ea25dd932f07689 |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
ips/micromips-multiply-instructions.s
|
| dadd1fba3280295936f556acbdc3fbb68b496bad |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
|
| bf7f7b5e0eae40bb47a410c90f9f0885c0f38b2c |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
ips/micromips-movcond-instructions.s
|
| a674463aac1d0b5d039da11045ccfab5e849b886 |
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS disassembler and disassembler make check tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/micromips.txt
isassembler/Mips/micromips_le.txt
|
| d8e2f1757d9ececd7937406596fec8e4ebfb7d46 |
05-Sep-2013 |
Kevin Enderby <enderby@apple.com> |
Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment. Â In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.
rdar://9356266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190096 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-diff-reloc-assign-2.s
|
| ed119820f223401b0c64769759eafc46de30a9da |
05-Sep-2013 |
Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> |
Improve handling of .file, .include and .incbin directives to
allow escaped octal character sequences.
The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190089 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_file.s
smParser/directive_incbin.s
smParser/directive_include.s
|
| 67990fa3ba3b0d61f7f94cadfebd7c78ed8f6a71 |
05-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add some missing tests for DSB/DMB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190060 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions-v8.s
isassembler/ARM/basic-arm-instructions-v8.txt
isassembler/ARM/thumb-v8.txt
|
| 4897151df698197f0eb5c4085545312dbb20c94d |
05-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions-v8.s
|
| b5523ce1bb50e86942ad5273e3a89872c4d26b73 |
05-Sep-2013 |
Richard Barton <richard.barton@arm.com> |
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions-v8.s
RM/basic-thumb2-instructions-v8.s
RM/diagnostics.s
RM/thumb-diagnostics.s
isassembler/ARM/basic-arm-instructions-v8.txt
isassembler/ARM/thumb-v8.txt
|
| 16277c4698f36a756c540fae326874774156aaed |
05-Sep-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 19fdc268c316b3b0bdcb2b558449819f4f402d6a |
04-Sep-2013 |
Hao Liu <Hao.Liu@arm.com> |
Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
and 4 convert instructions:
scvtf,ucvtf,fcvtzs,fcvtzu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-simd-shift.s
isassembler/AArch64/neon-instructions.txt
|
| d4b3168609d4a6dfb8a948d87dc61f83855ac604 |
30-Aug-2013 |
Richard Mitton <richard@codersnotes.com> |
Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189698 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/prefixes.txt
|
| e54726a87a49e3254696b05787f4635dc59fe750 |
29-Aug-2013 |
Kevin Enderby <enderby@apple.com> |
The darwin integrated assembler for X86 in 64-bit mode is not rejecting
32-bit absolute addressing in instructions likei this:
mov $_f, %rsi
which is not supported in 64-bit mode.
rdar://8827134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189543 91177308-0d34-0410-b5e6-96231b3b80d8
achO/bad-darwin-x86_64-32-bit-abs-addr.s
|
| 4f066b6db8a7a95b206725aecf99a64fd6e9415c |
28-Aug-2013 |
Kevin Enderby <enderby@apple.com> |
The integrated darwin assembler can hang in an infinite loop (or get an assert
with a debug build) with this buggy .indirect_symbol directive usage:
% cat test.s
x: .indirect_symbol _y
The assertion is because it is trying to get the symbol index for the
symbol _y when it is writing out the indirect symbol table. This line of
code in MachObjectWriter::WriteObject() :
Write32(Asm.getSymbolData(*it->Symbol).getIndex());
And while there is a symbol _y it does not have any getSymbolData set which
is only done in MachObjectWriter::BindIndirectSymbols() for pointer sections
or stub sections. I added a check and an error in there to catch this in case
something slips through.
But to get a better error the parser should detect when a .indirect_symbol
directive is used and it is not in a pointer section or stub section. To make
that work I moved the handling of the indirect symbol out of the target
independent AsmParser code into the DarwinAsmParser code that can check
for the proper Mach-O section types.
rdar://14825505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189497 91177308-0d34-0410-b5e6-96231b3b80d8
achO/bad-indirect-symbols.s
|
| b2e5453821ef27306036a9961818cf530a3ca8cb |
28-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8]
Fix a few things in one swoop.
# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
RM/load-store-acquire-release-v8-thumb.s
RM/load-store-acquire-release-v8.s
|
| 477168192c98e1f75a5bc6db3d34a177f327bd34 |
28-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add support for TMHH, TMHL, TMLH and TMLL
For now just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189469 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| a796d90c0ed7ebd5d58fced43c60afc2e9bf6225 |
28-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips-dsp.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
ips/mips-dsp-instructions.s
ips/mips-fpu-instructions.s
ips/mips64-instructions.s
|
| 7cde9d0286a8976feebb20e61612fb999527f630 |
27-Aug-2013 |
David Majnemer <david.majnemer@gmail.com> |
[ms-inline asm] Support offsets after segment registers
Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'
Reviewers: craig.topper, rnk
Reviewed By: rnk
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189407 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 66b7139b1be1ddce410d97499d5831231c6be267 |
27-Aug-2013 |
Joerg Sonnenberger <joerg@bec.de> |
Given target assembler parsers a chance to handle variant expressions
first. Use this to turn the PPC modifiers into PPC specific expressions,
allowing them to work on constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189400 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-errors.s
owerPC/ppc64-fixups.s
|
| 0b90c6223d9c49b5e0dc4bf4e53796b0714d7b80 |
27-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add MC support for the new load/store acquire/release instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
RM/load-store-acquire-release-v8-thumb.s
RM/load-store-acquire-release-v8.s
isassembler/ARM/load-store-acquire-release-v8-thumb.txt
isassembler/ARM/load-store-acquire-release-v8.txt
|
| dcfa0f7a408e54f15f0237daf2336df852053c6b |
27-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add some negative tests for the recent VFP/NEON instructions.
Fix two issues I found while writing these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8
RM/invalid-neon-v8.s
RM/invalid-v8fp.s
|
| f0a0d578089572be37063bbe37063edb28148159 |
27-Aug-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Fix wrong code offset for unwind code SET_FPREG.
The code offset for unwind code SET_FPREG is wrong because it is set
to constant 0. The fix is to do the same as for the other unwind
codes: emit a label and later the absolute difference between the
label and the begin of the prologue.
Also enables the failing test case MC/COFF/seh.s
Reviewed by Jim Grosbach, Charles Davis and Nico Rieck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189309 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| e4bf77a1282bfdacb61bae192fdf79a696be780a |
26-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements trap instructions for mips. The test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-control-instructions.s
|
| a4959f3f6eb9b6ab3cbbe085a2797208682e96c6 |
26-Aug-2013 |
Craig Topper <craig.topper@gmail.com> |
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.
Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189201 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax-32.txt
isassembler/X86/intel-syntax.txt
isassembler/X86/x86-32.txt
|
| a550b51bac50493db75a7b5788a3f2c3b62fd913 |
23-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add basic prefetch support
Just the instructions and intrinsics for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189100 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns-pcrel.txt
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 5f268555b967fccbfab6e7b69305d74006116927 |
22-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix ARM vcvt encoding when the number of fractional bits is zero.
The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions.
This patch adds the necessary instruction aliases to achieve this behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-convert-encoding.s
|
| 1a9f21abac47dcea0c62341b0ee4fd35481350b8 |
21-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8ba76daba09e79b10c4aad8f4298433c6dafa6d5 |
21-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: Added SHIFT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899 91177308-0d34-0410-b5e6-96231b3b80d8
86/avx512-encodings.s
|
| d954716e7567282ff6f3d25b4f404bae006eed04 |
21-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add FI[EDX]BRA
These are extensions of the existing FI[EDX]BR instructions, but use a spare
bit to suppress inexact conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188894 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| d22b327b3d8fafade61fa2b4aaba5c9f3ee10d4d |
21-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[micromips] Print instruction alias "not" if the last operand of a nor is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188851 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-alu-instructions.s
|
| 93877b3cbcefc0f281b744b135d609d35c3f119c |
20-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-alu-instructions.s
|
| 1e09ed13893ad9d463c6c08c996170bac6e60449 |
19-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188690 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| 756e89c8c2a3c30ce3a73ed13724aad1b41a5608 |
19-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Thumb2 add immediate alias for SP
The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction.
All the patch does is adjust a register constraint on an instruction alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188676 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d4a37e61378949835d93df6b8e4a9feadb4edeef |
19-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add negative integer absolute (load negative)
For now this matches the equivalent of (neg (abs ...)), which did hit a few
times in projects/test-suite. We should probably also match cases where
absolute-like selects are used with reversed arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188671 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-good.s
|
| b0d40a22e5aa1a51913fa161c2ce5513d7bd9293 |
19-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add integer absolute (load positive)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188670 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-good.s
|
| 953a78084b85ea88cd2b208153a72df70e27133f |
19-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use
this to lower the FCOPYSIGN node (which is created from calls to the libm
copysign function). A couple of extra patterns are necessary because the
operand types of FCOPYSIGN need not agree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188653 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-fp.s
|
| e97fc44045732de9fc4715241013f9238ec007dc |
16-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Add support for Thumb2 literal loads with negative zero offset
Thumb2 literal loads use an offset encoding which allows for
negative zero. This fixes parsing and encoding so that #-0
is correctly processed. The parser represents #-0 as INT32_MIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188549 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8b36f9e4314ac4d786d2d4fd5fa9e7858487ee9e |
16-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix Thumb2 aliasing complementary instructions taking modified immediates
There are many Thumb instructions which take 12-bit immediates encoded in a special
8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal
to transform an assembly instruction to be able to encode the immediate.
For example: AND and BIC are complementary instructions; one can switch the AND
to a BIC as long as the immediate is complemented.
The intent is to switch one instruction into its complementary one when the immediate
cannot be encoded in the form requested in the original assembly and when the
complementary immediate is encodable.
The patch addresses two issues:
1. definition of t2SOImmNot immediate - it has to check that the orignal value is
not encoded naturally
2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand
rather than the ARM one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188548 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 19262ee0725a09b7c621a3d2eb66ba1513ae932a |
16-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use SRST to implement strlen and strnlen
It would also make sense to use it for memchr; I'm working on that now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188547 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-good.s
|
| 4fc7355a21e1fa838406e15459aaf54a58fcf909 |
16-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use MVST to implement strcpy and stpcpy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188546 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-good.s
|
| e1b2af731e2a45344a7c502232f66c55cd746da0 |
16-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Use CLST to implement strcmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188544 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-good.s
|
| 6f297afb7ea6ab53be1feae4a335e7b1cb7a1f02 |
16-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements wait instruction for mips. Examples are added in test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188537 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-control-instructions.s
|
| 24ec2e5a72d7fca58f8ae2b3c01501a9927ef04e |
16-Aug-2013 |
Daniel Dunbar <daniel@zuster.org> |
[tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
list in the top-level config. We now only modify the suffix list in a few
suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).
- Aside from removing the need for a bunch of lit.local.cfg files, this enables
4 tests that were inadvertently being skipped (one in
Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
XFAILED).
- This commit also fixes a bunch of config files to use config.root instead of
older copy-pasted code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/lit.local.cfg
RM/AlignedBundling/lit.local.cfg
RM/lit.local.cfg
smParser/lit.local.cfg
OFF/lit.local.cfg
isassembler/AArch64/lit.local.cfg
isassembler/ARM/lit.local.cfg
isassembler/Mips/lit.local.cfg
isassembler/SystemZ/lit.local.cfg
isassembler/X86/lit.local.cfg
isassembler/XCore/lit.local.cfg
LF/lit.local.cfg
achO/ARM/lit.local.cfg
achO/lit.local.cfg
ips/lit.local.cfg
owerPC/lit.local.cfg
ystemZ/lit.local.cfg
86/AlignedBundling/lit.local.cfg
86/lit.local.cfg
|
| 428715d4e120e6ef6fc898665607a92f3dd02709 |
15-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb-diagnostics.s
|
| d9767021f83879429e930b068d1d6aef22285b33 |
15-Aug-2013 |
Hao Liu <Hao.Liu@arm.com> |
Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/neon-diagnostics.s
Arch64/neon-shift-left-long.s
Arch64/neon-shift.s
isassembler/AArch64/neon-instructions.txt
|
| 73cd0c844ba6c46ddb94405ee28246f084a13a12 |
14-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
Add test-case for hex floating-literals
Somehow I forgot to test one of the error conditions I'd added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188372 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| 337439d12d2e2a9e820e0aeee261bbdb935fc0a5 |
14-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
Support C99 hexadecimal floating-point literals in assembly
It's useful to be able to write down floating-point numbers without having to
worry about what they'll be rounded to (as C99 discovered), this extends that
ability to the MC assembly parsers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188370 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| 899ee589f5182a35495f068ae15b5f2b5ff4ef8a |
14-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix bug in parsing accumulator registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188344 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-dsp-instructions.s
|
| da0860f78e6e43aca3333a7815b2f9bc0f8dfac0 |
13-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-loadstore-unaligned.s
|
| 3f87f2510c0d84fe092ac311a0e25a5e2f7aa3ac |
13-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
ARMv8: SWP and SWPB are obsoleted on ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188288 91177308-0d34-0410-b5e6-96231b3b80d8
RM/obsolete-v8.s
|
| ea8ddd86b1e364a799e57fc0ac468a9c4a8f8bcf |
13-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix signed overflow in when computing encodings for ADR instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 6aa9315353574c000c5f2aa0edd34067e94b8c79 |
13-Aug-2013 |
David Majnemer <david.majnemer@gmail.com> |
[-cxx-abi microsoft] Stick zero initialized symbols into the .bss section for COFF
Summary:
We need to do two things:
- Initialize BSSSection in MCObjectFileInfo::InitCOFFMCObjectFileInfo
- Teach TargetLoweringObjectFileCOFF::SelectSectionForGlobal what to do
with it
This fixes PR16861.
Reviewers: rnk
Reviewed By: rnk
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188244 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/bss_section.ll
|
| ebc573ed5b7d4757d58b3bfdec53fcf9b4cb8c01 |
13-Aug-2013 |
Kevin Enderby <enderby@apple.com> |
Fix a crash with X86 Mach-O and a subtraction expression where both symbols are
undefined and produce an error message instead as this is a non-relocatable
expression with X86 Mach-O.
rdar://8920876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188218 91177308-0d34-0410-b5e6-96231b3b80d8
achO/bad-darwin-x86_64-diff-relocs.s
|
| 809313970fc98bba6f36a332adfa3e5fef4110b3 |
12-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements ei and di instructions for mips. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188176 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-control-instructions.s
|
| dcef6a7400d51526a04a18e274bd579da262e9ad |
12-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
Fix FileCheck --check-prefix lines.
Various tests had sprung up over the years which had --check-prefix=ABC on the
RUN line, but "CHECK-ABC:" later on. This happened to work before, but was
strictly incorrect. FileCheck is getting stricter soon though.
Patch by Ron Ofir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188173 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-explicit.s
owerPC/ppc64-fixups.s
|
| e03a56d62fc623e2f72d623b816f91b293d5904b |
12-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add a definition of the CLC instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188162 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| f37c8feb468a0e1876c08bdeb449bdb5999c0534 |
12-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add a definition of the IPM instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188161 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-good.s
|
| 0a69bac39607c1f715835d951a6deb1c7ecbedfe |
10-Aug-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Check for $PWD in llvm::sys::current_path.
Some users (clang, libTooling) require this. After this patch we can remove
the calls to getenv("PWD") from clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188125 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comp-dir.s
|
| 04b03fac11f10c92cf7ce63ba2f548a42ee2c448 |
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This fixes the Thumb2 CPS assembly syntax.
In Thumb1, only one variant is supported: CPS{effect} {flags}
Thumb2 supports three:
CPS{effect}.W {flags}
CPS{effect} {flags} {mode}
CPS {mode}
Canonically, .W should be used only when ambiguity is present between encodings of different width.
The wide suffix is still accepted for the latter two forms via aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188071 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/basic-thumb2-instructions.s
isassembler/ARM/thumb-tests.txt
|
| e921f323533ee751b3fa34bd00d10fa72096ffd3 |
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.
Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.
Due to this, for any mnemonic there are really 4 encodings to choose for.
The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that
order is governed by the lexicographical ordering of the names of operand
classes...
To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/basic-thumb2-instructions.s
RM/thumb-diagnostics.s
RM/thumb2-b.w-encodingT4.s
RM/thumb2-branches.s
RM/thumb2-diagnostics.s
|
| d12fce1a27c30292dcd5f5bc10d4ba6e742888be |
09-Aug-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips ELF: MicroMips direct object Little endian support.
Test included.
Patch by Zoran Jovanovich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188024 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-alu-instructions.s
ips/micromips-loadstore-instructions.s
ips/micromips-shift-instructions.s
|
| 9706d43b56e16eb3029314e02c499305284e99f1 |
08-Aug-2013 |
David Majnemer <david.majnemer@gmail.com> |
Revert "coff also doesn't have a ReadOnlySection yet, (!)"
This reverts commit r77814.
We were sticking global constants in the .data section instead of in the
.rdata section when emitting for COFF.
This fixes PR16831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187956 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/rdata.ll
|
| 10251753b6897adcd22cc981c0cc42f348c109de |
07-Aug-2013 |
Eric Christopher <echristo@gmail.com> |
Using the integrated assembler we'd fail to change section to the
.tbss section for zerofill thread locals. Make sure we do this
before emitting the zerofills.
Fixes PR15972.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187913 91177308-0d34-0410-b5e6-96231b3b80d8
achO/tlv-bss.ll
|
| e0bbf7288c00c377a97a9d4bf5fb0bf20c44cd1c |
07-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 4f7092176c3d3eaae0ea7af26aec2d77b3e4035f |
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
RM/thumb2-pldw.s
|
| 4a378b95aa0f24ba461e512608b8aaeaa803996f |
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| ccdf5cc7bc443726425dd1ad498d44768332d49c |
05-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add definitions for BRCT and BRCTG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187721 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns-pcrel.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 0e4044c233d10596578df35bae2483fbe4e8a507 |
05-Aug-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support. The next patch uses them for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187719 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 787fdb86a71c5108c231b3bbbb7d3fea3ce4bb8c |
02-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add an assembler warning for the deprecated 'setend' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187666 91177308-0d34-0410-b5e6-96231b3b80d8
RM/deprecated-v8.s
|
| 0780179d532d20b6b01ba0f1434c93f81b7faea8 |
01-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
EVEX and compressed displacement encoding for AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
86/avx512-encodings.s
|
| a701de8d2433eac2033916ae6c1bc277415aefd4 |
01-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add tests for Mips DSP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187570 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-dsp-instructions.s
|
| 87773c318fcee853fb34a80a10c4347d523bdafb |
01-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: add initial NEON support
Patch by Ana Pazos.
- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise
- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic
- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same
- Intial implementation of instruction class:
Scalar Arithmetic
- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.
- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-a64-diagnostics.s
Arch64/basic-a64-instructions.s
Arch64/neon-aba-abd.s
Arch64/neon-add-pairwise.s
Arch64/neon-add-sub-instructions.s
Arch64/neon-bitwise-instructions.s
Arch64/neon-compare-instructions.s
Arch64/neon-diagnostics.s
Arch64/neon-facge-facgt.s
Arch64/neon-frsqrt-frecp.s
Arch64/neon-halving-add-sub.s
Arch64/neon-max-min-pairwise.s
Arch64/neon-max-min.s
Arch64/neon-mla-mls-instructions.s
Arch64/neon-mov.s
Arch64/neon-mul-div-instructions.s
Arch64/neon-rounding-halving-add.s
Arch64/neon-rounding-shift.s
Arch64/neon-saturating-add-sub.s
Arch64/neon-saturating-rounding-shift.s
Arch64/neon-saturating-shift.s
Arch64/neon-shift.s
Arch64/noneon-diagnostics.s
isassembler/AArch64/neon-instructions.txt
|
| e38070fc32818a6e412dafbb8b3807b413d0819e |
31-Jul-2013 |
Kevin Enderby <enderby@apple.com> |
Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match. Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.
rdar://14214063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
isassembler/ARM/thumb2.txt
|
| f3068d02e5f55d7e69134c8f14aa21c4b9fde91a |
31-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187490 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| 418eb3df746816293dd013b82264f43e501ec093 |
31-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
|
| b67775df0cc702cd94408200ff2d58cf83f1334a |
30-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| fdbea5107b5a8249421fd5e603a31f40f05ea25f |
29-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use proper section suffix for COFF weak symbols
32-bit symbols have "_" as global prefix, but when forming the name of
COMDAT sections this prefix is ignored. The current behavior assumes that
this prefix is always present which is not the case for 64-bit and names
are truncated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187356 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/weak-symbol-section-specification.ll
OFF/weak-symbol.ll
|
| c63dce3c59ac24b2656e06f7017cd4dce4bf733c |
29-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
MC: Support larger COFF string tables
Single-slash encoded entries do not require a terminating null. This bumps
the maximum table size from ~1MB to ~9.5MB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187352 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/section-name-encoding.s
|
| 407883b69b3bc10ebf053f5922d877b2e786d124 |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
|
| 83d8ef133b121b7e752e7468cb1e0e5e3b636aee |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP branch instructions to have explicit FP condition code register
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| 9b06dd6ca25fd1f8d2cf9227fdffc304c9f51564 |
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.
beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or $2, $3, $zero => move $2, $3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32_le.txt
ips/mips-alu-instructions.s
ips/mips-jump-instructions.s
|
| 6ee1464ba599f1afbed502fa1b3ac18c8577fd97 |
26-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187188 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
86/x86-32-coverage.s
86/x86-64.s
|
| 6fccaafd8be0eb7619b5a210387b0d1254ef4174 |
25-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove the mblaze backend from llvm.
Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187145 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MBlaze/lit.local.cfg
isassembler/MBlaze/mblaze_branch.txt
isassembler/MBlaze/mblaze_fpu.txt
isassembler/MBlaze/mblaze_fsl.txt
isassembler/MBlaze/mblaze_imm.txt
isassembler/MBlaze/mblaze_mbar.txt
isassembler/MBlaze/mblaze_memory.txt
isassembler/MBlaze/mblaze_operands.txt
isassembler/MBlaze/mblaze_pattern.txt
isassembler/MBlaze/mblaze_shift.txt
isassembler/MBlaze/mblaze_special.txt
isassembler/MBlaze/mblaze_typea.txt
isassembler/MBlaze/mblaze_typeb.txt
Blaze/lit.local.cfg
Blaze/mblaze_branch.s
Blaze/mblaze_fpu.s
Blaze/mblaze_fsl.s
Blaze/mblaze_imm.s
Blaze/mblaze_memory.s
Blaze/mblaze_operands.s
Blaze/mblaze_pattern.s
Blaze/mblaze_shift.s
Blaze/mblaze_special.s
Blaze/mblaze_typea.s
Blaze/mblaze_typeb.s
|
| bf99364f819465536a6b230b95735b239e3fc7a5 |
25-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add LOCR and LOCGR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187113 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-good-z196.s
|
| cf20e45cc4cb77bcb16363531e600883cd27ff80 |
25-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187112 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-good-z196.s
|
| b284e1bf08d24deb20b7deab71fce6f3034cc89a |
25-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187111 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-good-z196.s
|
| 113034596c30c4a0eba2005772d16849695bf67d |
23-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add not so that these tests pass with pipefail enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186939 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-armv7.txt
isassembler/ARM/invalid-because-armv7.txt
isassembler/ARM/invalid-thumbv7.txt
|
| 9b8b830f3fa6dca2275dcd86bdaf0d78ab1651a1 |
23-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
86/x86-32.s
86/x86-64.s
|
| 877d123bdb0198705884e4ca7980d2ab845d9888 |
22-Jul-2013 |
Kevin Enderby <enderby@apple.com> |
Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.
rdar://8612627 and rdar://14299221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
86/x86-64.s
|
| 4e3170b63a31c515644846ce7a77631429d93050 |
22-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 9a05b98ef9ec58c52f35ce04677f24ef62a79701 |
22-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186861 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| 0b926427670de6e0ed855ef93f220a3f51ed1eab |
22-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
|
| 02265382929b0275d7b7b334eab5e2fd34e1b9fe |
22-Jul-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:
1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 6dae7ae7659444efc2149852e366ba97d3a6e449 |
19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add tests for ALHSIK and ALGHSIK
The insn definitions themselves crept into r186689, sorry.
This should be the last of the distinct-ops instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186690 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| c7c7e1502a62123a5e54fe6ff7da490bf26d319e |
19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186689 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| 6fec715a1a662ce3b560f85c710875cfeeb1fb98 |
19-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186688 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-v8.s
RM/thumb-neon-v8.s
isassembler/ARM/neon-v8.txt
isassembler/ARM/thumb-neon-v8.txt
|
| 70d3e71f2e44250594f1b6edd7bbbf8b945a4452 |
19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add AHIK and AGHIK
I did these as a separate patch because it uses a slightly different
form of RIE layout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186687 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| dc05e0bff67f818e615a47e831ff92d65ee0ac64 |
19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186686 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| 52b2774577e07fbf804e4d647119578df4111f21 |
19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add NGRK, OGRK and XGRK
Like r186683, but for 64 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186685 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| db92fb07169af6941dfe47439f9849d370f0eb0b |
19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.
Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried). Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186683 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
|
| cae5d5ea658e05091e66b742b5834f1896ff2f5d |
19-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.
See A8.8.127 in ARM DDI 0406C.b.
Related to <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186682 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb2-pldw.s
|
| eddfaad1ef9a208a8a9ee23c26fac4d980caa99a |
19-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.
insn-bad.s tests that some form of error is reported when using these
instructions on z10. More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186680 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad-z196.s
ystemZ/insn-bad.s
ystemZ/insn-good-z196.s
ystemZ/insn-good.s
|
| 914bc14e7bdc4e6c37c0b651139e34588a1b395f |
19-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: delete two tests now integrated into the larger files
Somehow forgot to git rm these two files. I believe I left the remaining
invalid* tests intentionally, though whether my reasons were sound is a
different matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186663 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-Bcc-thumb.txt
isassembler/ARM/invalid-MOVs-LSL-arm.txt
|
| 29cc13892d9215b0e7eeb5adf0e16064ac4156ec |
19-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: remove invalid invalid tests
The tests were checking for barriers which the ARM ARM says they must execute
as a full system DMB/DSB, rather than that they're UNDEFINED and LLVM does in
fact represent them.
The tests happened to be passing because they were using a non-versioned ARM
triple which didn't have *any* DMB/DSB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186662 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-DMB-thumb.txt
isassembler/ARM/invalid-DSB-arm.txt
|
| 38c6ff6c111fcc53debb9e2880f89e2dd0676217 |
19-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
Improve llvm-mc disassembler mode and refactor ARM tests to use it
This allows "llvm-mc -disassemble" to accept two new features:
+ Using comma as a byte separator
+ Grouping bytes with '[' and ']' pairs.
The behaviour outside a [...] group is unchanged. But within the group once
llvm-mc encounters a true error, it stops rather than trying to resynchronise
the stream at the next byte. This is more useful for disassembly tests, where
we have an almost-instruction in mind and don't care what the misaligned
interpretation would be. Particularly if it means llvm-mc won't actually see
the next intended almost-instruction.
As a side effect, this means llvm-mc can disassemble its own -show-encoding
output if copy-pasted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186661 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-BFI-arm.txt
isassembler/ARM/invalid-CDP2-arm.txt
isassembler/ARM/invalid-CPS-arm.txt
isassembler/ARM/invalid-CPS2p-arm.txt
isassembler/ARM/invalid-CPS3p-arm.txt
isassembler/ARM/invalid-IT-CBNZ-thumb.txt
isassembler/ARM/invalid-IT-thumb.txt
isassembler/ARM/invalid-LDC-form-arm.txt
isassembler/ARM/invalid-LDM-thumb.txt
isassembler/ARM/invalid-LDR-thumb.txt
isassembler/ARM/invalid-LDRB_POST-arm.txt
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
isassembler/ARM/invalid-LDR_POST-arm.txt
isassembler/ARM/invalid-LDR_PRE-arm.txt
isassembler/ARM/invalid-LDRrs-arm.txt
isassembler/ARM/invalid-MCR-arm.txt
isassembler/ARM/invalid-MOVTi16-arm.txt
isassembler/ARM/invalid-MOVr-arm.txt
isassembler/ARM/invalid-MOVs-arm.txt
isassembler/ARM/invalid-MRRC2-arm.txt
isassembler/ARM/invalid-MSRi-arm.txt
isassembler/ARM/invalid-NEON-thumb.txt
isassembler/ARM/invalid-RFEorLDMIA-arm.txt
isassembler/ARM/invalid-SBFX-arm.txt
isassembler/ARM/invalid-SMLAD-arm.txt
isassembler/ARM/invalid-SRS-arm.txt
isassembler/ARM/invalid-STMIA_UPD-thumb.txt
isassembler/ARM/invalid-STR-thumb.txt
isassembler/ARM/invalid-SXTB-arm.txt
isassembler/ARM/invalid-UMAAL-arm.txt
isassembler/ARM/invalid-VCVT-arm.txt
isassembler/ARM/invalid-VEXTd-arm.txt
isassembler/ARM/invalid-VFP-thumb.txt
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt
isassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
isassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt
isassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt
isassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
isassembler/ARM/invalid-VLDST-arm.txt
isassembler/ARM/invalid-VMOV-arm.txt
isassembler/ARM/invalid-VQADD-arm.txt
isassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt
isassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
isassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt
isassembler/ARM/invalid-armv7.txt
isassembler/ARM/invalid-because-armv7.txt
isassembler/ARM/invalid-hint-arm.txt
isassembler/ARM/invalid-hint-thumb.txt
isassembler/ARM/invalid-t2Bcc-thumb.txt
isassembler/ARM/invalid-t2LDRBT-thumb.txt
isassembler/ARM/invalid-t2LDREXD-thumb.txt
isassembler/ARM/invalid-t2LDRSHi12-thumb.txt
isassembler/ARM/invalid-t2LDRSHi8-thumb.txt
isassembler/ARM/invalid-t2PUSH-thumb.txt
isassembler/ARM/invalid-t2STRD_PRE-thumb.txt
isassembler/ARM/invalid-t2STREXB-thumb.txt
isassembler/ARM/invalid-t2STREXD-thumb.txt
isassembler/ARM/invalid-t2STR_POST-thumb.txt
isassembler/ARM/invalid-thumbv7-xfail.txt
isassembler/ARM/invalid-thumbv7.txt
isassembler/ARM/invalid-v8fp.txt
|
| f8087419df7153f20ac0d418cdc8ae657f5d2d89 |
19-Jul-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/test/MC/AsmParser/secure_log_unique.s: Use env(1) here. Then r186611 can be reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186643 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/secure_log_unique.s
|
| 9903a2513deba26d2284a5c83822b2043577bf69 |
18-Jul-2013 |
Hans Wennborg <hans@hanshq.net> |
test/MC/AsmParser/secure_log_unique.s requires shell
This should fix the chapuni bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186611 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/secure_log_unique.s
|
| 13c9cf1d5158d704546494f4b4851e5c9f09573f |
18-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a test for .secure_log_unique.
It also doubles a test that F_Append works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186606 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/secure_log_unique.s
|
| 59b3300664d062bf04159eacaeb44d6c729e6a8c |
18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add NEON instructions VCVT{A, N, P, M}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-v8.s
RM/thumb-neon-v8.s
isassembler/ARM/neon-v8.txt
isassembler/ARM/thumb-neon-v8.txt
|
| 6a3d933e1645d34984f4c7c9e2e4e46d0d15e1b3 |
18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add Thumb tests for the ARMv8 FP instructions that I recently added.
Also, fix the namespace for two instructions that I missed previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186572 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-v8fp.s
isassembler/ARM/thumb-v8fp.txt
|
| 764f6f51257a0669acc58c8e5b4b802a29069302 |
18-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186567 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| 16f385f90f481195bfcf6b139ced4cee033bb887 |
17-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186507 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-control-instructions.s
ips/mips_directives.s
|
| c88ac4a344bdb5b3ade5c24d67e1227c4d3a8978 |
17-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add the tests that I forgot to 'svn add' with my previous commit (r186504).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186506 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-v8.s
RM/thumb-neon-v8.s
isassembler/ARM/neon-v8.txt
isassembler/ARM/thumb-neon-v8.txt
|
| 898788c6bcc2abfe0e1c7b21c14394352963acd6 |
16-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add support for the Thumb2 PLI alternate literal form.
This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>]
See A8.8.129 in the ARM ARM (DDI 0406C.b).
Fixes <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186459 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| c25d21e05b76e9c542e3bea6a9a12a77772beb14 |
16-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add MC support for R[NOX]SBG
CodeGen support will come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186401 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 6057eb7ab697fcd0feb3cdd55e9a497cfe0aff72 |
15-Jul-2013 |
Reid Kleckner <reid@kleckner.net> |
[mc-coff] Resolve aliases when emitting COFF relocations
This is consistent with the ELF object writer.
Add some COFF tests that relocate against an alias.
Reviewers: espindola
Differential Revision: http://llvm-reviews.chandlerc.com/D1079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186341 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/alias.s
|
| 0dfc1664870ad6e48ecb8259d8ad8e70a2a475d3 |
14-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
Add newlines at end of test files, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186263 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| dd51a0c1e0b3cce8093244533b3505668d16f218 |
12-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186151 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 3ee0673e4f5f0324ecd0a65507009b0748ed072c |
11-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Allow 8-bit operands to RISBG
RISBG has three 8-bit operands (I3, I4 and I5). I'd originally
restricted all three to 6 bits, since that's the only range we intended
to use at the time. However, the top bit of I4 acts as a "zero" flag for
RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co.
This patch therefore allows them to have the full 8-bit range.
I've left the fifth operand as a 6-bit value for now since the
upper 2 bits have no defined meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186070 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| f5b1c5043de4d485ff17d8b2aad709c63a5a9ff3 |
10-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
Put ELF COMDAT relocations into the relevant COMDAT group.
Patch from Игорь Пашев (I do hope we support utf-8 commit messages; I
also hope he'll forgive me for transliterating it as Igor Pashev in
case things go horribly wrong).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186034 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comdat-reloc.s
LF/comdat.s
|
| faf98904b7442c8054b291c2e1ee30226abc0313 |
10-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Reverting commit r185999 due to buildboot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186001 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 2ec5933eae2e889225d33bd2f93a35926e958c95 |
10-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 7a34599db017a5486cf7cd11eb124984acec8286 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Revert r185476 and fix up TLS variant kinds
In the commit message to r185476 I wrote:
>The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
>correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
>This causes some confusion with the asm parser, since VK_PPC_TLSGD
>is output as @tlsgd, which is then read back in as VK_TLSGD.
>
>To avoid this confusion, this patch removes the PowerPC-specific
>modifiers and uses the generic modifiers throughout. (The only
>drawback is that the generic modifiers are printed in upper case
>while the usual convention on PowerPC is to use lower-case modifiers.
>But this is just a cosmetic issue.)
This was unfortunately incorrect, there is is fact another,
serious drawback to using the default VK_TLSLD/VK_TLSGD
variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT
to return true, which in turn causes the ELFObjectWriter to emit
an undefined reference to _GLOBAL_OFFSET_TABLE_.
This is a problem on powerpc64, because it uses the TOC instead
of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_,
so the symbol remains undefined. This means shared libraries
using TLS built with the integrated assembler are currently
broken.
While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation
probably ought to be properly fixed at some point, for now I'm
simply reverting the r185476 commit. Now this in turn exposes
the breakage of handling @tlsgd/@tlsld in the asm parser that
this check-in was originally intended to fix.
To avoid this regression, I'm also adding a different fix for
this problem: while common code now parses @tlsgd as VK_TLSGD,
a special hack in the asm parser translates this code to the
platform-specific VK_PPC_TLSGD that the back-end now expects.
While this is not really pretty, it's self-contained and
shouldn't hurt anything else for now. One the underlying
problem is fixed, this hack can be reverted again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185945 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 12f45c3782c0d01bcf9973bbc23dba2b17ce54cb |
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185929 91177308-0d34-0410-b5e6-96231b3b80d8
RM/v8fp.s
isassembler/ARM/v8fp.txt
|
| 8dc741d29f9c9beff8a9f26ff23b307b9df4f8fd |
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185926 91177308-0d34-0410-b5e6-96231b3b80d8
RM/v8fp.s
isassembler/ARM/v8fp.txt
|
| b2713e018e1c99bb9a65d2d2e63dc7e3e2222c57 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support ".machine any"
The PowerPC assembler is supposed to provide a directive .machine
that allows switching the supported CPU instruction set on the fly.
Since we do not yet check CPU feature sets at all and always accept
any available instruction, this is not really useful at this point.
However, it makes sense to accept (and ignore) ".machine any" to
avoid spuriously rejecting existing assembler files that use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185924 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc-machine.s
|
| 9fb5a6588becc92be1d7cf503d2947b170be3c31 |
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185922 91177308-0d34-0410-b5e6-96231b3b80d8
RM/v8fp.s
isassembler/ARM/v8fp.txt
|
| ff16df71f50231c79c379a146dc55b4d6867cbd9 |
09-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support .llong and fix .word
This adds support for the .llong PowerPC-specifc assembler directive.
In doing so, I notices that .word is currently incorrect: it is
supposed to define a 2-byte data element, not a 4-byte one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185911 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc-llong.s
owerPC/ppc-word.s
owerPC/ppc64-fixup-apply.s
|
| 01e4509972509e59874612d7d04419cdaeccc0ef |
08-Jul-2013 |
Eric Christopher <echristo@gmail.com> |
CEHCK->CHECK typo fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185875 91177308-0d34-0410-b5e6-96231b3b80d8
RM/eh-directive-cantunwind-diagnostics.s
|
| 193a2da6d157488caf6ed98c49fcfc677703890c |
08-Jul-2013 |
Eric Christopher <echristo@gmail.com> |
Fix up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185874 91177308-0d34-0410-b5e6-96231b3b80d8
RM/eh-directive-cantunwind-diagnostics.s
|
| 19d2b78978905cfde0a0d7190c8480219fb2d1c6 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support time base instructions
This adds support for the old-style time base instructions;
while new programs are supposed to use mfspr, the mftb instructions
are still supported and in use by existing assembler files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185829 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookII.s
|
| 9e5bbeab1f6f79375c24bfab87c28f5f4c5afea1 |
08-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support basic compare mnemonics
This adds support for the basic mnemoics (with the L operand) for the
fixed-point compare instructions. These are defined as aliases for the
already existing CMPW/CMPD patterns, depending on the value of L.
This requires use of InstAlias patterns with immediate literal operands.
To make this work, we need two further changes:
- define a RegisterPrefix, because otherwise literals 0 and 1 would
be parsed as literal register names
- provide a PPCAsmParser::validateTargetOperandClass routine to
recognize immediate literals (like ARM does)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185826 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding.s
|
| 5310cdbcc909a7c35d4c7df0fd5703850a9db2a5 |
08-Jul-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Revert: Fix wrong code offset for unwind code SET_FPREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185793 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| 9611873724b9f8d6cbbed7924c972e8d026cc263 |
08-Jul-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Revert: Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH data structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185791 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| 9c411e649e86c1734bc087d0e87208569ae1cb5c |
08-Jul-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Revert: Fix alignment of unwind data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185790 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh-align1.s
OFF/seh-align2.s
OFF/seh-align3.s
|
| 2a9683289b78a2533b261e1b341f9ea9724465a0 |
06-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC support for the v8fp instructions: vmaxnm and vminnm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185767 91177308-0d34-0410-b5e6-96231b3b80d8
RM/v8fp.s
isassembler/ARM/v8fp.txt
|
| 59c5c6c2b24b77371e53e6dbdf035edb50eafe1a |
06-Jul-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Fix alignment of unwind data.
For alignment purposes, the instruction array will always have an even
number of entries, with the final entry potentially unused (in which
case the array will be one longer than indicated by the count of unwind
codes field).
Reviewed by Charles Davis and Nico Rieck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185760 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh-align1.s
OFF/seh-align2.s
OFF/seh-align3.s
|
| eececbc7d3d420a27f9e1f9e11cce1b9bbff953f |
06-Jul-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH
data structures.
The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB
instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding
the VK_COFF_IMGREL32 modifier to the symbol reference.
Change also references to start and end of the SEH range of a function
as offsets to start of the function.
Reviewed by Charles Davis and Nico Rieck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185759 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| ea434e4bca15383418ac65788fdb8bc3b5725fe2 |
06-Jul-2013 |
Kai Nacke <kai.nacke@redstar.de> |
Fix wrong code offset for unwind code SET_FPREG.
The code offset for unwind code SET_FPREG is wrong because it is set
to constant 0. The fix is to do the same as for the other unwind
codes: emit a label and later the absolute difference between the
label and the begin of the prologue.
Also enables the failing test case MC/COFF/seh.s
Reviewed by Charles Davis and Nico Rieck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185758 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| 80646283796b20c6a1b7d8eb69ce6f0478d54383 |
06-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
MC: Implement COFF .linkonce directive
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185753 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/linkonce-invalid.s
OFF/linkonce.s
|
| 457571ed6977f78ca8d30b993fa7e86e2d7ad8d5 |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.
However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.
The same applies for the @got@dtprel variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 3d4427347e5d540d22bd135535282761efb6bd6e |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Make test case buildable with GNU as
The ppc64-fixups.s test currently fails to build with GNU as, since it
does not support plain symbols as arguments to li/lis. Rewrite the test
for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead.
Allowing the test case to be built with both LLVM and GNU as makes it
easier to spot unwanted difference in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185694 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df |
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-errors.s
owerPC/ppc64-fixups.s
|
| a6d343a688073664b3a80aa117e0d3cbecf28014 |
04-Jul-2013 |
Nico Rieck <nico.rieck@gmail.com> |
MC: Add .section directive to COFF
Supports GAS flags "abdnrswxy". No support for alignment or subsections.
Fixes PR16366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185669 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/section-invalid-flags.s
OFF/section.s
OFF/seh-section.s
|
| 972befb3f281f0f9ce08d7cf27b4e879327676b0 |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.
This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc-nop.s
|
| 449f64c69c8db6ac0b63078e1feb1f51b7b0549a |
04-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add 'not' in front of a command that is expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185659 91177308-0d34-0410-b5e6-96231b3b80d8
RM/invalid-v8fp.s
|
| 4ea250524f77a67102118747dad6ee69f9f3b3aa |
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
RM/v8fp.s
isassembler/ARM/v8fp.txt
|
| 3c99602ca87f604080e367838180c3d63f6931f3 |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add all trap mnemonics
This adds support for all basic and extended variants
of the trap instructions to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding.s
|
| 5606fcae50951e9d9aef7def18531b5fd017971b |
04-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 929d9ef111cc0053e245d04464c5ba9fba7727b2 |
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
RM/invalid-v8fp.s
RM/v8fp.s
isassembler/ARM/invalid-v8fp.txt
isassembler/ARM/v8fp.txt
|
| 79c163d6ddeb84ea1743eca0644688951bfc5a97 |
03-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.
The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.
This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.
Fixes <rdar://problem/14224440>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 51f558c9aed3bf74c2e8f3ff3bf365c94637ecdf |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding.s
|
| 33efedc0481c4b0d9866ff526eb1161372b5919f |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding.s
|
| 73477b9f32da6488f2883f33fd17fa0de61f2bd1 |
03-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Prefix failing commands with not to make clear they are expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/elf-objdump.s
Arch64/gicv3-regs-diagnostics.s
Arch64/trace-regs-diagnostics.s
RM/arm-thumb-cpus.s
RM/arm-thumb-trustzone.s
RM/arm-trustzone.s
RM/eh-directive-fnend-diagnostics.s
RM/eh-directive-fnstart-diagnostics.s
RM/invalid-hint-arm.s
RM/invalid-hint-thumb.s
smParser/align_invalid.s
smParser/directive_align.s
smParser/macros-darwin.s
86/AlignedBundling/align-mode-argument-error.s
86/AlignedBundling/bundle-group-too-large-error.s
86/AlignedBundling/bundle-lock-option-error.s
86/AlignedBundling/lock-without-bundle-mode-error.s
86/AlignedBundling/switch-section-locked-error.s
86/AlignedBundling/unlock-without-lock-error.s
|
| 44175d9715268bfb7c2cb10ebf14474f4a411464 |
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser. The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding.s
|
| b81b477cd4392a51112c3af0659ea9fc176e74f1 |
03-Jul-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/basic-thumb2-instructions.s
isassembler/ARM/thumb1.txt
|
| 25b9bbae69befa03cc48d4be73b741eff8e523bc |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser. This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop. That pattern is used for the
asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 9188443a2d35352c4e8a2cffd1b4d31d47843b26 |
02-Jul-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add the MVC instruction
This is the first use of D(L,B) addressing, which required a fair bit
of surgery. For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
ystemZ/insn-bad.s
ystemZ/insn-good.s
ystemZ/tokens.s
|
| 0a39e264330c5f6eb9e5e9e60d276613985e178d |
02-Jul-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix ARM EHABI compact model 1 and 2 without handlerdata.
According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes. The handler data consists of several words, and
should be terminated by zero.
In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
RM/eh-compact-pr1.s
|
| 75dd57a8f0407be32551cf695e63a106dd051a27 |
02-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:
1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.
2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).
3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.
4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.
With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-regs.s
|
| 228e0afcfd0d5f167a95c6ddbec2c6a4a90b6d2b |
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
.quad target@dtpmod
.quad target@tprel
.quad target@dtprel
Currently exploited by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 1307d8300f6fe97059998480c42b44faefbc9b99 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding.s
|
| e29e2afc738348c74966ed81b3568779247c9fbd |
01-Jul-2013 |
Chad Rosier <mcrosier@apple.com> |
[ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values. This should be the last fix due to fallout from r185094.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| 3bd2b92267df204c5633329611cc7ae3e1c11834 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookII.s
|
| db8e0bbedb46c9f781f8a32728b1019f34089ed8 |
01-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| 222e781d92541017c3a9c5dd40cb52e334cdb86f |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.
Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185353 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-explicit.s
|
| 62c1baf8b58a40d37f56a5431214e6514e42970f |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185350 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookII.s
|
| c0a6b981de8efd2c68125edb94bf9ffb933df727 |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support "eieio" instruction
This adds support for the "eieio" instruction to
the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185349 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookII.s
|
| 4c1d023de889428e3ea17767b9a7238901c66eff |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some existing instructions to ppc64-encoding-bookII.s
The test case had a couple of FIXMEs where the instruction is in
fact already supported by the back-end. In some other case, while
the generic form of the instruction is not yet supported, a
specialized form is. This adds tests for those already supported
instructions / instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185347 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookII.s
|
| af679a22923d2b61e3bfb6721bd562b99546bfad |
01-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185344 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookII.s
|
| f04f8b4f779919de0b3bccef2144d965ac51d35f |
01-Jul-2013 |
Serge Pavlov <sepavloff@gmail.com> |
Added the test missed from r185080.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185316 91177308-0d34-0410-b5e6-96231b3b80d8
LF/bss-large.ll
|
| a744d41a3f8af25938e12617abe2a8d32f6eabf6 |
28-Jun-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Fix pseudo-instructions for SRS (Store Return State).
The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is:
srsfa -> srsib
srsea -> srsia
srsfd -> srsdb
srsed -> srsda
This fixes <rdar://problem/14214734>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185155 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| c084c0945b0530180e8969f5e2017d02d06db130 |
28-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
Integrate Assembler: Support X86_64_DTPOFF64 relocations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185131 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| b7110cf5b5e4832e8ded6db7ab7577e3cfa2c462 |
27-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.
The current algorithm, LessRecord, uses the StringRef compare_numeric
function. This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:
T1
T1_W
T1_X
T1_XYZW
T1_Y
T1_Z
T2
T2_W
T2_X
T2_XYZW
T2_Y
T2_Z
In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another. However, in other parts
of the register bank, the scaling factors are different:
dEnum/dN = 5:
KC0_128_W
KC0_128_X
KC0_128_XYZW
KC0_128_Y
KC0_128_Z
KC0_129_W
KC0_129_X
KC0_129_XYZW
KC0_129_Y
KC0_129_Z
The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'. This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1. For example, the registers are now sorted as
follows:
T1
T2
T3
...
T0_W
T1_W
T2_W
...
T0_X
T1_X
T2_X
...
KC0_128_W
KC0_129_W
KC0_130_W
...
For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even
greater wins for targets with larger register files.
Patch reviewed by Jakob.
rdar://14006013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 096c0a03313ea43a1e4035645b02bf99fd35801a |
27-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| 842cfc91f29f6446bb675891f7abc127f9fbe768 |
26-Jun-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Do not emit ".option pic0" if target is mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185012 91177308-0d34-0410-b5e6-96231b3b80d8
ips/abicalls.ll
|
| c19bd321362166805194cbaf170e06a4790d2da9 |
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
RM/thumb-only-conditionals.s
RM/thumb2-diagnostics.s
|
| c1a91dd97b000128189421eda6c5bb7905b1f467 |
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
RM/thumb-only-conditionals.s
|
| 8950dd127ad4cccd9dadf616b5057cf130f24ade |
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Accept 17-bit signed immediates for addis
The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767). This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).
The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.
Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-errors.s
owerPC/ppc64-operands.s
|
| 0b8594268feb1c804370541c7853e658caee0ae5 |
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands. However, for u16imm operands, we only support actual
immediate integers. This causes the assembler to reject code like
ori %r5, %r5, symbol@l
This patch changes the u16imm operand definition to likewise
accept symbolic operands. In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 6e0857e0b6b241e8b698417659a5821f15290a63 |
26-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: operands should be explicit when disassembled
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184943 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 5de735a962a255676cf3a9bc255579d465670633 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @got modifier
Add VK_... values and relocation types necessary to support
the @got family of modifiers. Used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184860 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 1bc147c0910bb02398730c79e0d0310ffbbd2868 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add extended rotate/shift mnemonics
This adds all missing extended rotate/shift mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184834 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 816c06f7fa73e8150e260a11d897be2f52d4f2b8 |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing). They are currently used
only by the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184833 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding.s
|
| 9c52f81e1787dc9666e510f5b7a0ea75b697cd0b |
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add extended subtract mnemonics
This adds support for the extended subtract mnemonics to the asm parser:
subi
subis
subic
subic.
sub
sub.
subc
subc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184832 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 96fb3a25cb0007f06d22d28c0b9c3503798324f6 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support some miscellaneous mnemonics in the asm parser
This adds support for the following extended mnemonics:
xnop
mr.
not
not.
la
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184767 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 329d41319996d943e97180307df7e1600198d356 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some FIXMEs
A bunch of extendend mnemomics ought to support '.' forms.
Add FIXMEs to the test case for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184757 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 2e8bd8950345b0857130dd0f4068222a79c103f2 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
For these, I've added new PPC::Predicate codes corresponding
to the BO values for predicted branch forms, and updated insn
printing to print them correctly. I've also added new aliases
for the asm parser matching the new forms.
- bt/bf
I've added new aliases matching to gBC etc.
- bd(n)z variants
I've added new instruction patterns for the predicted forms.
In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 48473a8de50d6047432a3619e4781788ba004c93 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add t/f branch mnemonics to asm parser
This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184725 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| e5a30f0ca22cc1ba97478e9fadcdef02d341004e |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support generic conditional branches in asm parser
This adds instruction patterns to cover the generic forms of
the conditional branch instructions. This allows the assembler
to support the generic mnemonics.
The compiler will still generate the various specific forms
of the instruction that were already supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184722 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding.s
|
| 9679c47a07386cbf3547a0927609c7ee080b2aab |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions. This patch adds support for the absolute
variants of all branches that are currently otherwise supported.
This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.
While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
owerPC/ppc64-encoding.s
owerPC/ppc64-fixups.s
owerPC/ppc64-operands.s
|
| 9068d5310cfafdd201f77b0434dc7eebb7f51a45 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support bd(n)zl and bd(n)zlrl
This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184720 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 813942a0cf8e0605002c5fa364372a8a61634cc4 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support b(cond)l in the asm parser
This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184719 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 7e66f5c1b4a166d823e0452d1a1bc0f822d04201 |
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support blrl and variants in the asm parser
This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184718 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| ebc3938ae717d7352de800344c3ad5a1bceb74e5 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-NEON-thumb.txt
isassembler/ARM/invalid-VFP-thumb.txt
|
| 07c3e159d8fffc8b16bcd52cc395a78007c62910 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: rGPR is meant to be unpredictable, not undefined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184706 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
isassembler/ARM/invalid-t2STRD_PRE-thumb.txt
|
| 4ee72398a15cd7b8e217bb3d34a4e9e0e72caca1 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb1 nop decoding
In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184703 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-nop.s
RM/thumb.s
isassembler/ARM/thumb1.txt
|
| ff08da15cf3d0412ee9cc325fc5a720bcad178f2 |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix IT decoding
mask == 0 -> UNPRED
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184702 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-IT-thumb.txt
|
| 0c9f0c047dfba91bc7c0fb66f7e868e917d37c4c |
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: enable decoding of pc-relative PLD/PLI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184701 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDR-thumb.txt
isassembler/ARM/thumb2.txt
|
| 7130a9561787cf14d5349d22cde1e0b3a4d5c21d |
23-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: fix overzealous NEXTing for Windows testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184667 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/tls-relocs.s
|
| 84569698f01bcb49afe5b6140bf0d61cf4f3cf5a |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:
li 1, base-.
This patch adds support for those relocation types in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184552 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| cab0a1933875935c717136d251e2af9749533ba8 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support various tls-related modifiers
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code. This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184551 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| f7c1ee79fe90353fcd3f545f9d45a01a837bbf4b |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @higher et.al. modifiers
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184550 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-apply.s
owerPC/ppc64-fixups.s
|
| f8f87dcfceadd1b842d130303a7091ad7d7d67d0 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @toc@h modifier
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184549 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| d2849572463da994c685b3bd7a60d5a7566c01e3 |
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @h modifier
This adds necessary infrastructure to support the @h modifier.
Note that all required relocation types were already present
(and unused).
This patch provides support for using @h in the assembler;
it would also be possible to now use this feature in code
generated by the compiler, but this is not done yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184548 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-apply.s
owerPC/ppc64-fixups.s
|
| 46d7de7a192f43eb568c26c88e2dc2b804c09614 |
21-Jun-2013 |
Kevin Enderby <enderby@apple.com> |
Update the X86 disassembler to use xacquire and xrelease when appropriate.
This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.
Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease. Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.
rdar://11019859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184490 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 4cbbbf49b69646ff990203ef3feae6a2726b8753 |
20-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
This reverts r155000.
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.
VFP instructions on v8/AArch32 share the same encoding space as cdp2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-CDP2-arm.txt
|
| 151ad37fed2685f020bbed5b342ad7c0c35616bd |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[MC] Support @ variants with directional labels
The assembler parser common code supports recognizing symbol variants
using the @ modifer. On PowerPC, it should also be possible to use
(some of) those modifiers with directional labels, like "1f@l".
This patch adds support for accepting symbol variants on directional
labels as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184437 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-apply.s
|
| 027e94479c9e69eb3c3c5536fa9990d0b96e9510 |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Optimize @ha/@l constructs
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.
This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions. However,
those target expression were used only on Darwin targets.
This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.
It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers. The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184436 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-apply.s
|
| 0db5379fe643cbe738b4831e337251819cc5dc5d |
20-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support compare mnemonics with implied CR0
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).
This patch adds support for those extended compare mnemonics.
Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80]
cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80]
+ cmpdi 3, 128
# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00]
cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00]
+ cmpd 3, 4
# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80]
cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80]
+ cmpldi 3, 128
# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40]
cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40]
+ cmpld 3, 4
# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80]
cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80]
+ cmpwi 3, 128
# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00]
cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00]
+ cmpw 3, 4
# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80]
cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80]
+ cmplwi 3, 128
# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40]
cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40]
+ cmplw 3, 4
# FIXME: Trap mnemonics
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
defm : BranchExtendedMnemonic<"nu", 100>;
defm : BranchExtendedMnemonic<"ns", 100>;
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 7231625f75b4da1c87deb833cd9cad6c5ee95d95 |
20-Jun-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184411 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 4df4bccc71ea0477836db9a417d3da202c2baa09 |
19-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directives
The compiler occasionally generates multiple .loc directives in a row
(at the same instruction address). These need to be transformed into
multple actual .debug_line table entries, since they are used to signal
certain information to the debugger (e.g. if the opening brace of a
function body is on the same line as the declaration).
The MCAsmStreamer version of EmitDwarfLocDirective handles this
correctly by emitting a .loc directive every time it is called.
However, the MCObjectStream version simply defaults to recording
the information and emitting only a single table entry later,
e.g. when EmitInstruction is called.
This patch introduces a MCAsmStreamer::EmitDwarfLocDirective
version that emits a line table entry for a .loc directive
that may already be pending before recording the new directive.
(This is similar to how this is handled in GNU as.)
With this patch (and the code alignment factor patch) applied,
I'm now getting identical DWARF .debug sections for all test-suite
object files on PowerPC for the internal and the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184357 91177308-0d34-0410-b5e6-96231b3b80d8
LF/debug-line2.s
|
| a95e3091eb9ba5010f6c5f6f51958b01ca3a85f6 |
18-Jun-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add optional datatype suffix to NEON mvn asm syntax.
rdar://14194152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.s
|
| bf811d602d1d81b93846c6cbbd1cec85f2f153cb |
18-Jun-2013 |
Kevin Enderby <enderby@apple.com> |
Change the arm assembler to support this from the v7c spec:
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."
In the pre-matcher handler in the asm parser the ".w" (wide) qualifier
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.
Test cases for these were added.
rdar://14064574
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 571dd98ea4d6bf911c3b46a20ca3b5e3b341b21f |
18-Jun-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips ELF: Mark object file as ABI compliant
When producing objects that are abi compliant we are
marking neither the object file nor the assembly file
correctly and thus generate warnings.
We need to set the EF_CPIC flag in the ELF header when
generating direct object.
Note that the warning is only generated when compiling without PIC.
When compiling with clang the warning will be suppressed by supplying:
-Wa,-mno-shared -Wa,-call_nonpic
Also the following directive should also be added:
.option pic0
when compiling without PIC, This eliminates the need for supplying:
-mno-shared -call_nonpic
on the assembler command line.
Patch by Douglas Gilmore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184220 91177308-0d34-0410-b5e6-96231b3b80d8
ips/abicalls.ll
ips/elf_eflags.ll
|
| 23306deb92e2424165f2145895e21e223c3887eb |
18-Jun-2013 |
Stefanus Du Toit <stefanus.du.toit@intel.com> |
Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-hle-encoding.s
|
| beb920fce6ccc89b4735f280f94cb8c227f4ef5e |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly
This patch also makes the assembler look at the .w/.n specifier for
loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f8b60d6f30a8f25c84a71d36ff3a86fe1f52f671 |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: add operands pre-writeback variants when needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184181 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| ce046b98ed6c351779fc43599a80d588752bc1ca |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb literal loads decoding
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| cea0032f73a56a62b692b25ca4084850cd51763b |
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: thumb stores cannot use PC as dest register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-STR-thumb.txt
|
| 7338de37a802970857079b5a532c5dd50d0a6d5d |
17-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: print relocation addends if present on AArch64
llvm-objdump should provide some way of printing out the addends present in the
.rela sections for debugging purposes if nothing else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184072 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/elf-reloc-addend.s
|
| a768a4954818456fa6fe2077a3cbe75979025c15 |
14-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 8117ac555d06b23f61ddd06aa54d3dfa3e5b8e56 |
13-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix B decoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183914 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 1290ce00a372f10fa1667d3566477f86ede04c73 |
13-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix t2am_imm8_offset operand printing for imm=#-0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183913 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 19b30d56b224ab3507f7a93743eac2b01c5861dd |
13-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Make the cmov aliases work with intel syntax too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183907 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| c1f4a4b2640dfc871bacacef53a95f1c96a9fe48 |
12-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.
In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4. However, current MC code hard-codes a code
alignment factor of 1.
This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.
This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc. Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available. However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it. If it turns out to be needed again at a later time, it
could be re-added with an updated interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183834 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-initial-cfa.s
|
| e48e8c7a6069374daee4c9be1e17b8ed31527f5e |
12-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use assembler source in MC tests
A couple of old test cases in test/MC/PowerPC were still using
LLVM IR. Now that we have a working assembler, we can move
them to assembler tests instead:
ppc64-initial-cfa.ll
ppc64-relocs-01.ll
ppc64-tls-relocs-01.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183829 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-initial-cfa.ll
owerPC/ppc64-initial-cfa.s
owerPC/ppc64-relocs-01.ll
owerPC/ppc64-relocs-01.s
owerPC/ppc64-tls-relocs-01.ll
owerPC/ppc64-tls-relocs-01.s
|
| 6c921a55f4d5fc51a127fcc673ac1c9b46273899 |
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-thumb-cpus-default.s
RM/arm-thumb-cpus.s
|
| 55ab7315d04ce4f25a15e5cd50f6a23d950a00cf |
11-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183734 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 16ad92ad3cd0cbbaa4d0524d9f201dd5dbefa15a |
11-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183733 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
isassembler/ARM/fp-encoding.txt
|
| aa8003712e8b28bc4f263aeb79d8851146273a05 |
11-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: Enforce decoding rules for VLDn instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VLDST-arm.txt
isassembler/ARM/invalid-VST-arm.txt
isassembler/ARM/neont2.txt
|
| 3862709058ecfe809c9d4b32e3bff0efe8ebe646 |
11-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183729 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-LDREXD-reencoding.txt
isassembler/ARM/arm-STREXD-reencoding.txt
|
| c139672407b6ad8d2929fd0c52591216fd32b4b6 |
11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
- For now, The tests are marked as XFAIL for win32 hosts.
FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-thumb-cpus-default.s
RM/arm-thumb-cpus.s
|
| 9bdd78501484a1add2d8a757fd29960dd9fc9de7 |
11-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.
rdar://14024354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-thumb-cpus-default.s
RM/arm-thumb-cpus.s
RM/elf-thumbfunc-reloc.s
RM/mapping-within-section.s
RM/multi-section-mapping.s
|
| 278916500a2d7c735e3ed6b0f57cd757815b9867 |
10-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support extended sc mnemonic
A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler. This patch adds a corresponding alias.
Problem reported by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183687 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding.s
|
| 7c6f90d486911076da01ec0f37af4760fdd7041f |
10-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support branch mnemonics with implied CR0
The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified. This patch
adds extra variants of the mnemonics to this effect.
Problem reported by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183686 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 4e9a96d810eb0cc126ebe6f18e536b474c84940c |
10-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
RM/diagnostics.s
RM/thumb2-diagnostics.s
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/thumb2.txt
|
| 18cba562c8016f8095643b5dd8c4b34b294b62dd |
09-Jun-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Fix ARM unwind opcode assembler in several cases.
Changes to ARM unwind opcode assembler:
* Fix multiple .save or .vsave directives. Besides, the
order is preserved now.
* For the directives which will generate multiple opcodes,
such as ".save {r0-r11}", the order of the unwind opcode
is fixed now, i.e. the registers with less encoding value
are popped first.
* Fix the $sp offset calculation. Now, we can use the
.setfp, .pad, .save, and .vsave directives at any order.
Changes to test cases:
* Add test cases to check the order of multiple opcodes
for the .save directive.
* Fix the incorrect $sp offset in the test case. The
stack pointer offset specified in the test case was
incorrect. (Changed test cases: ehabi-mc-section.ll and
ehabi-mc.ll)
* The opcode to restore $sp are slightly reordered. The
behavior are not changed, and the new output is same
as the output of GNU as. (Changed test cases:
eh-directive-pad.s and eh-directive-setfp.s)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
RM/eh-directive-integrated-test.s
RM/eh-directive-multiple-offsets.s
RM/eh-directive-pad.s
RM/eh-directive-save.s
RM/eh-directive-setfp.s
|
| 9eefea009fb559cf441254f7022a2824386852c6 |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VMOV-arm.txt
|
| ae50ddb2aeaec7dd91ef8db3918688c104a6baed |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: enforce SRS decoding constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-SRS-arm.txt
|
| 46e136c952e0242308db2682ba2ec4020cdcd006 |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix CPS decoding when ambiguous with QADD
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.
Add some necessary safe guards in CPS decoding as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/invalid-CPS-arm.txt
|
| c64835b0c57913b11abd648b76913390e62af8d6 |
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix VCVT decoding
UNPRED was reported instead of UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VCVT-arm.txt
|
| c9f2cc7e05b2a7f3991a94cad1730a59dd7555e3 |
05-Jun-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't hide the first ELF symbol.
The first symbol on ELF is dummy, but it has a defined content and readelf
normally displays it. With this change llvm-readobj also displays it and we
can check that llvm-mc output is correct according to the standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183337 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias-reloc.s
LF/alias.s
LF/weakref.s
|
| 2248cf590617cbe91eeb6a845ad06d675d9f2e91 |
05-Jun-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/basic-arm-instructions.txt
|
| ee5e24cb3e987c74d4dce146b4f78e83fb2b56a8 |
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: permit upper-case BE/LE on setend instruction
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 242c9f4615feeee2fbdd1f29cd9a8e8ffd43c075 |
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add fstmx and fldmx instructions for assembly
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
isassembler/ARM/fp-encoding.txt
isassembler/ARM/invalid-FSTMX-arm.txt
|
| e93c701cac2ac62bcd390b978604da76be9967d0 |
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix VEXT encoding corner case
The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).
Patch by Amaury de la Vieuville
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VEXTd-arm.txt
|
| 7486d92a6c949a193bb75c0ffa0170eeb2fabb80 |
30-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change how we iterate over relocations on ELF.
For COFF and MachO, sections semantically have relocations that apply to them.
That is not the case on ELF.
In relocatable objects (.o), a section with relocations in ELF has offsets to
another section where the relocations should be applied.
In dynamic objects and executables, relocations don't have an offset, they have
a virtual address. The section sh_info may or may not point to another section,
but that is not actually used for resolving the relocations.
This patch exposes that in the ObjectFile API. It has the following advantages:
* Most (all?) clients can handle this more efficiently. They will normally walk
all relocations, so doing an effort to iterate in a particular order doesn't
save time.
* llvm-readobj now prints relocations in the same way the native readelf does.
* probably most important, relocations that don't point to any section are now
visible. This is the case of relocations in the rela.dyn section. See the
updated relocation-executable.test for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/elf-globaladdress.ll
Arch64/elf-reloc-addsubimm.s
Arch64/elf-reloc-condbr.s
Arch64/elf-reloc-ldrlit.s
Arch64/elf-reloc-ldstunsimm.s
Arch64/elf-reloc-movw.s
Arch64/elf-reloc-pcreladdressing.s
Arch64/elf-reloc-tstb.s
Arch64/elf-reloc-uncondbrimm.s
Arch64/tls-relocs.s
RM/eh-compact-pr0.s
RM/eh-compact-pr1.s
RM/eh-directive-cantunwind.s
RM/eh-directive-handlerdata.s
RM/eh-directive-personality.s
RM/eh-directive-section-multiple-func.s
RM/eh-directive-section.s
RM/eh-directive-text-section-multiple-func.s
RM/eh-directive-text-section.s
RM/elf-movt.s
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-reloc-condcall.s
RM/elf-thumbfunc-reloc.ll
RM/elf-thumbfunc-reloc.s
LF/alias-reloc.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-escape.s
LF/cfi-offset.s
LF/cfi-register.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-restore.s
LF/cfi-same-value.s
LF/cfi-undefined.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/gen-dwarf.s
LF/got.s
LF/local-reloc.s
LF/merge.s
LF/relocation-386.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/symref.s
LF/weak-relocation.s
LF/x86_64-reloc-sizetest.s
ips/eh-frame.s
ips/elf-gprel-32-64.ll
ips/elf-tls.ll
owerPC/ppc64-initial-cfa.ll
owerPC/ppc64-relocs-01.ll
owerPC/ppc64-tls-relocs-01.ll
|
| 2d664abbfca8b9fa3d99e8a2f74bd52faf007f12 |
29-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Immediate compare-and-branch support
This patch adds support for the CIJ and CGIJ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182846 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns-pcrel.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| c57905ef4dfc7a8b573efbf8e0a1f9580d98bfe8 |
29-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Improve set register alias handling
This patch solves the problem of numeric register values not being accepted:
../set_alias.s:1:11: error: expected valid expression after comma
.set r4,$4
^
The parsing of .set directive is changed and handling of symbols in code
as well to enable this feature.
The test example is added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182807 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| d50bcb2162a529534da42748ab4a418bfc9aaf06 |
28-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Register compare-and-branch support
This patch adds support for the CRJ and CGRJ instructions. Support for
the immediate forms will be a separate patch.
The architecture has a large number of comparison instructions. I think
it's generally better to concentrate on using the "best" comparison
instruction first and foremost, then only use something like CRJ if
CR really was the natual choice of comparison instruction. The patch
therefore opportunistically converts separate CR and BRC instructions
into a single CRJ while emitting instructions in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns-pcrel.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| 41b646c127300c6e3b83f1a0bfc49c812110ebf4 |
25-May-2013 |
Cameron Zwarich <zwarich@apple.com> |
Add support for DWARF line number table entries for values in the instruction
stream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182712 91177308-0d34-0410-b5e6-96231b3b80d8
LF/debug-line.s
|
| bfe3212dd807d018cb66479829fd81c8e7bd0f81 |
24-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Improve AsmParser handling of invalid instructions
Previously, an invalid instruction like:
foo %r1, %r0
would generate the rather odd error message:
....: error: unknown token in expression
foo %r1, %r0
^
We now get the more informative:
....: error: invalid instruction
foo %r1, %r0
^
The same would happen if an address were used where a register was expected.
We now get "invalid operand for instruction" instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182644 91177308-0d34-0410-b5e6-96231b3b80d8
ystemZ/regs-bad.s
ystemZ/tokens.s
|
| f386961da34426d12de8558ad04ad7f22c71489a |
24-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Improve AsmParser register parsing
The idea is to make sure that:
(1) "register expected" is restricted to cases where ParseRegister()
is called and the token obviously isn't a register.
(2) "invalid register" is restricted to cases where a register-like "%..."
sequence is found, but the "..." makes no sense.
(3) the generic "invalid operand for instruction" is used in cases where
the wrong register type is used (GPR instead of FPR, etc.).
(4) the new "invalid register pair" is used if the register has the right type,
but is not a valid register pair.
Testing of (1)-(3) is now restricted to regs-bad.s. It uses a representative
instruction for each register class to make sure that only registers from
that class are accepted.
(4) is tested by both regs-bad.s (which checks all invalid register pairs)
and insn-bad.s (which tests one invalid pair for each instruction that
requires a pair).
While there, I changed "Number" to "Num" for consistency with the
operand class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182643 91177308-0d34-0410-b5e6-96231b3b80d8
ystemZ/insn-bad.s
ystemZ/regs-bad.s
|
| 30a7a7c1fdbd2607345dd1554e3436749fd75c6e |
20-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VST-arm.txt
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
|
| bac932e9c3c4305a3c73598f3d0dc55de53d4c68 |
20-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VQADD-arm.txt
|
| e152eac63efa836cbb109d79e4307516fa16f1a6 |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Merge/rename PPC fixup types
Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly
the same everywhere, it no longer makes sense to have two fixup types.
This patch merges them both into a single type fixup_ppc_half16,
and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency.
(The half16 and half16ds names are taken from the description of
relocation types in the PowerPC ABI.)
No change in code generation expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| c299ad32c8e59ceea05ede15e1c59ac787d17feb |
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-apply.s
owerPC/ppc64-fixups.s
|
| e351865b65e92bea8ceeb32ad757d783d0ecea0f |
16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add TwoOperandConstraint definitions
This patch removes alias definition for addiu $rs,$imm
and instead uses the TwoOperandAliasConstraint field in
the ArithLogicI instruction class.
This way all instructions that inherit ArithLogicI class
have the same macro defined.
The usage examples are added to test files.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
ips/mips64-alu-instructions.s
|
| 3209baefd4ab8242563118c37d8357bd9de6b421 |
16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add branch macro definitions
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm
The corresponding test cases are added.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-jump-instructions.s
|
| 9122396a4dea52cf917062782fc2f39c7dc698bb |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define
fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte
fixups, applied at an offset of 2 relative to the start of the
instruction text.
This has the benefit that if we actually need to generate a real
relocation record, its address will come out correctly automatically,
without having to fiddle with the offset in adjustFixupOffset.
Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| ddbf053a4cad58393a389f264c51923111eba3db |
15-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Make use of SUBTRACT HALFWORD
Thanks to Ulrich Weigand for noticing that this instruction was missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insns.txt
ystemZ/insn-bad.s
ystemZ/insn-good.s
|
| e66ef733188f06f24baa8fe496abd9eab442b3b0 |
15-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add test case for r181891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181892 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixup-apply.s
|
| 363ce4085f6e414d99ba4faeeba965be83856a8c |
15-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Consolidate disassembler tests for valid input into 2 big tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181879 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insn-a.txt
isassembler/SystemZ/insn-adb.txt
isassembler/SystemZ/insn-adbr.txt
isassembler/SystemZ/insn-aeb.txt
isassembler/SystemZ/insn-aebr.txt
isassembler/SystemZ/insn-afi.txt
isassembler/SystemZ/insn-ag.txt
isassembler/SystemZ/insn-agf.txt
isassembler/SystemZ/insn-agfi.txt
isassembler/SystemZ/insn-agfr.txt
isassembler/SystemZ/insn-aghi.txt
isassembler/SystemZ/insn-agr.txt
isassembler/SystemZ/insn-agsi.txt
isassembler/SystemZ/insn-ah.txt
isassembler/SystemZ/insn-ahi.txt
isassembler/SystemZ/insn-ahy.txt
isassembler/SystemZ/insn-al.txt
isassembler/SystemZ/insn-alc.txt
isassembler/SystemZ/insn-alcg.txt
isassembler/SystemZ/insn-alcgr.txt
isassembler/SystemZ/insn-alcr.txt
isassembler/SystemZ/insn-alfi.txt
isassembler/SystemZ/insn-alg.txt
isassembler/SystemZ/insn-algf.txt
isassembler/SystemZ/insn-algfi.txt
isassembler/SystemZ/insn-algfr.txt
isassembler/SystemZ/insn-algr.txt
isassembler/SystemZ/insn-alr.txt
isassembler/SystemZ/insn-aly.txt
isassembler/SystemZ/insn-ar.txt
isassembler/SystemZ/insn-asi.txt
isassembler/SystemZ/insn-axbr.txt
isassembler/SystemZ/insn-ay.txt
isassembler/SystemZ/insn-basr.txt
isassembler/SystemZ/insn-br.txt
isassembler/SystemZ/insn-bras.txt
isassembler/SystemZ/insn-brasl.txt
isassembler/SystemZ/insn-brc.txt
isassembler/SystemZ/insn-brcl.txt
isassembler/SystemZ/insn-c.txt
isassembler/SystemZ/insn-cdb.txt
isassembler/SystemZ/insn-cdbr.txt
isassembler/SystemZ/insn-cdfbr.txt
isassembler/SystemZ/insn-cdgbr.txt
isassembler/SystemZ/insn-ceb.txt
isassembler/SystemZ/insn-cebr.txt
isassembler/SystemZ/insn-cefbr.txt
isassembler/SystemZ/insn-cegbr.txt
isassembler/SystemZ/insn-cfdbr.txt
isassembler/SystemZ/insn-cfebr.txt
isassembler/SystemZ/insn-cfi.txt
isassembler/SystemZ/insn-cfxbr.txt
isassembler/SystemZ/insn-cg.txt
isassembler/SystemZ/insn-cgdbr.txt
isassembler/SystemZ/insn-cgebr.txt
isassembler/SystemZ/insn-cgf.txt
isassembler/SystemZ/insn-cgfi.txt
isassembler/SystemZ/insn-cgfr.txt
isassembler/SystemZ/insn-cgfrl.txt
isassembler/SystemZ/insn-cgh.txt
isassembler/SystemZ/insn-cghi.txt
isassembler/SystemZ/insn-cghrl.txt
isassembler/SystemZ/insn-cghsi.txt
isassembler/SystemZ/insn-cgr.txt
isassembler/SystemZ/insn-cgrl.txt
isassembler/SystemZ/insn-cgxbr.txt
isassembler/SystemZ/insn-ch.txt
isassembler/SystemZ/insn-chhsi.txt
isassembler/SystemZ/insn-chi.txt
isassembler/SystemZ/insn-chrl.txt
isassembler/SystemZ/insn-chsi.txt
isassembler/SystemZ/insn-chy.txt
isassembler/SystemZ/insn-cl.txt
isassembler/SystemZ/insn-clfhsi.txt
isassembler/SystemZ/insn-clfi.txt
isassembler/SystemZ/insn-clg.txt
isassembler/SystemZ/insn-clgf.txt
isassembler/SystemZ/insn-clgfi.txt
isassembler/SystemZ/insn-clgfr.txt
isassembler/SystemZ/insn-clgfrl.txt
isassembler/SystemZ/insn-clghrl.txt
isassembler/SystemZ/insn-clghsi.txt
isassembler/SystemZ/insn-clgr.txt
isassembler/SystemZ/insn-clgrl.txt
isassembler/SystemZ/insn-clhhsi.txt
isassembler/SystemZ/insn-clhrl.txt
isassembler/SystemZ/insn-cli.txt
isassembler/SystemZ/insn-cliy.txt
isassembler/SystemZ/insn-clr.txt
isassembler/SystemZ/insn-clrl.txt
isassembler/SystemZ/insn-cly.txt
isassembler/SystemZ/insn-cpsdr.txt
isassembler/SystemZ/insn-cr.txt
isassembler/SystemZ/insn-crl.txt
isassembler/SystemZ/insn-cs.txt
isassembler/SystemZ/insn-csg.txt
isassembler/SystemZ/insn-csy.txt
isassembler/SystemZ/insn-cxbr.txt
isassembler/SystemZ/insn-cxfbr.txt
isassembler/SystemZ/insn-cxgbr.txt
isassembler/SystemZ/insn-cy.txt
isassembler/SystemZ/insn-ddb.txt
isassembler/SystemZ/insn-ddbr.txt
isassembler/SystemZ/insn-deb.txt
isassembler/SystemZ/insn-debr.txt
isassembler/SystemZ/insn-dl.txt
isassembler/SystemZ/insn-dlg.txt
isassembler/SystemZ/insn-dlgr.txt
isassembler/SystemZ/insn-dlr.txt
isassembler/SystemZ/insn-dsg.txt
isassembler/SystemZ/insn-dsgf.txt
isassembler/SystemZ/insn-dsgfr.txt
isassembler/SystemZ/insn-dsgr.txt
isassembler/SystemZ/insn-dxbr.txt
isassembler/SystemZ/insn-ear.txt
isassembler/SystemZ/insn-fidbr.txt
isassembler/SystemZ/insn-fiebr.txt
isassembler/SystemZ/insn-fixbr.txt
isassembler/SystemZ/insn-flogr.txt
isassembler/SystemZ/insn-ic.txt
isassembler/SystemZ/insn-icy.txt
isassembler/SystemZ/insn-iihf.txt
isassembler/SystemZ/insn-iihh.txt
isassembler/SystemZ/insn-iihl.txt
isassembler/SystemZ/insn-iilf.txt
isassembler/SystemZ/insn-iilh.txt
isassembler/SystemZ/insn-iill.txt
isassembler/SystemZ/insn-l.txt
isassembler/SystemZ/insn-la.txt
isassembler/SystemZ/insn-larl.txt
isassembler/SystemZ/insn-lay.txt
isassembler/SystemZ/insn-lb.txt
isassembler/SystemZ/insn-lbr.txt
isassembler/SystemZ/insn-lcdbr.txt
isassembler/SystemZ/insn-lcebr.txt
isassembler/SystemZ/insn-lcgfr.txt
isassembler/SystemZ/insn-lcgr.txt
isassembler/SystemZ/insn-lcr.txt
isassembler/SystemZ/insn-lcxbr.txt
isassembler/SystemZ/insn-ld.txt
isassembler/SystemZ/insn-ldeb.txt
isassembler/SystemZ/insn-ldebr.txt
isassembler/SystemZ/insn-ldgr.txt
isassembler/SystemZ/insn-ldr.txt
isassembler/SystemZ/insn-ldxbr.txt
isassembler/SystemZ/insn-ldy.txt
isassembler/SystemZ/insn-le.txt
isassembler/SystemZ/insn-ledbr.txt
isassembler/SystemZ/insn-ler.txt
isassembler/SystemZ/insn-lexbr.txt
isassembler/SystemZ/insn-ley.txt
isassembler/SystemZ/insn-lg.txt
isassembler/SystemZ/insn-lgb.txt
isassembler/SystemZ/insn-lgbr.txt
isassembler/SystemZ/insn-lgdr.txt
isassembler/SystemZ/insn-lgf.txt
isassembler/SystemZ/insn-lgfi.txt
isassembler/SystemZ/insn-lgfr.txt
isassembler/SystemZ/insn-lgfrl.txt
isassembler/SystemZ/insn-lgh.txt
isassembler/SystemZ/insn-lghi.txt
isassembler/SystemZ/insn-lghr.txt
isassembler/SystemZ/insn-lghrl.txt
isassembler/SystemZ/insn-lgr.txt
isassembler/SystemZ/insn-lgrl.txt
isassembler/SystemZ/insn-lh.txt
isassembler/SystemZ/insn-lhi.txt
isassembler/SystemZ/insn-lhr.txt
isassembler/SystemZ/insn-lhrl.txt
isassembler/SystemZ/insn-lhy.txt
isassembler/SystemZ/insn-llc.txt
isassembler/SystemZ/insn-llcr.txt
isassembler/SystemZ/insn-llgc.txt
isassembler/SystemZ/insn-llgcr.txt
isassembler/SystemZ/insn-llgf.txt
isassembler/SystemZ/insn-llgfr.txt
isassembler/SystemZ/insn-llgfrl.txt
isassembler/SystemZ/insn-llgh.txt
isassembler/SystemZ/insn-llghr.txt
isassembler/SystemZ/insn-llghrl.txt
isassembler/SystemZ/insn-llh.txt
isassembler/SystemZ/insn-llhr.txt
isassembler/SystemZ/insn-llhrl.txt
isassembler/SystemZ/insn-llihf.txt
isassembler/SystemZ/insn-llihh.txt
isassembler/SystemZ/insn-llihl.txt
isassembler/SystemZ/insn-llilf.txt
isassembler/SystemZ/insn-llilh.txt
isassembler/SystemZ/insn-llill.txt
isassembler/SystemZ/insn-lmg.txt
isassembler/SystemZ/insn-lndbr.txt
isassembler/SystemZ/insn-lnebr.txt
isassembler/SystemZ/insn-lnxbr.txt
isassembler/SystemZ/insn-lpdbr.txt
isassembler/SystemZ/insn-lpebr.txt
isassembler/SystemZ/insn-lpxbr.txt
isassembler/SystemZ/insn-lr.txt
isassembler/SystemZ/insn-lrl.txt
isassembler/SystemZ/insn-lrv.txt
isassembler/SystemZ/insn-lrvg.txt
isassembler/SystemZ/insn-lrvgr.txt
isassembler/SystemZ/insn-lrvr.txt
isassembler/SystemZ/insn-lxr.txt
isassembler/SystemZ/insn-ly.txt
isassembler/SystemZ/insn-lzdr.txt
isassembler/SystemZ/insn-lzer.txt
isassembler/SystemZ/insn-lzxr.txt
isassembler/SystemZ/insn-madb.txt
isassembler/SystemZ/insn-madbr.txt
isassembler/SystemZ/insn-maeb.txt
isassembler/SystemZ/insn-maebr.txt
isassembler/SystemZ/insn-mdb.txt
isassembler/SystemZ/insn-mdbr.txt
isassembler/SystemZ/insn-mdeb.txt
isassembler/SystemZ/insn-mdebr.txt
isassembler/SystemZ/insn-meeb.txt
isassembler/SystemZ/insn-meebr.txt
isassembler/SystemZ/insn-mghi.txt
isassembler/SystemZ/insn-mh.txt
isassembler/SystemZ/insn-mhi.txt
isassembler/SystemZ/insn-mhy.txt
isassembler/SystemZ/insn-mlg.txt
isassembler/SystemZ/insn-mlgr.txt
isassembler/SystemZ/insn-ms.txt
isassembler/SystemZ/insn-msdb.txt
isassembler/SystemZ/insn-msdbr.txt
isassembler/SystemZ/insn-mseb.txt
isassembler/SystemZ/insn-msebr.txt
isassembler/SystemZ/insn-msfi.txt
isassembler/SystemZ/insn-msg.txt
isassembler/SystemZ/insn-msgf.txt
isassembler/SystemZ/insn-msgfi.txt
isassembler/SystemZ/insn-msgfr.txt
isassembler/SystemZ/insn-msgr.txt
isassembler/SystemZ/insn-msr.txt
isassembler/SystemZ/insn-msy.txt
isassembler/SystemZ/insn-mvghi.txt
isassembler/SystemZ/insn-mvhhi.txt
isassembler/SystemZ/insn-mvhi.txt
isassembler/SystemZ/insn-mvi.txt
isassembler/SystemZ/insn-mviy.txt
isassembler/SystemZ/insn-mxbr.txt
isassembler/SystemZ/insn-mxdb.txt
isassembler/SystemZ/insn-mxdbr.txt
isassembler/SystemZ/insn-n.txt
isassembler/SystemZ/insn-ng.txt
isassembler/SystemZ/insn-ngr.txt
isassembler/SystemZ/insn-ni.txt
isassembler/SystemZ/insn-nihf.txt
isassembler/SystemZ/insn-nihh.txt
isassembler/SystemZ/insn-nihl.txt
isassembler/SystemZ/insn-nilf.txt
isassembler/SystemZ/insn-nilh.txt
isassembler/SystemZ/insn-nill.txt
isassembler/SystemZ/insn-niy.txt
isassembler/SystemZ/insn-nr.txt
isassembler/SystemZ/insn-ny.txt
isassembler/SystemZ/insn-o.txt
isassembler/SystemZ/insn-og.txt
isassembler/SystemZ/insn-ogr.txt
isassembler/SystemZ/insn-oi.txt
isassembler/SystemZ/insn-oihf.txt
isassembler/SystemZ/insn-oihh.txt
isassembler/SystemZ/insn-oihl.txt
isassembler/SystemZ/insn-oilf.txt
isassembler/SystemZ/insn-oilh.txt
isassembler/SystemZ/insn-oill.txt
isassembler/SystemZ/insn-oiy.txt
isassembler/SystemZ/insn-or.txt
isassembler/SystemZ/insn-oy.txt
isassembler/SystemZ/insn-risbg.txt
isassembler/SystemZ/insn-rll.txt
isassembler/SystemZ/insn-rllg.txt
isassembler/SystemZ/insn-s.txt
isassembler/SystemZ/insn-sdb.txt
isassembler/SystemZ/insn-sdbr.txt
isassembler/SystemZ/insn-seb.txt
isassembler/SystemZ/insn-sebr.txt
isassembler/SystemZ/insn-sg.txt
isassembler/SystemZ/insn-sgf.txt
isassembler/SystemZ/insn-sgfr.txt
isassembler/SystemZ/insn-sgr.txt
isassembler/SystemZ/insn-sl.txt
isassembler/SystemZ/insn-slb.txt
isassembler/SystemZ/insn-slbg.txt
isassembler/SystemZ/insn-slbgr.txt
isassembler/SystemZ/insn-slbr.txt
isassembler/SystemZ/insn-slfi.txt
isassembler/SystemZ/insn-slg.txt
isassembler/SystemZ/insn-slgf.txt
isassembler/SystemZ/insn-slgfi.txt
isassembler/SystemZ/insn-slgfr.txt
isassembler/SystemZ/insn-slgr.txt
isassembler/SystemZ/insn-sll.txt
isassembler/SystemZ/insn-sllg.txt
isassembler/SystemZ/insn-slr.txt
isassembler/SystemZ/insn-sly.txt
isassembler/SystemZ/insn-sqdb.txt
isassembler/SystemZ/insn-sqdbr.txt
isassembler/SystemZ/insn-sqeb.txt
isassembler/SystemZ/insn-sqebr.txt
isassembler/SystemZ/insn-sqxbr.txt
isassembler/SystemZ/insn-sr.txt
isassembler/SystemZ/insn-sra.txt
isassembler/SystemZ/insn-srag.txt
isassembler/SystemZ/insn-srl.txt
isassembler/SystemZ/insn-srlg.txt
isassembler/SystemZ/insn-st.txt
isassembler/SystemZ/insn-stc.txt
isassembler/SystemZ/insn-stcy.txt
isassembler/SystemZ/insn-std.txt
isassembler/SystemZ/insn-stdy.txt
isassembler/SystemZ/insn-ste.txt
isassembler/SystemZ/insn-stey.txt
isassembler/SystemZ/insn-stg.txt
isassembler/SystemZ/insn-stgrl.txt
isassembler/SystemZ/insn-sth.txt
isassembler/SystemZ/insn-sthrl.txt
isassembler/SystemZ/insn-sthy.txt
isassembler/SystemZ/insn-stmg.txt
isassembler/SystemZ/insn-strl.txt
isassembler/SystemZ/insn-strv.txt
isassembler/SystemZ/insn-strvg.txt
isassembler/SystemZ/insn-sty.txt
isassembler/SystemZ/insn-sxbr.txt
isassembler/SystemZ/insn-sy.txt
isassembler/SystemZ/insn-x.txt
isassembler/SystemZ/insn-xg.txt
isassembler/SystemZ/insn-xgr.txt
isassembler/SystemZ/insn-xi.txt
isassembler/SystemZ/insn-xihf.txt
isassembler/SystemZ/insn-xilf.txt
isassembler/SystemZ/insn-xiy.txt
isassembler/SystemZ/insn-xr.txt
isassembler/SystemZ/insn-xy.txt
isassembler/SystemZ/insns-pcrel.txt
isassembler/SystemZ/insns.txt
isassembler/SystemZ/invalid-regs-01.txt
isassembler/SystemZ/invalid-regs.txt
isassembler/SystemZ/unmapped-01.txt
isassembler/SystemZ/unmapped.txt
|
| 8580e79fba028e6d6085033617c0c566034cad54 |
15-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Consolidate assembler tests into 4 big tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181878 91177308-0d34-0410-b5e6-96231b3b80d8
ystemZ/insn-a-01.s
ystemZ/insn-a-02.s
ystemZ/insn-adb-01.s
ystemZ/insn-adb-02.s
ystemZ/insn-adbr-01.s
ystemZ/insn-aeb-01.s
ystemZ/insn-aeb-02.s
ystemZ/insn-aebr-01.s
ystemZ/insn-afi-01.s
ystemZ/insn-afi-02.s
ystemZ/insn-ag-01.s
ystemZ/insn-ag-02.s
ystemZ/insn-agf-01.s
ystemZ/insn-agf-02.s
ystemZ/insn-agfi-01.s
ystemZ/insn-agfi-02.s
ystemZ/insn-agfr-01.s
ystemZ/insn-aghi-01.s
ystemZ/insn-aghi-02.s
ystemZ/insn-agr-01.s
ystemZ/insn-agsi-01.s
ystemZ/insn-agsi-02.s
ystemZ/insn-ah-01.s
ystemZ/insn-ah-02.s
ystemZ/insn-ahi-01.s
ystemZ/insn-ahi-02.s
ystemZ/insn-ahy-01.s
ystemZ/insn-ahy-02.s
ystemZ/insn-al-01.s
ystemZ/insn-al-02.s
ystemZ/insn-alc-01.s
ystemZ/insn-alc-02.s
ystemZ/insn-alcg-01.s
ystemZ/insn-alcg-02.s
ystemZ/insn-alcgr-01.s
ystemZ/insn-alcr-01.s
ystemZ/insn-alfi-01.s
ystemZ/insn-alfi-02.s
ystemZ/insn-alg-01.s
ystemZ/insn-alg-02.s
ystemZ/insn-algf-01.s
ystemZ/insn-algf-02.s
ystemZ/insn-algfi-01.s
ystemZ/insn-algfi-02.s
ystemZ/insn-algfr-01.s
ystemZ/insn-algr-01.s
ystemZ/insn-alr-01.s
ystemZ/insn-aly-01.s
ystemZ/insn-aly-02.s
ystemZ/insn-ar-01.s
ystemZ/insn-asi-01.s
ystemZ/insn-asi-02.s
ystemZ/insn-axbr-01.s
ystemZ/insn-axbr-02.s
ystemZ/insn-ay-01.s
ystemZ/insn-ay-02.s
ystemZ/insn-bad.s
ystemZ/insn-basr-01.s
ystemZ/insn-br-01.s
ystemZ/insn-bras-01.s
ystemZ/insn-bras-02.s
ystemZ/insn-brasl-01.s
ystemZ/insn-brasl-02.s
ystemZ/insn-brc-01.s
ystemZ/insn-brc-02.s
ystemZ/insn-brcl-01.s
ystemZ/insn-brcl-02.s
ystemZ/insn-c-01.s
ystemZ/insn-c-02.s
ystemZ/insn-cdb-01.s
ystemZ/insn-cdb-02.s
ystemZ/insn-cdbr-01.s
ystemZ/insn-cdfbr-01.s
ystemZ/insn-cdfbr-02.s
ystemZ/insn-cdgbr-01.s
ystemZ/insn-cdgbr-02.s
ystemZ/insn-ceb-01.s
ystemZ/insn-ceb-02.s
ystemZ/insn-cebr-01.s
ystemZ/insn-cefbr-01.s
ystemZ/insn-cefbr-02.s
ystemZ/insn-cegbr-01.s
ystemZ/insn-cegbr-02.s
ystemZ/insn-cfdbr-01.s
ystemZ/insn-cfdbr-02.s
ystemZ/insn-cfebr-01.s
ystemZ/insn-cfebr-02.s
ystemZ/insn-cfi-01.s
ystemZ/insn-cfi-02.s
ystemZ/insn-cfxbr-01.s
ystemZ/insn-cfxbr-02.s
ystemZ/insn-cg-01.s
ystemZ/insn-cg-02.s
ystemZ/insn-cgdbr-01.s
ystemZ/insn-cgdbr-02.s
ystemZ/insn-cgebr-01.s
ystemZ/insn-cgebr-02.s
ystemZ/insn-cgf-01.s
ystemZ/insn-cgf-02.s
ystemZ/insn-cgfi-01.s
ystemZ/insn-cgfi-02.s
ystemZ/insn-cgfr-01.s
ystemZ/insn-cgfrl-01.s
ystemZ/insn-cgfrl-02.s
ystemZ/insn-cgh-01.s
ystemZ/insn-cgh-02.s
ystemZ/insn-cghi-01.s
ystemZ/insn-cghi-02.s
ystemZ/insn-cghrl-01.s
ystemZ/insn-cghrl-02.s
ystemZ/insn-cghsi-01.s
ystemZ/insn-cghsi-02.s
ystemZ/insn-cgr-01.s
ystemZ/insn-cgrl-01.s
ystemZ/insn-cgrl-02.s
ystemZ/insn-cgxbr-01.s
ystemZ/insn-cgxbr-02.s
ystemZ/insn-ch-01.s
ystemZ/insn-ch-02.s
ystemZ/insn-chhsi-01.s
ystemZ/insn-chhsi-02.s
ystemZ/insn-chi-01.s
ystemZ/insn-chi-02.s
ystemZ/insn-chrl-01.s
ystemZ/insn-chrl-02.s
ystemZ/insn-chsi-01.s
ystemZ/insn-chsi-02.s
ystemZ/insn-chy-01.s
ystemZ/insn-chy-02.s
ystemZ/insn-cl-01.s
ystemZ/insn-cl-02.s
ystemZ/insn-clfhsi-01.s
ystemZ/insn-clfhsi-02.s
ystemZ/insn-clfi-01.s
ystemZ/insn-clfi-02.s
ystemZ/insn-clg-01.s
ystemZ/insn-clg-02.s
ystemZ/insn-clgf-01.s
ystemZ/insn-clgf-02.s
ystemZ/insn-clgfi-01.s
ystemZ/insn-clgfi-02.s
ystemZ/insn-clgfr-01.s
ystemZ/insn-clgfrl-01.s
ystemZ/insn-clgfrl-02.s
ystemZ/insn-clghrl-01.s
ystemZ/insn-clghrl-02.s
ystemZ/insn-clghsi-01.s
ystemZ/insn-clghsi-02.s
ystemZ/insn-clgr-01.s
ystemZ/insn-clgrl-01.s
ystemZ/insn-clgrl-02.s
ystemZ/insn-clhhsi-01.s
ystemZ/insn-clhhsi-02.s
ystemZ/insn-clhrl-01.s
ystemZ/insn-clhrl-02.s
ystemZ/insn-cli-01.s
ystemZ/insn-cli-02.s
ystemZ/insn-cliy-01.s
ystemZ/insn-cliy-02.s
ystemZ/insn-clr-01.s
ystemZ/insn-clrl-01.s
ystemZ/insn-clrl-02.s
ystemZ/insn-cly-01.s
ystemZ/insn-cly-02.s
ystemZ/insn-cpsdr-01.s
ystemZ/insn-cr-01.s
ystemZ/insn-crl-01.s
ystemZ/insn-crl-02.s
ystemZ/insn-cs-01.s
ystemZ/insn-cs-02.s
ystemZ/insn-csg-01.s
ystemZ/insn-csg-02.s
ystemZ/insn-csy-01.s
ystemZ/insn-csy-02.s
ystemZ/insn-cxbr-01.s
ystemZ/insn-cxbr-02.s
ystemZ/insn-cxfbr-01.s
ystemZ/insn-cxfbr-02.s
ystemZ/insn-cxgbr-01.s
ystemZ/insn-cxgbr-02.s
ystemZ/insn-cy-01.s
ystemZ/insn-cy-02.s
ystemZ/insn-ddb-01.s
ystemZ/insn-ddb-02.s
ystemZ/insn-ddbr-01.s
ystemZ/insn-deb-01.s
ystemZ/insn-deb-02.s
ystemZ/insn-debr-01.s
ystemZ/insn-dl-01.s
ystemZ/insn-dl-02.s
ystemZ/insn-dlg-01.s
ystemZ/insn-dlg-02.s
ystemZ/insn-dlgr-01.s
ystemZ/insn-dlgr-02.s
ystemZ/insn-dlr-01.s
ystemZ/insn-dlr-02.s
ystemZ/insn-dsg-01.s
ystemZ/insn-dsg-02.s
ystemZ/insn-dsgf-01.s
ystemZ/insn-dsgf-02.s
ystemZ/insn-dsgfr-01.s
ystemZ/insn-dsgfr-02.s
ystemZ/insn-dsgr-01.s
ystemZ/insn-dsgr-02.s
ystemZ/insn-dxbr-01.s
ystemZ/insn-dxbr-02.s
ystemZ/insn-ear-01.s
ystemZ/insn-ear-02.s
ystemZ/insn-fidbr-01.s
ystemZ/insn-fidbr-02.s
ystemZ/insn-fiebr-01.s
ystemZ/insn-fiebr-02.s
ystemZ/insn-fixbr-01.s
ystemZ/insn-fixbr-02.s
ystemZ/insn-flogr-01.s
ystemZ/insn-flogr-02.s
ystemZ/insn-good.s
ystemZ/insn-ic-01.s
ystemZ/insn-ic-02.s
ystemZ/insn-icy-01.s
ystemZ/insn-icy-02.s
ystemZ/insn-iihf-01.s
ystemZ/insn-iihf-02.s
ystemZ/insn-iihh-01.s
ystemZ/insn-iihh-02.s
ystemZ/insn-iihl-01.s
ystemZ/insn-iihl-02.s
ystemZ/insn-iilf-01.s
ystemZ/insn-iilf-02.s
ystemZ/insn-iilh-01.s
ystemZ/insn-iilh-02.s
ystemZ/insn-iill-01.s
ystemZ/insn-iill-02.s
ystemZ/insn-l-01.s
ystemZ/insn-l-02.s
ystemZ/insn-la-01.s
ystemZ/insn-la-02.s
ystemZ/insn-larl-01.s
ystemZ/insn-larl-02.s
ystemZ/insn-lay-01.s
ystemZ/insn-lay-02.s
ystemZ/insn-lb-01.s
ystemZ/insn-lb-02.s
ystemZ/insn-lbr-01.s
ystemZ/insn-lcdbr-01.s
ystemZ/insn-lcebr-01.s
ystemZ/insn-lcgfr-01.s
ystemZ/insn-lcgr-01.s
ystemZ/insn-lcr-01.s
ystemZ/insn-lcxbr-01.s
ystemZ/insn-lcxbr-02.s
ystemZ/insn-ld-01.s
ystemZ/insn-ld-02.s
ystemZ/insn-ldeb-01.s
ystemZ/insn-ldeb-02.s
ystemZ/insn-ldebr-01.s
ystemZ/insn-ldgr-01.s
ystemZ/insn-ldgr-02.s
ystemZ/insn-ldr-01.s
ystemZ/insn-ldxbr-01.s
ystemZ/insn-ldxbr-02.s
ystemZ/insn-ldy-01.s
ystemZ/insn-ldy-02.s
ystemZ/insn-le-01.s
ystemZ/insn-le-02.s
ystemZ/insn-ledbr-01.s
ystemZ/insn-ler-01.s
ystemZ/insn-lexbr-01.s
ystemZ/insn-lexbr-02.s
ystemZ/insn-ley-01.s
ystemZ/insn-ley-02.s
ystemZ/insn-lg-01.s
ystemZ/insn-lg-02.s
ystemZ/insn-lgb-01.s
ystemZ/insn-lgb-02.s
ystemZ/insn-lgbr-01.s
ystemZ/insn-lgdr-01.s
ystemZ/insn-lgdr-02.s
ystemZ/insn-lgf-01.s
ystemZ/insn-lgf-02.s
ystemZ/insn-lgfi-01.s
ystemZ/insn-lgfi-02.s
ystemZ/insn-lgfr-01.s
ystemZ/insn-lgfrl-01.s
ystemZ/insn-lgfrl-02.s
ystemZ/insn-lgh-01.s
ystemZ/insn-lgh-02.s
ystemZ/insn-lghi-01.s
ystemZ/insn-lghi-02.s
ystemZ/insn-lghr-01.s
ystemZ/insn-lghrl-01.s
ystemZ/insn-lghrl-02.s
ystemZ/insn-lgr-01.s
ystemZ/insn-lgrl-01.s
ystemZ/insn-lgrl-02.s
ystemZ/insn-lh-01.s
ystemZ/insn-lh-02.s
ystemZ/insn-lhi-01.s
ystemZ/insn-lhi-02.s
ystemZ/insn-lhr-01.s
ystemZ/insn-lhrl-01.s
ystemZ/insn-lhrl-02.s
ystemZ/insn-lhy-01.s
ystemZ/insn-lhy-02.s
ystemZ/insn-llc-01.s
ystemZ/insn-llc-02.s
ystemZ/insn-llcr-01.s
ystemZ/insn-llgc-01.s
ystemZ/insn-llgc-02.s
ystemZ/insn-llgcr-01.s
ystemZ/insn-llgf-01.s
ystemZ/insn-llgf-02.s
ystemZ/insn-llgfr-01.s
ystemZ/insn-llgfrl-01.s
ystemZ/insn-llgfrl-02.s
ystemZ/insn-llgh-01.s
ystemZ/insn-llgh-02.s
ystemZ/insn-llghr-01.s
ystemZ/insn-llghrl-01.s
ystemZ/insn-llghrl-02.s
ystemZ/insn-llh-01.s
ystemZ/insn-llh-02.s
ystemZ/insn-llhr-01.s
ystemZ/insn-llhrl-01.s
ystemZ/insn-llhrl-02.s
ystemZ/insn-llihf-01.s
ystemZ/insn-llihf-02.s
ystemZ/insn-llihh-01.s
ystemZ/insn-llihh-02.s
ystemZ/insn-llihl-01.s
ystemZ/insn-llihl-02.s
ystemZ/insn-llilf-01.s
ystemZ/insn-llilf-02.s
ystemZ/insn-llilh-01.s
ystemZ/insn-llilh-02.s
ystemZ/insn-llill-01.s
ystemZ/insn-llill-02.s
ystemZ/insn-lmg-01.s
ystemZ/insn-lmg-02.s
ystemZ/insn-lndbr-01.s
ystemZ/insn-lnebr-01.s
ystemZ/insn-lnxbr-01.s
ystemZ/insn-lnxbr-02.s
ystemZ/insn-lpdbr-01.s
ystemZ/insn-lpebr-01.s
ystemZ/insn-lpxbr-01.s
ystemZ/insn-lpxbr-02.s
ystemZ/insn-lr-01.s
ystemZ/insn-lrl-01.s
ystemZ/insn-lrl-02.s
ystemZ/insn-lrv-01.s
ystemZ/insn-lrv-02.s
ystemZ/insn-lrvg-01.s
ystemZ/insn-lrvg-02.s
ystemZ/insn-lrvgr-01.s
ystemZ/insn-lrvr-01.s
ystemZ/insn-lxr-01.s
ystemZ/insn-lxr-02.s
ystemZ/insn-ly-01.s
ystemZ/insn-ly-02.s
ystemZ/insn-lzdr-01.s
ystemZ/insn-lzer-01.s
ystemZ/insn-lzxr-01.s
ystemZ/insn-lzxr-02.s
ystemZ/insn-madb-01.s
ystemZ/insn-madb-02.s
ystemZ/insn-madbr-01.s
ystemZ/insn-maeb-01.s
ystemZ/insn-maeb-02.s
ystemZ/insn-maebr-01.s
ystemZ/insn-mdb-01.s
ystemZ/insn-mdb-02.s
ystemZ/insn-mdbr-01.s
ystemZ/insn-mdeb-01.s
ystemZ/insn-mdeb-02.s
ystemZ/insn-mdebr-01.s
ystemZ/insn-meeb-01.s
ystemZ/insn-meeb-02.s
ystemZ/insn-meebr-01.s
ystemZ/insn-mghi-01.s
ystemZ/insn-mghi-02.s
ystemZ/insn-mh-01.s
ystemZ/insn-mh-02.s
ystemZ/insn-mhi-01.s
ystemZ/insn-mhi-02.s
ystemZ/insn-mhy-01.s
ystemZ/insn-mhy-02.s
ystemZ/insn-mlg-01.s
ystemZ/insn-mlg-02.s
ystemZ/insn-mlgr-01.s
ystemZ/insn-mlgr-02.s
ystemZ/insn-ms-01.s
ystemZ/insn-ms-02.s
ystemZ/insn-msdb-01.s
ystemZ/insn-msdb-02.s
ystemZ/insn-msdbr-01.s
ystemZ/insn-mseb-01.s
ystemZ/insn-mseb-02.s
ystemZ/insn-msebr-01.s
ystemZ/insn-msfi-01.s
ystemZ/insn-msfi-02.s
ystemZ/insn-msg-01.s
ystemZ/insn-msg-02.s
ystemZ/insn-msgf-01.s
ystemZ/insn-msgf-02.s
ystemZ/insn-msgfi-01.s
ystemZ/insn-msgfi-02.s
ystemZ/insn-msgfr-01.s
ystemZ/insn-msgr-01.s
ystemZ/insn-msr-01.s
ystemZ/insn-msy-01.s
ystemZ/insn-msy-02.s
ystemZ/insn-mvghi-01.s
ystemZ/insn-mvghi-02.s
ystemZ/insn-mvhhi-01.s
ystemZ/insn-mvhhi-02.s
ystemZ/insn-mvhi-01.s
ystemZ/insn-mvhi-02.s
ystemZ/insn-mvi-01.s
ystemZ/insn-mvi-02.s
ystemZ/insn-mviy-01.s
ystemZ/insn-mviy-02.s
ystemZ/insn-mxbr-01.s
ystemZ/insn-mxbr-02.s
ystemZ/insn-mxdb-01.s
ystemZ/insn-mxdb-02.s
ystemZ/insn-mxdbr-01.s
ystemZ/insn-mxdbr-02.s
ystemZ/insn-n-01.s
ystemZ/insn-n-02.s
ystemZ/insn-ng-01.s
ystemZ/insn-ng-02.s
ystemZ/insn-ngr-01.s
ystemZ/insn-ni-01.s
ystemZ/insn-ni-02.s
ystemZ/insn-nihf-01.s
ystemZ/insn-nihf-02.s
ystemZ/insn-nihh-01.s
ystemZ/insn-nihh-02.s
ystemZ/insn-nihl-01.s
ystemZ/insn-nihl-02.s
ystemZ/insn-nilf-01.s
ystemZ/insn-nilf-02.s
ystemZ/insn-nilh-01.s
ystemZ/insn-nilh-02.s
ystemZ/insn-nill-01.s
ystemZ/insn-nill-02.s
ystemZ/insn-niy-01.s
ystemZ/insn-niy-02.s
ystemZ/insn-nr-01.s
ystemZ/insn-ny-01.s
ystemZ/insn-ny-02.s
ystemZ/insn-o-01.s
ystemZ/insn-o-02.s
ystemZ/insn-og-01.s
ystemZ/insn-og-02.s
ystemZ/insn-ogr-01.s
ystemZ/insn-oi-01.s
ystemZ/insn-oi-02.s
ystemZ/insn-oihf-01.s
ystemZ/insn-oihf-02.s
ystemZ/insn-oihh-01.s
ystemZ/insn-oihh-02.s
ystemZ/insn-oihl-01.s
ystemZ/insn-oihl-02.s
ystemZ/insn-oilf-01.s
ystemZ/insn-oilf-02.s
ystemZ/insn-oilh-01.s
ystemZ/insn-oilh-02.s
ystemZ/insn-oill-01.s
ystemZ/insn-oill-02.s
ystemZ/insn-oiy-01.s
ystemZ/insn-oiy-02.s
ystemZ/insn-or-01.s
ystemZ/insn-oy-01.s
ystemZ/insn-oy-02.s
ystemZ/insn-risbg-01.s
ystemZ/insn-risbg-02.s
ystemZ/insn-rll-01.s
ystemZ/insn-rll-02.s
ystemZ/insn-rllg-01.s
ystemZ/insn-rllg-02.s
ystemZ/insn-s-01.s
ystemZ/insn-s-02.s
ystemZ/insn-sdb-01.s
ystemZ/insn-sdb-02.s
ystemZ/insn-sdbr-01.s
ystemZ/insn-seb-01.s
ystemZ/insn-seb-02.s
ystemZ/insn-sebr-01.s
ystemZ/insn-sg-01.s
ystemZ/insn-sg-02.s
ystemZ/insn-sgf-01.s
ystemZ/insn-sgf-02.s
ystemZ/insn-sgfr-01.s
ystemZ/insn-sgr-01.s
ystemZ/insn-sl-01.s
ystemZ/insn-sl-02.s
ystemZ/insn-slb-01.s
ystemZ/insn-slb-02.s
ystemZ/insn-slbg-01.s
ystemZ/insn-slbg-02.s
ystemZ/insn-slbgr-01.s
ystemZ/insn-slbr-01.s
ystemZ/insn-slfi-01.s
ystemZ/insn-slfi-02.s
ystemZ/insn-slg-01.s
ystemZ/insn-slg-02.s
ystemZ/insn-slgf-01.s
ystemZ/insn-slgf-02.s
ystemZ/insn-slgfi-01.s
ystemZ/insn-slgfi-02.s
ystemZ/insn-slgfr-01.s
ystemZ/insn-slgr-01.s
ystemZ/insn-sll-01.s
ystemZ/insn-sll-02.s
ystemZ/insn-sllg-01.s
ystemZ/insn-sllg-02.s
ystemZ/insn-slr-01.s
ystemZ/insn-sly-01.s
ystemZ/insn-sly-02.s
ystemZ/insn-sqdb-01.s
ystemZ/insn-sqdb-02.s
ystemZ/insn-sqdbr-01.s
ystemZ/insn-sqeb-01.s
ystemZ/insn-sqeb-02.s
ystemZ/insn-sqebr-01.s
ystemZ/insn-sqxbr-01.s
ystemZ/insn-sqxbr-02.s
ystemZ/insn-sr-01.s
ystemZ/insn-sra-01.s
ystemZ/insn-sra-02.s
ystemZ/insn-srag-01.s
ystemZ/insn-srag-02.s
ystemZ/insn-srl-01.s
ystemZ/insn-srl-02.s
ystemZ/insn-srlg-01.s
ystemZ/insn-srlg-02.s
ystemZ/insn-st-01.s
ystemZ/insn-st-02.s
ystemZ/insn-stc-01.s
ystemZ/insn-stc-02.s
ystemZ/insn-stcy-01.s
ystemZ/insn-stcy-02.s
ystemZ/insn-std-01.s
ystemZ/insn-std-02.s
ystemZ/insn-stdy-01.s
ystemZ/insn-stdy-02.s
ystemZ/insn-ste-01.s
ystemZ/insn-ste-02.s
ystemZ/insn-stey-01.s
ystemZ/insn-stey-02.s
ystemZ/insn-stg-01.s
ystemZ/insn-stg-02.s
ystemZ/insn-stgrl-01.s
ystemZ/insn-stgrl-02.s
ystemZ/insn-sth-01.s
ystemZ/insn-sth-02.s
ystemZ/insn-sthrl-01.s
ystemZ/insn-sthrl-02.s
ystemZ/insn-sthy-01.s
ystemZ/insn-sthy-02.s
ystemZ/insn-stmg-01.s
ystemZ/insn-stmg-02.s
ystemZ/insn-strl-01.s
ystemZ/insn-strl-02.s
ystemZ/insn-strv-01.s
ystemZ/insn-strv-02.s
ystemZ/insn-strvg-01.s
ystemZ/insn-strvg-02.s
ystemZ/insn-sty-01.s
ystemZ/insn-sty-02.s
ystemZ/insn-sxbr-01.s
ystemZ/insn-sxbr-02.s
ystemZ/insn-sy-01.s
ystemZ/insn-sy-02.s
ystemZ/insn-x-01.s
ystemZ/insn-x-02.s
ystemZ/insn-xg-01.s
ystemZ/insn-xg-02.s
ystemZ/insn-xgr-01.s
ystemZ/insn-xi-01.s
ystemZ/insn-xi-02.s
ystemZ/insn-xihf-01.s
ystemZ/insn-xihf-02.s
ystemZ/insn-xilf-01.s
ystemZ/insn-xilf-02.s
ystemZ/insn-xiy-01.s
ystemZ/insn-xiy-02.s
ystemZ/insn-xr-01.s
ystemZ/insn-xy-01.s
ystemZ/insn-xy-02.s
ystemZ/regs-01.s
ystemZ/regs-02.s
ystemZ/regs-03.s
ystemZ/regs-04.s
ystemZ/regs-05.s
ystemZ/regs-06.s
ystemZ/regs-07.s
ystemZ/regs-08.s
ystemZ/regs-09.s
ystemZ/regs-10.s
ystemZ/regs-11.s
ystemZ/regs-12.s
ystemZ/regs-13.s
ystemZ/regs-14.s
ystemZ/regs-15.s
ystemZ/regs-bad.s
ystemZ/regs-good.s
|
| 5bbdb190412a55436b808cfa59820b1e6cf08db0 |
14-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Implement the PowerPC system call (sc) instruction.
Instruction added at request of Roman Divacky. Tested via asm-parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding.s
|
| ed788b62830c26bd1f5d23d73a6337c88b66ab61 |
14-May-2013 |
Derek Schuff <dschuff@google.com> |
Fix ARM FastISel tests, as a first step to enabling ARM FastISel
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on
enabling it for other targets. As a first step I've fixed some of the tests.
Changes to ARM FastISel tests:
- Different triples don't generate the same relocations (especially
movw/movt versus constant pool loads). Use a regex to allow either.
- Mangling is different. Use a regex to allow either.
- The reserved registers are sometimes different, so registers get
allocated in a different order. Capture the names only where this
occurs.
- Add -verify-machineinstrs to some tests where it works. It doesn't
work everywhere it should yet.
- Add -fast-isel-abort to many tests that didn't have it before.
- Split out the VarArg test from fast-isel-call.ll into its own
test. This simplifies test setup because of --check-prefix.
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
RM/data-in-code.ll
|
| c3b20c260ee17a66c6306f81293c75681d8ea0aa |
14-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add disassembler support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/SystemZ/insn-a.txt
isassembler/SystemZ/insn-adb.txt
isassembler/SystemZ/insn-adbr.txt
isassembler/SystemZ/insn-aeb.txt
isassembler/SystemZ/insn-aebr.txt
isassembler/SystemZ/insn-afi.txt
isassembler/SystemZ/insn-ag.txt
isassembler/SystemZ/insn-agf.txt
isassembler/SystemZ/insn-agfi.txt
isassembler/SystemZ/insn-agfr.txt
isassembler/SystemZ/insn-aghi.txt
isassembler/SystemZ/insn-agr.txt
isassembler/SystemZ/insn-agsi.txt
isassembler/SystemZ/insn-ah.txt
isassembler/SystemZ/insn-ahi.txt
isassembler/SystemZ/insn-ahy.txt
isassembler/SystemZ/insn-al.txt
isassembler/SystemZ/insn-alc.txt
isassembler/SystemZ/insn-alcg.txt
isassembler/SystemZ/insn-alcgr.txt
isassembler/SystemZ/insn-alcr.txt
isassembler/SystemZ/insn-alfi.txt
isassembler/SystemZ/insn-alg.txt
isassembler/SystemZ/insn-algf.txt
isassembler/SystemZ/insn-algfi.txt
isassembler/SystemZ/insn-algfr.txt
isassembler/SystemZ/insn-algr.txt
isassembler/SystemZ/insn-alr.txt
isassembler/SystemZ/insn-aly.txt
isassembler/SystemZ/insn-ar.txt
isassembler/SystemZ/insn-asi.txt
isassembler/SystemZ/insn-axbr.txt
isassembler/SystemZ/insn-ay.txt
isassembler/SystemZ/insn-basr.txt
isassembler/SystemZ/insn-br.txt
isassembler/SystemZ/insn-bras.txt
isassembler/SystemZ/insn-brasl.txt
isassembler/SystemZ/insn-brc.txt
isassembler/SystemZ/insn-brcl.txt
isassembler/SystemZ/insn-c.txt
isassembler/SystemZ/insn-cdb.txt
isassembler/SystemZ/insn-cdbr.txt
isassembler/SystemZ/insn-cdfbr.txt
isassembler/SystemZ/insn-cdgbr.txt
isassembler/SystemZ/insn-ceb.txt
isassembler/SystemZ/insn-cebr.txt
isassembler/SystemZ/insn-cefbr.txt
isassembler/SystemZ/insn-cegbr.txt
isassembler/SystemZ/insn-cfdbr.txt
isassembler/SystemZ/insn-cfebr.txt
isassembler/SystemZ/insn-cfi.txt
isassembler/SystemZ/insn-cfxbr.txt
isassembler/SystemZ/insn-cg.txt
isassembler/SystemZ/insn-cgdbr.txt
isassembler/SystemZ/insn-cgebr.txt
isassembler/SystemZ/insn-cgf.txt
isassembler/SystemZ/insn-cgfi.txt
isassembler/SystemZ/insn-cgfr.txt
isassembler/SystemZ/insn-cgfrl.txt
isassembler/SystemZ/insn-cgh.txt
isassembler/SystemZ/insn-cghi.txt
isassembler/SystemZ/insn-cghrl.txt
isassembler/SystemZ/insn-cghsi.txt
isassembler/SystemZ/insn-cgr.txt
isassembler/SystemZ/insn-cgrl.txt
isassembler/SystemZ/insn-cgxbr.txt
isassembler/SystemZ/insn-ch.txt
isassembler/SystemZ/insn-chhsi.txt
isassembler/SystemZ/insn-chi.txt
isassembler/SystemZ/insn-chrl.txt
isassembler/SystemZ/insn-chsi.txt
isassembler/SystemZ/insn-chy.txt
isassembler/SystemZ/insn-cl.txt
isassembler/SystemZ/insn-clfhsi.txt
isassembler/SystemZ/insn-clfi.txt
isassembler/SystemZ/insn-clg.txt
isassembler/SystemZ/insn-clgf.txt
isassembler/SystemZ/insn-clgfi.txt
isassembler/SystemZ/insn-clgfr.txt
isassembler/SystemZ/insn-clgfrl.txt
isassembler/SystemZ/insn-clghrl.txt
isassembler/SystemZ/insn-clghsi.txt
isassembler/SystemZ/insn-clgr.txt
isassembler/SystemZ/insn-clgrl.txt
isassembler/SystemZ/insn-clhhsi.txt
isassembler/SystemZ/insn-clhrl.txt
isassembler/SystemZ/insn-cli.txt
isassembler/SystemZ/insn-cliy.txt
isassembler/SystemZ/insn-clr.txt
isassembler/SystemZ/insn-clrl.txt
isassembler/SystemZ/insn-cly.txt
isassembler/SystemZ/insn-cpsdr.txt
isassembler/SystemZ/insn-cr.txt
isassembler/SystemZ/insn-crl.txt
isassembler/SystemZ/insn-cs.txt
isassembler/SystemZ/insn-csg.txt
isassembler/SystemZ/insn-csy.txt
isassembler/SystemZ/insn-cxbr.txt
isassembler/SystemZ/insn-cxfbr.txt
isassembler/SystemZ/insn-cxgbr.txt
isassembler/SystemZ/insn-cy.txt
isassembler/SystemZ/insn-ddb.txt
isassembler/SystemZ/insn-ddbr.txt
isassembler/SystemZ/insn-deb.txt
isassembler/SystemZ/insn-debr.txt
isassembler/SystemZ/insn-dl.txt
isassembler/SystemZ/insn-dlg.txt
isassembler/SystemZ/insn-dlgr.txt
isassembler/SystemZ/insn-dlr.txt
isassembler/SystemZ/insn-dsg.txt
isassembler/SystemZ/insn-dsgf.txt
isassembler/SystemZ/insn-dsgfr.txt
isassembler/SystemZ/insn-dsgr.txt
isassembler/SystemZ/insn-dxbr.txt
isassembler/SystemZ/insn-ear.txt
isassembler/SystemZ/insn-fidbr.txt
isassembler/SystemZ/insn-fiebr.txt
isassembler/SystemZ/insn-fixbr.txt
isassembler/SystemZ/insn-flogr.txt
isassembler/SystemZ/insn-ic.txt
isassembler/SystemZ/insn-icy.txt
isassembler/SystemZ/insn-iihf.txt
isassembler/SystemZ/insn-iihh.txt
isassembler/SystemZ/insn-iihl.txt
isassembler/SystemZ/insn-iilf.txt
isassembler/SystemZ/insn-iilh.txt
isassembler/SystemZ/insn-iill.txt
isassembler/SystemZ/insn-l.txt
isassembler/SystemZ/insn-la.txt
isassembler/SystemZ/insn-larl.txt
isassembler/SystemZ/insn-lay.txt
isassembler/SystemZ/insn-lb.txt
isassembler/SystemZ/insn-lbr.txt
isassembler/SystemZ/insn-lcdbr.txt
isassembler/SystemZ/insn-lcebr.txt
isassembler/SystemZ/insn-lcgfr.txt
isassembler/SystemZ/insn-lcgr.txt
isassembler/SystemZ/insn-lcr.txt
isassembler/SystemZ/insn-lcxbr.txt
isassembler/SystemZ/insn-ld.txt
isassembler/SystemZ/insn-ldeb.txt
isassembler/SystemZ/insn-ldebr.txt
isassembler/SystemZ/insn-ldgr.txt
isassembler/SystemZ/insn-ldr.txt
isassembler/SystemZ/insn-ldxbr.txt
isassembler/SystemZ/insn-ldy.txt
isassembler/SystemZ/insn-le.txt
isassembler/SystemZ/insn-ledbr.txt
isassembler/SystemZ/insn-ler.txt
isassembler/SystemZ/insn-lexbr.txt
isassembler/SystemZ/insn-ley.txt
isassembler/SystemZ/insn-lg.txt
isassembler/SystemZ/insn-lgb.txt
isassembler/SystemZ/insn-lgbr.txt
isassembler/SystemZ/insn-lgdr.txt
isassembler/SystemZ/insn-lgf.txt
isassembler/SystemZ/insn-lgfi.txt
isassembler/SystemZ/insn-lgfr.txt
isassembler/SystemZ/insn-lgfrl.txt
isassembler/SystemZ/insn-lgh.txt
isassembler/SystemZ/insn-lghi.txt
isassembler/SystemZ/insn-lghr.txt
isassembler/SystemZ/insn-lghrl.txt
isassembler/SystemZ/insn-lgr.txt
isassembler/SystemZ/insn-lgrl.txt
isassembler/SystemZ/insn-lh.txt
isassembler/SystemZ/insn-lhi.txt
isassembler/SystemZ/insn-lhr.txt
isassembler/SystemZ/insn-lhrl.txt
isassembler/SystemZ/insn-lhy.txt
isassembler/SystemZ/insn-llc.txt
isassembler/SystemZ/insn-llcr.txt
isassembler/SystemZ/insn-llgc.txt
isassembler/SystemZ/insn-llgcr.txt
isassembler/SystemZ/insn-llgf.txt
isassembler/SystemZ/insn-llgfr.txt
isassembler/SystemZ/insn-llgfrl.txt
isassembler/SystemZ/insn-llgh.txt
isassembler/SystemZ/insn-llghr.txt
isassembler/SystemZ/insn-llghrl.txt
isassembler/SystemZ/insn-llh.txt
isassembler/SystemZ/insn-llhr.txt
isassembler/SystemZ/insn-llhrl.txt
isassembler/SystemZ/insn-llihf.txt
isassembler/SystemZ/insn-llihh.txt
isassembler/SystemZ/insn-llihl.txt
isassembler/SystemZ/insn-llilf.txt
isassembler/SystemZ/insn-llilh.txt
isassembler/SystemZ/insn-llill.txt
isassembler/SystemZ/insn-lmg.txt
isassembler/SystemZ/insn-lndbr.txt
isassembler/SystemZ/insn-lnebr.txt
isassembler/SystemZ/insn-lnxbr.txt
isassembler/SystemZ/insn-lpdbr.txt
isassembler/SystemZ/insn-lpebr.txt
isassembler/SystemZ/insn-lpxbr.txt
isassembler/SystemZ/insn-lr.txt
isassembler/SystemZ/insn-lrl.txt
isassembler/SystemZ/insn-lrv.txt
isassembler/SystemZ/insn-lrvg.txt
isassembler/SystemZ/insn-lrvgr.txt
isassembler/SystemZ/insn-lrvr.txt
isassembler/SystemZ/insn-lxr.txt
isassembler/SystemZ/insn-ly.txt
isassembler/SystemZ/insn-lzdr.txt
isassembler/SystemZ/insn-lzer.txt
isassembler/SystemZ/insn-lzxr.txt
isassembler/SystemZ/insn-madb.txt
isassembler/SystemZ/insn-madbr.txt
isassembler/SystemZ/insn-maeb.txt
isassembler/SystemZ/insn-maebr.txt
isassembler/SystemZ/insn-mdb.txt
isassembler/SystemZ/insn-mdbr.txt
isassembler/SystemZ/insn-mdeb.txt
isassembler/SystemZ/insn-mdebr.txt
isassembler/SystemZ/insn-meeb.txt
isassembler/SystemZ/insn-meebr.txt
isassembler/SystemZ/insn-mghi.txt
isassembler/SystemZ/insn-mh.txt
isassembler/SystemZ/insn-mhi.txt
isassembler/SystemZ/insn-mhy.txt
isassembler/SystemZ/insn-mlg.txt
isassembler/SystemZ/insn-mlgr.txt
isassembler/SystemZ/insn-ms.txt
isassembler/SystemZ/insn-msdb.txt
isassembler/SystemZ/insn-msdbr.txt
isassembler/SystemZ/insn-mseb.txt
isassembler/SystemZ/insn-msebr.txt
isassembler/SystemZ/insn-msfi.txt
isassembler/SystemZ/insn-msg.txt
isassembler/SystemZ/insn-msgf.txt
isassembler/SystemZ/insn-msgfi.txt
isassembler/SystemZ/insn-msgfr.txt
isassembler/SystemZ/insn-msgr.txt
isassembler/SystemZ/insn-msr.txt
isassembler/SystemZ/insn-msy.txt
isassembler/SystemZ/insn-mvghi.txt
isassembler/SystemZ/insn-mvhhi.txt
isassembler/SystemZ/insn-mvhi.txt
isassembler/SystemZ/insn-mvi.txt
isassembler/SystemZ/insn-mviy.txt
isassembler/SystemZ/insn-mxbr.txt
isassembler/SystemZ/insn-mxdb.txt
isassembler/SystemZ/insn-mxdbr.txt
isassembler/SystemZ/insn-n.txt
isassembler/SystemZ/insn-ng.txt
isassembler/SystemZ/insn-ngr.txt
isassembler/SystemZ/insn-ni.txt
isassembler/SystemZ/insn-nihf.txt
isassembler/SystemZ/insn-nihh.txt
isassembler/SystemZ/insn-nihl.txt
isassembler/SystemZ/insn-nilf.txt
isassembler/SystemZ/insn-nilh.txt
isassembler/SystemZ/insn-nill.txt
isassembler/SystemZ/insn-niy.txt
isassembler/SystemZ/insn-nr.txt
isassembler/SystemZ/insn-ny.txt
isassembler/SystemZ/insn-o.txt
isassembler/SystemZ/insn-og.txt
isassembler/SystemZ/insn-ogr.txt
isassembler/SystemZ/insn-oi.txt
isassembler/SystemZ/insn-oihf.txt
isassembler/SystemZ/insn-oihh.txt
isassembler/SystemZ/insn-oihl.txt
isassembler/SystemZ/insn-oilf.txt
isassembler/SystemZ/insn-oilh.txt
isassembler/SystemZ/insn-oill.txt
isassembler/SystemZ/insn-oiy.txt
isassembler/SystemZ/insn-or.txt
isassembler/SystemZ/insn-oy.txt
isassembler/SystemZ/insn-risbg.txt
isassembler/SystemZ/insn-rll.txt
isassembler/SystemZ/insn-rllg.txt
isassembler/SystemZ/insn-s.txt
isassembler/SystemZ/insn-sdb.txt
isassembler/SystemZ/insn-sdbr.txt
isassembler/SystemZ/insn-seb.txt
isassembler/SystemZ/insn-sebr.txt
isassembler/SystemZ/insn-sg.txt
isassembler/SystemZ/insn-sgf.txt
isassembler/SystemZ/insn-sgfr.txt
isassembler/SystemZ/insn-sgr.txt
isassembler/SystemZ/insn-sl.txt
isassembler/SystemZ/insn-slb.txt
isassembler/SystemZ/insn-slbg.txt
isassembler/SystemZ/insn-slbgr.txt
isassembler/SystemZ/insn-slbr.txt
isassembler/SystemZ/insn-slfi.txt
isassembler/SystemZ/insn-slg.txt
isassembler/SystemZ/insn-slgf.txt
isassembler/SystemZ/insn-slgfi.txt
isassembler/SystemZ/insn-slgfr.txt
isassembler/SystemZ/insn-slgr.txt
isassembler/SystemZ/insn-sll.txt
isassembler/SystemZ/insn-sllg.txt
isassembler/SystemZ/insn-slr.txt
isassembler/SystemZ/insn-sly.txt
isassembler/SystemZ/insn-sqdb.txt
isassembler/SystemZ/insn-sqdbr.txt
isassembler/SystemZ/insn-sqeb.txt
isassembler/SystemZ/insn-sqebr.txt
isassembler/SystemZ/insn-sqxbr.txt
isassembler/SystemZ/insn-sr.txt
isassembler/SystemZ/insn-sra.txt
isassembler/SystemZ/insn-srag.txt
isassembler/SystemZ/insn-srl.txt
isassembler/SystemZ/insn-srlg.txt
isassembler/SystemZ/insn-st.txt
isassembler/SystemZ/insn-stc.txt
isassembler/SystemZ/insn-stcy.txt
isassembler/SystemZ/insn-std.txt
isassembler/SystemZ/insn-stdy.txt
isassembler/SystemZ/insn-ste.txt
isassembler/SystemZ/insn-stey.txt
isassembler/SystemZ/insn-stg.txt
isassembler/SystemZ/insn-stgrl.txt
isassembler/SystemZ/insn-sth.txt
isassembler/SystemZ/insn-sthrl.txt
isassembler/SystemZ/insn-sthy.txt
isassembler/SystemZ/insn-stmg.txt
isassembler/SystemZ/insn-strl.txt
isassembler/SystemZ/insn-strv.txt
isassembler/SystemZ/insn-strvg.txt
isassembler/SystemZ/insn-sty.txt
isassembler/SystemZ/insn-sxbr.txt
isassembler/SystemZ/insn-sy.txt
isassembler/SystemZ/insn-x.txt
isassembler/SystemZ/insn-xg.txt
isassembler/SystemZ/insn-xgr.txt
isassembler/SystemZ/insn-xi.txt
isassembler/SystemZ/insn-xihf.txt
isassembler/SystemZ/insn-xilf.txt
isassembler/SystemZ/insn-xiy.txt
isassembler/SystemZ/insn-xr.txt
isassembler/SystemZ/insn-xy.txt
isassembler/SystemZ/invalid-regs-01.txt
isassembler/SystemZ/lit.local.cfg
isassembler/SystemZ/trunc-01.txt
isassembler/SystemZ/trunc-02.txt
isassembler/SystemZ/trunc-03.txt
isassembler/SystemZ/unmapped-01.txt
|
| 847cb575a1533777f45239a8136446e02c202763 |
14-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Add extra testscases for r181773
Forgot to svn add these...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181774 91177308-0d34-0410-b5e6-96231b3b80d8
ystemZ/insn-bras-02.s
ystemZ/insn-brasl-02.s
ystemZ/insn-cgfrl-02.s
ystemZ/insn-cghrl-02.s
ystemZ/insn-cgrl-02.s
ystemZ/insn-chrl-02.s
ystemZ/insn-clgfrl-02.s
ystemZ/insn-clghrl-02.s
ystemZ/insn-clgrl-02.s
ystemZ/insn-clhrl-02.s
ystemZ/insn-clrl-02.s
ystemZ/insn-crl-02.s
ystemZ/insn-larl-02.s
ystemZ/insn-lgfrl-02.s
ystemZ/insn-lghrl-02.s
ystemZ/insn-lgrl-02.s
ystemZ/insn-lhrl-02.s
ystemZ/insn-llgfrl-02.s
ystemZ/insn-llghrl-02.s
ystemZ/insn-llhrl-02.s
ystemZ/insn-lrl-02.s
ystemZ/insn-stgrl-02.s
ystemZ/insn-sthrl-02.s
ystemZ/insn-strl-02.s
|
| b594c4c873bd3e2ee560cc83bd50282ec56b01e9 |
14-May-2013 |
Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
[SystemZ] Rework handling of constant PC-relative operands
The GNU assembler treats things like:
brasl %r14, 100
in the same way as:
brasl %r14, .+100
rather than as a branch to absolute address 100. We implemented this in
LLVM by creating an immediate operand rather than the usual expr operand,
and by handling immediate operands specially in the code emitter.
This was undesirable for (at least) three reasons:
- the specialness of immediate operands was exposed to the backend MC code,
rather than being limited to the assembler parser.
- in disassembly, an immediate operand really is an absolute address.
(Note that this means reassembling printed disassembly can't recreate
the original code.)
- it would interfere with any assembly manipulation that we might
try in future. E.g. operations like branch shortening can change
the relative position of instructions, but any code that updates
sym+offset addresses wouldn't update an immediate "100" operand
in the same way as an explicit ".+100" operand.
This patch changes the implementation so that the assembler creates
a "." label for immediate PC-relative operands, so that the operand
to the MCInst is always the absolute address. The patch also adds
some error checking of the offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773 91177308-0d34-0410-b5e6-96231b3b80d8
ystemZ/insn-bras-01.s
ystemZ/insn-brasl-01.s
ystemZ/insn-brc-01.s
ystemZ/insn-brc-02.s
ystemZ/insn-brcl-01.s
ystemZ/insn-brcl-02.s
ystemZ/insn-cgfrl-01.s
ystemZ/insn-cghrl-01.s
ystemZ/insn-cgrl-01.s
ystemZ/insn-chrl-01.s
ystemZ/insn-clgfrl-01.s
ystemZ/insn-clghrl-01.s
ystemZ/insn-clgrl-01.s
ystemZ/insn-clhrl-01.s
ystemZ/insn-clrl-01.s
ystemZ/insn-crl-01.s
ystemZ/insn-larl-01.s
ystemZ/insn-lgfrl-01.s
ystemZ/insn-lghrl-01.s
ystemZ/insn-lgrl-01.s
ystemZ/insn-lhrl-01.s
ystemZ/insn-llgfrl-01.s
ystemZ/insn-llghrl-01.s
ystemZ/insn-llhrl-01.s
ystemZ/insn-lrl-01.s
ystemZ/insn-stgrl-01.s
ystemZ/insn-sthrl-01.s
ystemZ/insn-strl-01.s
|
| f4a1377322a9234c17b1d324c47248bdb5f62158 |
13-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Assembler macro ADDIU $rs,imm
This patch adds alias for addiu instruction which enables following syntax:
addiu $rs,imm
The macro is translated as:
addiu $rs,$rs,imm
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
|
| f86e436fb95670ed110818fefa403f21ae104639 |
13-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/basic-arm-instructions.txt
|
| ffc49cbea41c08132587a3e622bb65191fa576a2 |
10-May-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Fix a crasher when we fail on a direct match.
The issue was that the MatchingInlineAsm and VariantID args to the
MatchInstructionImpl function weren't being set properly. Specifically, when
parsing intel syntax, the parser thought it was parsing inline assembly in the
at&t dialect; that will never be the case.
The crash was caused when the emitter tried to emit the instruction, but the
operands weren't set. When parsing inline assembly we only set the opcode, not
the operands, which is used to lookup the instruction descriptor.
rdar://13854391 and PR15945
Also, this commit reverts r176036. Now that we're correctly parsing the intel
syntax the pushad/popad don't match properly. I've reimplemented that fix using
a MnemonicAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181620 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_errors.s
|
| c24a374331fc97dd215937c8f0a9bf5271f39657 |
10-May-2013 |
Logan Chien <tzuhsiang.chien@gmail.com> |
Implement AsmParser for ARM unwind directives.
This commit implements the AsmParser for fnstart, fnend,
cantunwind, personality, handlerdata, pad, setfp, save, and
vsave directives.
This commit fixes some minor issue in the ARMELFStreamer:
* The switch back to corresponding section after the .fnend
directive.
* Emit the unwind opcode while processing .fnend directive
if there is no .handlerdata directive.
* Emit the unwind opcode to .ARM.extab while processing
.handlerdata even if .personality directive does not exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181603 91177308-0d34-0410-b5e6-96231b3b80d8
RM/eh-compact-pr0.s
RM/eh-compact-pr1.s
RM/eh-directive-cantunwind-diagnostics.s
RM/eh-directive-cantunwind.s
RM/eh-directive-fnend-diagnostics.s
RM/eh-directive-fnstart-diagnostics.s
RM/eh-directive-handlerdata.s
RM/eh-directive-pad-diagnostics.s
RM/eh-directive-pad.s
RM/eh-directive-personality-diagnostics.s
RM/eh-directive-personality.s
RM/eh-directive-save-diagnoatics.s
RM/eh-directive-save.s
RM/eh-directive-section-comdat.s
RM/eh-directive-section-multiple-func.s
RM/eh-directive-section.s
RM/eh-directive-setfp-diagnostics.s
RM/eh-directive-setfp.s
RM/eh-directive-text-section-multiple-func.s
RM/eh-directive-text-section.s
RM/eh-directive-vsave-diagnostics.s
RM/eh-directive-vsave.s
|
| a70d02ff2841d535875fe80bd3d3c25ba90613da |
10-May-2013 |
Chad Rosier <mcrosier@apple.com> |
[x86AsmParser] It's valid to stop parsing an operand at an immediate.
rdar://13854369 and PR15944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181564 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 146f336272f442e8342ef9bbfa5f5937c4bb8d65 |
08-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add ELF relocation tests
This patch extends test/MC/PowerPC/ppc64-fixups.s to not only check for
the correct fixup type in the --show-encoding output, but also runs the
generated object file through llvm-readobj -r and verifies that the
correct ELF relocation records were generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181453 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 3ea16db0be90892ab25a2f211d1a292be55f386c |
08-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This patch fixes two tests marked as XFAIL among the ARM assembler tests.
The reference encoding is correct, but written in the wrong byte order (these are Thumb tests, while the reference is in ARM byte order).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181420 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-vld-encoding.s
RM/neont2-vst-encoding.s
|
| 88535dda9050377cc52dfffa20664484b0bb9f7f |
07-May-2013 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in the MC asm parser evaluating expressions. It was treating:
A = 9
B = 3 * A - 2 * A + 1 as B = 3 * A - (2 * A + 1)
rdar://13816516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181366 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 097b88fff6c091e3ce314d1b5fe89ed3e691b261 |
06-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[SystemZ] Add MC test cases
This adds all MC tests for the SystemZ target.
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181206 91177308-0d34-0410-b5e6-96231b3b80d8
ystemZ/insn-a-01.s
ystemZ/insn-a-02.s
ystemZ/insn-adb-01.s
ystemZ/insn-adb-02.s
ystemZ/insn-adbr-01.s
ystemZ/insn-aeb-01.s
ystemZ/insn-aeb-02.s
ystemZ/insn-aebr-01.s
ystemZ/insn-afi-01.s
ystemZ/insn-afi-02.s
ystemZ/insn-ag-01.s
ystemZ/insn-ag-02.s
ystemZ/insn-agf-01.s
ystemZ/insn-agf-02.s
ystemZ/insn-agfi-01.s
ystemZ/insn-agfi-02.s
ystemZ/insn-agfr-01.s
ystemZ/insn-aghi-01.s
ystemZ/insn-aghi-02.s
ystemZ/insn-agr-01.s
ystemZ/insn-agsi-01.s
ystemZ/insn-agsi-02.s
ystemZ/insn-ah-01.s
ystemZ/insn-ah-02.s
ystemZ/insn-ahi-01.s
ystemZ/insn-ahi-02.s
ystemZ/insn-ahy-01.s
ystemZ/insn-ahy-02.s
ystemZ/insn-al-01.s
ystemZ/insn-al-02.s
ystemZ/insn-alc-01.s
ystemZ/insn-alc-02.s
ystemZ/insn-alcg-01.s
ystemZ/insn-alcg-02.s
ystemZ/insn-alcgr-01.s
ystemZ/insn-alcr-01.s
ystemZ/insn-alfi-01.s
ystemZ/insn-alfi-02.s
ystemZ/insn-alg-01.s
ystemZ/insn-alg-02.s
ystemZ/insn-algf-01.s
ystemZ/insn-algf-02.s
ystemZ/insn-algfi-01.s
ystemZ/insn-algfi-02.s
ystemZ/insn-algfr-01.s
ystemZ/insn-algr-01.s
ystemZ/insn-alr-01.s
ystemZ/insn-aly-01.s
ystemZ/insn-aly-02.s
ystemZ/insn-ar-01.s
ystemZ/insn-asi-01.s
ystemZ/insn-asi-02.s
ystemZ/insn-axbr-01.s
ystemZ/insn-axbr-02.s
ystemZ/insn-ay-01.s
ystemZ/insn-ay-02.s
ystemZ/insn-basr-01.s
ystemZ/insn-br-01.s
ystemZ/insn-bras-01.s
ystemZ/insn-brasl-01.s
ystemZ/insn-brc-01.s
ystemZ/insn-brc-02.s
ystemZ/insn-brcl-01.s
ystemZ/insn-brcl-02.s
ystemZ/insn-c-01.s
ystemZ/insn-c-02.s
ystemZ/insn-cdb-01.s
ystemZ/insn-cdb-02.s
ystemZ/insn-cdbr-01.s
ystemZ/insn-cdfbr-01.s
ystemZ/insn-cdfbr-02.s
ystemZ/insn-cdgbr-01.s
ystemZ/insn-cdgbr-02.s
ystemZ/insn-ceb-01.s
ystemZ/insn-ceb-02.s
ystemZ/insn-cebr-01.s
ystemZ/insn-cefbr-01.s
ystemZ/insn-cefbr-02.s
ystemZ/insn-cegbr-01.s
ystemZ/insn-cegbr-02.s
ystemZ/insn-cfdbr-01.s
ystemZ/insn-cfdbr-02.s
ystemZ/insn-cfebr-01.s
ystemZ/insn-cfebr-02.s
ystemZ/insn-cfi-01.s
ystemZ/insn-cfi-02.s
ystemZ/insn-cfxbr-01.s
ystemZ/insn-cfxbr-02.s
ystemZ/insn-cg-01.s
ystemZ/insn-cg-02.s
ystemZ/insn-cgdbr-01.s
ystemZ/insn-cgdbr-02.s
ystemZ/insn-cgebr-01.s
ystemZ/insn-cgebr-02.s
ystemZ/insn-cgf-01.s
ystemZ/insn-cgf-02.s
ystemZ/insn-cgfi-01.s
ystemZ/insn-cgfi-02.s
ystemZ/insn-cgfr-01.s
ystemZ/insn-cgfrl-01.s
ystemZ/insn-cgh-01.s
ystemZ/insn-cgh-02.s
ystemZ/insn-cghi-01.s
ystemZ/insn-cghi-02.s
ystemZ/insn-cghrl-01.s
ystemZ/insn-cghsi-01.s
ystemZ/insn-cghsi-02.s
ystemZ/insn-cgr-01.s
ystemZ/insn-cgrl-01.s
ystemZ/insn-cgxbr-01.s
ystemZ/insn-cgxbr-02.s
ystemZ/insn-ch-01.s
ystemZ/insn-ch-02.s
ystemZ/insn-chhsi-01.s
ystemZ/insn-chhsi-02.s
ystemZ/insn-chi-01.s
ystemZ/insn-chi-02.s
ystemZ/insn-chrl-01.s
ystemZ/insn-chsi-01.s
ystemZ/insn-chsi-02.s
ystemZ/insn-chy-01.s
ystemZ/insn-chy-02.s
ystemZ/insn-cl-01.s
ystemZ/insn-cl-02.s
ystemZ/insn-clfhsi-01.s
ystemZ/insn-clfhsi-02.s
ystemZ/insn-clfi-01.s
ystemZ/insn-clfi-02.s
ystemZ/insn-clg-01.s
ystemZ/insn-clg-02.s
ystemZ/insn-clgf-01.s
ystemZ/insn-clgf-02.s
ystemZ/insn-clgfi-01.s
ystemZ/insn-clgfi-02.s
ystemZ/insn-clgfr-01.s
ystemZ/insn-clgfrl-01.s
ystemZ/insn-clghrl-01.s
ystemZ/insn-clghsi-01.s
ystemZ/insn-clghsi-02.s
ystemZ/insn-clgr-01.s
ystemZ/insn-clgrl-01.s
ystemZ/insn-clhhsi-01.s
ystemZ/insn-clhhsi-02.s
ystemZ/insn-clhrl-01.s
ystemZ/insn-cli-01.s
ystemZ/insn-cli-02.s
ystemZ/insn-cliy-01.s
ystemZ/insn-cliy-02.s
ystemZ/insn-clr-01.s
ystemZ/insn-clrl-01.s
ystemZ/insn-cly-01.s
ystemZ/insn-cly-02.s
ystemZ/insn-cpsdr-01.s
ystemZ/insn-cr-01.s
ystemZ/insn-crl-01.s
ystemZ/insn-cs-01.s
ystemZ/insn-cs-02.s
ystemZ/insn-csg-01.s
ystemZ/insn-csg-02.s
ystemZ/insn-csy-01.s
ystemZ/insn-csy-02.s
ystemZ/insn-cxbr-01.s
ystemZ/insn-cxbr-02.s
ystemZ/insn-cxfbr-01.s
ystemZ/insn-cxfbr-02.s
ystemZ/insn-cxgbr-01.s
ystemZ/insn-cxgbr-02.s
ystemZ/insn-cy-01.s
ystemZ/insn-cy-02.s
ystemZ/insn-ddb-01.s
ystemZ/insn-ddb-02.s
ystemZ/insn-ddbr-01.s
ystemZ/insn-deb-01.s
ystemZ/insn-deb-02.s
ystemZ/insn-debr-01.s
ystemZ/insn-dl-01.s
ystemZ/insn-dl-02.s
ystemZ/insn-dlg-01.s
ystemZ/insn-dlg-02.s
ystemZ/insn-dlgr-01.s
ystemZ/insn-dlgr-02.s
ystemZ/insn-dlr-01.s
ystemZ/insn-dlr-02.s
ystemZ/insn-dsg-01.s
ystemZ/insn-dsg-02.s
ystemZ/insn-dsgf-01.s
ystemZ/insn-dsgf-02.s
ystemZ/insn-dsgfr-01.s
ystemZ/insn-dsgfr-02.s
ystemZ/insn-dsgr-01.s
ystemZ/insn-dsgr-02.s
ystemZ/insn-dxbr-01.s
ystemZ/insn-dxbr-02.s
ystemZ/insn-ear-01.s
ystemZ/insn-ear-02.s
ystemZ/insn-fidbr-01.s
ystemZ/insn-fidbr-02.s
ystemZ/insn-fiebr-01.s
ystemZ/insn-fiebr-02.s
ystemZ/insn-fixbr-01.s
ystemZ/insn-fixbr-02.s
ystemZ/insn-flogr-01.s
ystemZ/insn-flogr-02.s
ystemZ/insn-ic-01.s
ystemZ/insn-ic-02.s
ystemZ/insn-icy-01.s
ystemZ/insn-icy-02.s
ystemZ/insn-iihf-01.s
ystemZ/insn-iihf-02.s
ystemZ/insn-iihh-01.s
ystemZ/insn-iihh-02.s
ystemZ/insn-iihl-01.s
ystemZ/insn-iihl-02.s
ystemZ/insn-iilf-01.s
ystemZ/insn-iilf-02.s
ystemZ/insn-iilh-01.s
ystemZ/insn-iilh-02.s
ystemZ/insn-iill-01.s
ystemZ/insn-iill-02.s
ystemZ/insn-l-01.s
ystemZ/insn-l-02.s
ystemZ/insn-la-01.s
ystemZ/insn-la-02.s
ystemZ/insn-larl-01.s
ystemZ/insn-lay-01.s
ystemZ/insn-lay-02.s
ystemZ/insn-lb-01.s
ystemZ/insn-lb-02.s
ystemZ/insn-lbr-01.s
ystemZ/insn-lcdbr-01.s
ystemZ/insn-lcebr-01.s
ystemZ/insn-lcgfr-01.s
ystemZ/insn-lcgr-01.s
ystemZ/insn-lcr-01.s
ystemZ/insn-lcxbr-01.s
ystemZ/insn-lcxbr-02.s
ystemZ/insn-ld-01.s
ystemZ/insn-ld-02.s
ystemZ/insn-ldeb-01.s
ystemZ/insn-ldeb-02.s
ystemZ/insn-ldebr-01.s
ystemZ/insn-ldgr-01.s
ystemZ/insn-ldgr-02.s
ystemZ/insn-ldr-01.s
ystemZ/insn-ldxbr-01.s
ystemZ/insn-ldxbr-02.s
ystemZ/insn-ldy-01.s
ystemZ/insn-ldy-02.s
ystemZ/insn-le-01.s
ystemZ/insn-le-02.s
ystemZ/insn-ledbr-01.s
ystemZ/insn-ler-01.s
ystemZ/insn-lexbr-01.s
ystemZ/insn-lexbr-02.s
ystemZ/insn-ley-01.s
ystemZ/insn-ley-02.s
ystemZ/insn-lg-01.s
ystemZ/insn-lg-02.s
ystemZ/insn-lgb-01.s
ystemZ/insn-lgb-02.s
ystemZ/insn-lgbr-01.s
ystemZ/insn-lgdr-01.s
ystemZ/insn-lgdr-02.s
ystemZ/insn-lgf-01.s
ystemZ/insn-lgf-02.s
ystemZ/insn-lgfi-01.s
ystemZ/insn-lgfi-02.s
ystemZ/insn-lgfr-01.s
ystemZ/insn-lgfrl-01.s
ystemZ/insn-lgh-01.s
ystemZ/insn-lgh-02.s
ystemZ/insn-lghi-01.s
ystemZ/insn-lghi-02.s
ystemZ/insn-lghr-01.s
ystemZ/insn-lghrl-01.s
ystemZ/insn-lgr-01.s
ystemZ/insn-lgrl-01.s
ystemZ/insn-lh-01.s
ystemZ/insn-lh-02.s
ystemZ/insn-lhi-01.s
ystemZ/insn-lhi-02.s
ystemZ/insn-lhr-01.s
ystemZ/insn-lhrl-01.s
ystemZ/insn-lhy-01.s
ystemZ/insn-lhy-02.s
ystemZ/insn-llc-01.s
ystemZ/insn-llc-02.s
ystemZ/insn-llcr-01.s
ystemZ/insn-llgc-01.s
ystemZ/insn-llgc-02.s
ystemZ/insn-llgcr-01.s
ystemZ/insn-llgf-01.s
ystemZ/insn-llgf-02.s
ystemZ/insn-llgfr-01.s
ystemZ/insn-llgfrl-01.s
ystemZ/insn-llgh-01.s
ystemZ/insn-llgh-02.s
ystemZ/insn-llghr-01.s
ystemZ/insn-llghrl-01.s
ystemZ/insn-llh-01.s
ystemZ/insn-llh-02.s
ystemZ/insn-llhr-01.s
ystemZ/insn-llhrl-01.s
ystemZ/insn-llihf-01.s
ystemZ/insn-llihf-02.s
ystemZ/insn-llihh-01.s
ystemZ/insn-llihh-02.s
ystemZ/insn-llihl-01.s
ystemZ/insn-llihl-02.s
ystemZ/insn-llilf-01.s
ystemZ/insn-llilf-02.s
ystemZ/insn-llilh-01.s
ystemZ/insn-llilh-02.s
ystemZ/insn-llill-01.s
ystemZ/insn-llill-02.s
ystemZ/insn-lmg-01.s
ystemZ/insn-lmg-02.s
ystemZ/insn-lndbr-01.s
ystemZ/insn-lnebr-01.s
ystemZ/insn-lnxbr-01.s
ystemZ/insn-lnxbr-02.s
ystemZ/insn-lpdbr-01.s
ystemZ/insn-lpebr-01.s
ystemZ/insn-lpxbr-01.s
ystemZ/insn-lpxbr-02.s
ystemZ/insn-lr-01.s
ystemZ/insn-lrl-01.s
ystemZ/insn-lrv-01.s
ystemZ/insn-lrv-02.s
ystemZ/insn-lrvg-01.s
ystemZ/insn-lrvg-02.s
ystemZ/insn-lrvgr-01.s
ystemZ/insn-lrvr-01.s
ystemZ/insn-lxr-01.s
ystemZ/insn-lxr-02.s
ystemZ/insn-ly-01.s
ystemZ/insn-ly-02.s
ystemZ/insn-lzdr-01.s
ystemZ/insn-lzer-01.s
ystemZ/insn-lzxr-01.s
ystemZ/insn-lzxr-02.s
ystemZ/insn-madb-01.s
ystemZ/insn-madb-02.s
ystemZ/insn-madbr-01.s
ystemZ/insn-maeb-01.s
ystemZ/insn-maeb-02.s
ystemZ/insn-maebr-01.s
ystemZ/insn-mdb-01.s
ystemZ/insn-mdb-02.s
ystemZ/insn-mdbr-01.s
ystemZ/insn-mdeb-01.s
ystemZ/insn-mdeb-02.s
ystemZ/insn-mdebr-01.s
ystemZ/insn-meeb-01.s
ystemZ/insn-meeb-02.s
ystemZ/insn-meebr-01.s
ystemZ/insn-mghi-01.s
ystemZ/insn-mghi-02.s
ystemZ/insn-mh-01.s
ystemZ/insn-mh-02.s
ystemZ/insn-mhi-01.s
ystemZ/insn-mhi-02.s
ystemZ/insn-mhy-01.s
ystemZ/insn-mhy-02.s
ystemZ/insn-mlg-01.s
ystemZ/insn-mlg-02.s
ystemZ/insn-mlgr-01.s
ystemZ/insn-mlgr-02.s
ystemZ/insn-ms-01.s
ystemZ/insn-ms-02.s
ystemZ/insn-msdb-01.s
ystemZ/insn-msdb-02.s
ystemZ/insn-msdbr-01.s
ystemZ/insn-mseb-01.s
ystemZ/insn-mseb-02.s
ystemZ/insn-msebr-01.s
ystemZ/insn-msfi-01.s
ystemZ/insn-msfi-02.s
ystemZ/insn-msg-01.s
ystemZ/insn-msg-02.s
ystemZ/insn-msgf-01.s
ystemZ/insn-msgf-02.s
ystemZ/insn-msgfi-01.s
ystemZ/insn-msgfi-02.s
ystemZ/insn-msgfr-01.s
ystemZ/insn-msgr-01.s
ystemZ/insn-msr-01.s
ystemZ/insn-msy-01.s
ystemZ/insn-msy-02.s
ystemZ/insn-mvghi-01.s
ystemZ/insn-mvghi-02.s
ystemZ/insn-mvhhi-01.s
ystemZ/insn-mvhhi-02.s
ystemZ/insn-mvhi-01.s
ystemZ/insn-mvhi-02.s
ystemZ/insn-mvi-01.s
ystemZ/insn-mvi-02.s
ystemZ/insn-mviy-01.s
ystemZ/insn-mviy-02.s
ystemZ/insn-mxbr-01.s
ystemZ/insn-mxbr-02.s
ystemZ/insn-mxdb-01.s
ystemZ/insn-mxdb-02.s
ystemZ/insn-mxdbr-01.s
ystemZ/insn-mxdbr-02.s
ystemZ/insn-n-01.s
ystemZ/insn-n-02.s
ystemZ/insn-ng-01.s
ystemZ/insn-ng-02.s
ystemZ/insn-ngr-01.s
ystemZ/insn-ni-01.s
ystemZ/insn-ni-02.s
ystemZ/insn-nihf-01.s
ystemZ/insn-nihf-02.s
ystemZ/insn-nihh-01.s
ystemZ/insn-nihh-02.s
ystemZ/insn-nihl-01.s
ystemZ/insn-nihl-02.s
ystemZ/insn-nilf-01.s
ystemZ/insn-nilf-02.s
ystemZ/insn-nilh-01.s
ystemZ/insn-nilh-02.s
ystemZ/insn-nill-01.s
ystemZ/insn-nill-02.s
ystemZ/insn-niy-01.s
ystemZ/insn-niy-02.s
ystemZ/insn-nr-01.s
ystemZ/insn-ny-01.s
ystemZ/insn-ny-02.s
ystemZ/insn-o-01.s
ystemZ/insn-o-02.s
ystemZ/insn-og-01.s
ystemZ/insn-og-02.s
ystemZ/insn-ogr-01.s
ystemZ/insn-oi-01.s
ystemZ/insn-oi-02.s
ystemZ/insn-oihf-01.s
ystemZ/insn-oihf-02.s
ystemZ/insn-oihh-01.s
ystemZ/insn-oihh-02.s
ystemZ/insn-oihl-01.s
ystemZ/insn-oihl-02.s
ystemZ/insn-oilf-01.s
ystemZ/insn-oilf-02.s
ystemZ/insn-oilh-01.s
ystemZ/insn-oilh-02.s
ystemZ/insn-oill-01.s
ystemZ/insn-oill-02.s
ystemZ/insn-oiy-01.s
ystemZ/insn-oiy-02.s
ystemZ/insn-or-01.s
ystemZ/insn-oy-01.s
ystemZ/insn-oy-02.s
ystemZ/insn-risbg-01.s
ystemZ/insn-risbg-02.s
ystemZ/insn-rll-01.s
ystemZ/insn-rll-02.s
ystemZ/insn-rllg-01.s
ystemZ/insn-rllg-02.s
ystemZ/insn-s-01.s
ystemZ/insn-s-02.s
ystemZ/insn-sdb-01.s
ystemZ/insn-sdb-02.s
ystemZ/insn-sdbr-01.s
ystemZ/insn-seb-01.s
ystemZ/insn-seb-02.s
ystemZ/insn-sebr-01.s
ystemZ/insn-sg-01.s
ystemZ/insn-sg-02.s
ystemZ/insn-sgf-01.s
ystemZ/insn-sgf-02.s
ystemZ/insn-sgfr-01.s
ystemZ/insn-sgr-01.s
ystemZ/insn-sl-01.s
ystemZ/insn-sl-02.s
ystemZ/insn-slb-01.s
ystemZ/insn-slb-02.s
ystemZ/insn-slbg-01.s
ystemZ/insn-slbg-02.s
ystemZ/insn-slbgr-01.s
ystemZ/insn-slbr-01.s
ystemZ/insn-slfi-01.s
ystemZ/insn-slfi-02.s
ystemZ/insn-slg-01.s
ystemZ/insn-slg-02.s
ystemZ/insn-slgf-01.s
ystemZ/insn-slgf-02.s
ystemZ/insn-slgfi-01.s
ystemZ/insn-slgfi-02.s
ystemZ/insn-slgfr-01.s
ystemZ/insn-slgr-01.s
ystemZ/insn-sll-01.s
ystemZ/insn-sll-02.s
ystemZ/insn-sllg-01.s
ystemZ/insn-sllg-02.s
ystemZ/insn-slr-01.s
ystemZ/insn-sly-01.s
ystemZ/insn-sly-02.s
ystemZ/insn-sqdb-01.s
ystemZ/insn-sqdb-02.s
ystemZ/insn-sqdbr-01.s
ystemZ/insn-sqeb-01.s
ystemZ/insn-sqeb-02.s
ystemZ/insn-sqebr-01.s
ystemZ/insn-sqxbr-01.s
ystemZ/insn-sqxbr-02.s
ystemZ/insn-sr-01.s
ystemZ/insn-sra-01.s
ystemZ/insn-sra-02.s
ystemZ/insn-srag-01.s
ystemZ/insn-srag-02.s
ystemZ/insn-srl-01.s
ystemZ/insn-srl-02.s
ystemZ/insn-srlg-01.s
ystemZ/insn-srlg-02.s
ystemZ/insn-st-01.s
ystemZ/insn-st-02.s
ystemZ/insn-stc-01.s
ystemZ/insn-stc-02.s
ystemZ/insn-stcy-01.s
ystemZ/insn-stcy-02.s
ystemZ/insn-std-01.s
ystemZ/insn-std-02.s
ystemZ/insn-stdy-01.s
ystemZ/insn-stdy-02.s
ystemZ/insn-ste-01.s
ystemZ/insn-ste-02.s
ystemZ/insn-stey-01.s
ystemZ/insn-stey-02.s
ystemZ/insn-stg-01.s
ystemZ/insn-stg-02.s
ystemZ/insn-stgrl-01.s
ystemZ/insn-sth-01.s
ystemZ/insn-sth-02.s
ystemZ/insn-sthrl-01.s
ystemZ/insn-sthy-01.s
ystemZ/insn-sthy-02.s
ystemZ/insn-stmg-01.s
ystemZ/insn-stmg-02.s
ystemZ/insn-strl-01.s
ystemZ/insn-strv-01.s
ystemZ/insn-strv-02.s
ystemZ/insn-strvg-01.s
ystemZ/insn-strvg-02.s
ystemZ/insn-sty-01.s
ystemZ/insn-sty-02.s
ystemZ/insn-sxbr-01.s
ystemZ/insn-sxbr-02.s
ystemZ/insn-sy-01.s
ystemZ/insn-sy-02.s
ystemZ/insn-x-01.s
ystemZ/insn-x-02.s
ystemZ/insn-xg-01.s
ystemZ/insn-xg-02.s
ystemZ/insn-xgr-01.s
ystemZ/insn-xi-01.s
ystemZ/insn-xi-02.s
ystemZ/insn-xihf-01.s
ystemZ/insn-xihf-02.s
ystemZ/insn-xilf-01.s
ystemZ/insn-xilf-02.s
ystemZ/insn-xiy-01.s
ystemZ/insn-xiy-02.s
ystemZ/insn-xr-01.s
ystemZ/insn-xy-01.s
ystemZ/insn-xy-02.s
ystemZ/lit.local.cfg
ystemZ/regs-01.s
ystemZ/regs-02.s
ystemZ/regs-03.s
ystemZ/regs-04.s
ystemZ/regs-05.s
ystemZ/regs-06.s
ystemZ/regs-07.s
ystemZ/regs-08.s
ystemZ/regs-09.s
ystemZ/regs-10.s
ystemZ/regs-11.s
ystemZ/regs-12.s
ystemZ/regs-13.s
ystemZ/regs-14.s
ystemZ/regs-15.s
|
| 589ddc9887406ddfd5a2661b567057faad7a22cc |
05-May-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add LDAPB instructions.
With the change the disassembler now supports the XCore ISA in its
entirety.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| c601bd69d5c7fcd3bf9946e8a8a1bd1f9ab6642b |
05-May-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add BLRB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| a7e5e6b959bfd2b7982e116a4fd6955b35534b4c |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Parse platform-specifc variant kinds in AsmParser
This patch adds support for PowerPC platform-specific variant
kinds in MCSymbolRefExpr::getVariantKindForName, and also
adds a test case to verify they are translated to the appropriate
fixup type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181053 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-fixups.s
|
| 8e4ba8f7b19615907e5874b3aa661d52c21fff74 |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add some Book II instructions to AsmParser
This patch adds a couple of Book II instructions (isync, icbi) to the
PowerPC assembler parser. These are needed when bootstrapping clang
with the integrated assembler forced on, because they are used in
inline asm statements in the code base.
The test case adds the full list of Book II storage control instructions,
including associated extended mnemonics. Again, those that are not yet
supported as marked as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-bookII.s
|
| 16adfdb2e666f46e058b603a8a7aa75758819fd5 |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support extended mnemonics in AsmParser
This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser. It adds support specifically for those
extended mnemonics that LLVM will itself generate.
The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-ext.s
|
| 5e220753ff81ac5cbee874e7c00c76c7fbe0d20a |
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.
The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux. The supported syntax is
intended to be compatible with the GNU assembler.
The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.
Instruction operands will be checked for validity and errors
generated. (Error handling in general could still be improved.)
The patch adds a number of test cases to verify instruction
and operand encodings. The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector.
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.
A number of follow-on check-ins will add extra features. When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-encoding-fp.s
owerPC/ppc64-encoding-vmx.s
owerPC/ppc64-encoding.s
owerPC/ppc64-errors.s
owerPC/ppc64-operands.s
|
| b8b1d35743a51cd5d451607d28a5efa609ff5c52 |
30-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Test for r179873.
Patch by Zoran Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180804 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-alu-instructions.s
|
| 62d77858be88ca011b55f5b350152bf04d1ca7db |
30-Apr-2013 |
Mihai Popa <mihail.popa@gmail.com> |
s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDR_POST-arm.txt
|
| 1ad3a410beff11913db0573942fb51b651d01a13 |
26-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.
Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.
This commit adds a proper diagnostic message for Imm0_4 and updates all tests.
Patch by Mihail Popa <Mihail.Popa@arm.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
RM/invalid-hint-arm.s
RM/invalid-hint-thumb.s
isassembler/ARM/invalid-hint-arm.txt
isassembler/ARM/invalid-hint-thumb.txt
|
| 97265a48895a2cda7f04e47bfe935c4fdd71f8ae |
26-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: .set reorder support
Mips have delayslots for certain instructions
like jumps and branches. These are instructions
that follow the branch or jump and are executed
before the jump or branch is completed.
Early Mips compilers could not cope with delayslots
and left them up to the assembler. The assembler would
fill the delayslots with the appropriate instruction,
usually just a nop to allow correct runtime behavior.
The default behavior for this is set with .set reorder.
To tell the assembler that you don't want it to mess with
the delayslot one used .set noreorder.
For backwards compatibility we need to support
.set reorder and have it be the default behavior in the
assembler.
Our support for it is to insert a NOP directly after an
instruction with a delayslot when in .set reorder mode.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 4b5581530393e647d559360f8c6f229c05aca94f |
25-Apr-2013 |
Reid Kleckner <reid@kleckner.net> |
[mc-coff] Forward Linker Option flags into the .drectve section
Summary:
This is modelled on the Mach-O linker options implementation and should
support a Clang implementation of #pragma comment(lib/linker).
Reviewers: rafael
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180569 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/linker-options.ll
|
| 93d0b06e2adca2d9f3d4ec544f352cc4e5e9618a |
25-Apr-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix section relocation for SECTIONREL32 with immediate offset.
Patch by Kai Nacke. This matches the gnu as output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180568 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/secrel-variant.s
|
| 24b56e94f68e58605450c4cea8f8644b722a4bae |
25-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Test case for r180241.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180246 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-loadstore-instructions.s
|
| 4cc3d1b910a60337f3dc9bc640ea18e2ed7090d4 |
25-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Test case for r180238.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180245 91177308-0d34-0410-b5e6-96231b3b80d8
ips/micromips-shift-instructions.s
|
| a2b9d3d8ba0e886971f953040a72e2b8e624f4dd |
24-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add 64 bit testing for JAL
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-jump-instructions.s
|
| f74d82d8e49ec54953c106a89e0a5951466d4e6b |
23-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
Add test case for PR15779, which has previously been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180058 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 4974b972e7dd94fad74ada4df32a12aba09c4de0 |
22-Apr-2013 |
Peter Collingbourne <peter@pcc.me.uk> |
COFF: Fix weak external aliases.
Differential Revision: http://llvm-reviews.chandlerc.com/D700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180034 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/weak.s
|
| 8d99ec574849ca8266e6491ceafee6c6029692b3 |
19-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change
operand type to uimm16.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips64-alu-instructions.s
|
| d3af696c08923d4d376641b52c3b2cb5baa00487 |
19-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Permit "sp" in ARM variant of STREXD instructions
Patch from Mihail Popa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/basic-arm-instructions.txt
|
| 4521019c6fd23680c583abe086067fc1c569bad1 |
19-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/basic-arm-instructions.txt
|
| 3f1f9c37986953250cbda7a7bfb7123571449be7 |
19-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and
AT&T dialect. Test case for r179804 as well.
rdar://13674398 and PR13340.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 26aef5b7d64e2dd2ed49123baf1e1075b648824f |
18-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] DSP-ASE move from HI/LO register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips-dsp.txt
|
| df39be6cb4eb44011db3d3e86f8fe463f81ce127 |
17-Apr-2013 |
Peter Collingbourne <peter@pcc.me.uk> |
Add support for subsections to the ELF assembler. Fixes PR8717.
Differential Revision: http://llvm-reviews.chandlerc.com/D598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179725 91177308-0d34-0410-b5e6-96231b3b80d8
LF/subsection.s
|
| d58f773b96fdb5539d9da2192b8cf2ff6112239f |
17-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for the minus unary operator. Previously, we were
unable to handle cases such as __asm mov eax, 8*-8.
This patch also attempts to simplify the state machine. Further, the error
reporting has been improved. Test cases included, but more will be added to
the clang side shortly.
rdar://13668445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179719 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 7c4cf030a898b5b4e0d2c66adf8dc068b1f1f070 |
17-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
Fix treatment of ARM unallocated hint instructions.
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)
Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179707 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 8afc8b7e63d5ce2d027e92934d16b19e5ba2db59 |
17-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Enable handling of nested expressions
This patch allows the Mips assembler to parse and emit nested
expressions as instruction operands. It also extends the
expansion of memory instructions when an offset is given as
an expression.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179657 91177308-0d34-0410-b5e6-96231b3b80d8
ips/expr1.s
|
| d0132ba7225883b2f7b828561d46fa6e203db6bb |
16-Apr-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add VACLT and VACLE assembly aliases.
These are aliases for VACGT and VACGE, respectively, with the source
operands reversed.
rdar://13638090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.s
|
| b8145e3881872fffbac15693c94536446f060330 |
16-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Explicit floating point condition register recognition.
This patch allows the assembler to recognize $fcc0
as a valid register for conditional move instructions.
Corresponding test cases have been added.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| ef1762b6a1d3353790bdb415788e7d8963e70372 |
14-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
isassembler/XCore/xcore.txt
ips/mips-alu-instructions.s
ips/mips-expansions.s
ips/mips-fpu-instructions.s
ips/mips-jump-instructions.s
ips/mips-memory-instructions.s
ips/mips-relocations.s
ips/mips64-alu-instructions.s
ips/nabi-regs.s
ips/set-at-directive.s
|
| d64ee4455a9d2fcec7e001c7f4c02d490bed5158 |
12-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Correct printing of pre-indexed operands.
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.
This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/arm-tests.txt
|
| b6ad2bd51195f7675db0f71c5826a12a2b7090fc |
12-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: use full triple for ELF tests
These tests rely specifically on the names of ELF relocations, let alone any
other detail. There's no way they'd work if LLVM was emitting something else by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179376 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/elf-globaladdress.ll
Arch64/elf-objdump.s
Arch64/elf-reloc-addsubimm.s
Arch64/elf-reloc-condbr.s
Arch64/elf-reloc-ldrlit.s
Arch64/elf-reloc-ldstunsimm.s
Arch64/elf-reloc-movw.s
Arch64/elf-reloc-pcreladdressing.s
Arch64/elf-reloc-tstb.s
Arch64/elf-reloc-uncondbrimm.s
Arch64/tls-relocs.s
|
| 15e883787f38b7c424e9de4ec8485ad9e32603b0 |
12-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: remove over-zealous use of CHECK-NEXT
It turns out some platforms (e.g. Windows) lay out their llvm-mc slightly
differently with extra newlines; there was no real reason for the test lines to
be consecutive, so this relaxes the FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179375 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/tls-relocs.s
|
| f89da7210b09a0a0f7c9ee216cd54dca03c6b64a |
12-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Replace coff-/elf-dump with llvm-readobj
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/elf-globaladdress.ll
Arch64/elf-reloc-addsubimm.s
Arch64/elf-reloc-condbr.s
Arch64/elf-reloc-ldrlit.s
Arch64/elf-reloc-ldstunsimm.s
Arch64/elf-reloc-movw.s
Arch64/elf-reloc-pcreladdressing.s
Arch64/elf-reloc-tstb.s
Arch64/elf-reloc-uncondbrimm.s
Arch64/tls-relocs.s
RM/cxx-global-constructor.ll
RM/data-in-code.ll
RM/elf-eflags-eabi-cg.ll
RM/elf-eflags-eabi.s
RM/elf-movt.s
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-reloc-condcall.s
RM/elf-thumbfunc-reloc.ll
RM/elf-thumbfunc-reloc.s
RM/elf-thumbfunc.s
RM/xscale-attributes.ll
smParser/section.s
smParser/section_names.s
OFF/align-nops.s
OFF/basic-coff-64.s
OFF/basic-coff.s
OFF/bss.s
OFF/diff.s
OFF/module-asm.ll
OFF/secrel32.s
OFF/seh-section.s
OFF/seh.s
OFF/simple-fixups.s
OFF/symbol-alias.s
OFF/symbol-fragment-offset-64.s
OFF/symbol-fragment-offset.s
OFF/weak-symbol-section-specification.ll
OFF/weak.s
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/align-bss.s
LF/align-nops.s
LF/align-size.s
LF/align-text.s
LF/align.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/call-abs.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-escape.s
LF/cfi-offset.s
LF/cfi-register.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-restore.s
LF/cfi-same-value.s
LF/cfi-sections.s
LF/cfi-signal-frame.s
LF/cfi-undefined.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/comdat.s
LF/common.s
LF/common2.s
LF/debug-line.s
LF/debug-loc.s
LF/diff.s
LF/empty-dwarf-lines.s
LF/empty.s
LF/entsize.ll
LF/entsize.s
LF/file.s
LF/gen-dwarf.s
LF/global-offset.s
LF/got.s
LF/ident.s
LF/lcomm.s
LF/leb128.s
LF/local-reloc.s
LF/merge.s
LF/n_bytes.s
LF/noexec.s
LF/norelocation.s
LF/org.s
LF/pic-diff.s
LF/plt.s
LF/pr9292.s
LF/relax-arith.s
LF/relax.s
LF/relocation-386.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/section.s
LF/set.s
LF/sleb.s
LF/symref.s
LF/tls-i386.s
LF/tls.s
LF/type.s
LF/uleb.s
LF/undef.s
LF/undef2.s
LF/version.s
LF/weak-relocation.s
LF/weak.s
LF/weakref-plt.s
LF/weakref-reloc.s
LF/weakref.s
LF/x86_64-reloc-sizetest.s
LF/zero.s
ips/elf-N64.ll
ips/elf-bigendian.ll
ips/elf-gprel-32-64.ll
ips/elf-reginfo.ll
ips/elf-relsym.ll
ips/elf-tls.ll
ips/elf_basic.s
ips/elf_eflags.ll
ips/elf_st_other.ll
ips/higher_highest.ll
ips/r-mips-got-disp.ll
ips/sym-offset.ll
ips/xgot.ll
owerPC/ppc64-initial-cfa.ll
owerPC/ppc64-relocs-01.ll
owerPC/ppc64-tls-relocs-01.ll
|
| 02d2e612521954b5ff7c1ba6fd53e36bc51e1c48 |
11-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
86/x86-64.s
|
| 18d49acdab79d6f0966b47182b6c3a2ba3d9f80f |
11-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
MC: Support COFF image-relative MCSymbolRefs
Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and
IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are
similar to normal 4-byte relocations except that they do not include
the base address of the image.
Image-relative relocations are used for debug information (32-bit) and
SEH unwind tables (64-bit).
A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to
specify such relocations. For AT&T assembly, this variant can be accessed
using the symbol suffix '@imgrel'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/relocation-imgrel.s
|
| c92cc5d9184c6a5f043dc22e186ff76eb0e18775 |
10-Apr-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
isassembler/X86/x86-64.txt
|
| 01a7b5c43e113513a3165a60e85372f89f7eaaff |
10-Apr-2013 |
Peter Collingbourne <peter@pcc.me.uk> |
Use a scheme closer to that of GNU as when deciding the type of a
symbol with multiple .type declarations.
Differential Revision: http://llvm-reviews.chandlerc.com/D607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179184 91177308-0d34-0410-b5e6-96231b3b80d8
LF/type.s
|
| 8c9e52a9fc1f99cf80c499ef10e6c8a54ef899d4 |
10-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-thumb-trustzone.s
RM/arm-trustzone.s
RM/basic-arm-instructions.s
isassembler/ARM/arm-thumb-trustzone.txt
isassembler/ARM/arm-trustzone.txt
isassembler/ARM/basic-arm-instructions.txt
|
| e112453fc39b97147ea3f23bf0b1973cd9f739b1 |
05-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for numeric displacement expressions in bracketed
memory operands.
Essentially, this layers an infix calculator on top of the parsing state
machine. The scale on the index register is still expected to be an immediate
__asm mov eax, [eax + ebx*4]
and will not work with more complex expressions. For example,
__asm mov eax, [eax + ebx*(2*2)]
The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement. Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| e50faa754b946d5240c1d4e84e64b7e84d4e27b1 |
04-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add bru instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| c6ff29713d69b4a41c225cbde9c82e4a350dbfac |
04-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] The RRegs register class is a superset of GRRegs.
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| d787a41b118a3724d1df87dc3d38cc3fddb3a145 |
03-Apr-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement the "mips endian" for r_info.
Normally r_info is just a 32 of 64 bit number matching the endian of the rest
of the file. Unfortunately, mips 64 bit little endian is special: The top 32
bits are a little endian number and the following 32 are a big endian one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178694 91177308-0d34-0410-b5e6-96231b3b80d8
ips/eh-frame.s
|
| 6107bbbbdf1c801b80f28a4d20e2194087f13c62 |
03-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Check disassembly of the st8 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| ef6343347a9269f17c1c723d6afaa28a5e5a5714 |
03-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Update disassembler test to improve coverage of the instructions.
Previously some instructions were unintentionally covered twice and
others were not covered at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 76e70f340c09ba759ad96d8dfe416b64f24bc287 |
03-Apr-2013 |
Eric Christopher <echristo@gmail.com> |
Implements low-level object file format specific output for COFF and
ELF with support for:
- File headers
- Section headers + data
- Relocations
- Symbols
- Unwind data (only COFF/Win64)
The output format follows a few rules:
- Values are almost always output one per line (as elf-dump/coff-dump already do). - Many values are translated to something readable (like enum names), with the raw value in parentheses.
- Hex numbers are output in uppercase, prefixed with "0x".
- Flags are sorted alphabetically.
- Lists and groups are always delimited.
Example output:
---------- snip ----------
Sections [
Section {
Index: 1
Name: .text (5)
Type: SHT_PROGBITS (0x1)
Flags [ (0x6)
SHF_ALLOC (0x2)
SHF_EXECINSTR (0x4)
]
Address: 0x0
Offset: 0x40
Size: 33
Link: 0
Info: 0
AddressAlignment: 16
EntrySize: 0
Relocations [
0x6 R_386_32 .rodata.str1.1 0x0
0xB R_386_PC32 puts 0x0
0x12 R_386_32 .rodata.str1.1 0x0
0x17 R_386_PC32 puts 0x0
]
SectionData (
0000: 83EC04C7 04240000 0000E8FC FFFFFFC7 |.....$..........|
0010: 04240600 0000E8FC FFFFFF31 C083C404 |.$.........1....|
0020: C3 |.|
)
}
]
---------- snip ----------
Relocations and symbols can be output standalone or together with the section header as displayed in the example.
This feature set supports all tests in test/MC/COFF and test/MC/ELF (and I suspect all additional tests using elf-dump), making elf-dump and coff-dump deprecated.
Patch by Nico Rieck!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178679 91177308-0d34-0410-b5e6-96231b3b80d8
LF/many-sections-2.s
|
| 4385f5dfced4e14bc59dfedb1f75116c0aabbc36 |
03-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: implement ETMv4 trace system registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/trace-regs-diagnostics.s
Arch64/trace-regs.s
isassembler/AArch64/trace-regs.txt
|
| 04011e8429033ae0623ea629527d2d13de3f8109 |
03-Apr-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix the fde encoding used by mips to match gas.
This finally fixes the encoding. The patch also
* Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking
the wrong value.
* Merge fde-reloc.s and eh-frame.s into a single test, since the only difference
was the run lines.
* Don't blindly test the content of the entire .eh_frame section. It makes it
hard to anyone actually fixing a bug and hitting a difference in a binary
blob. Instead, use a CHECK for each field and document what is being checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178615 91177308-0d34-0410-b5e6-96231b3b80d8
ips/eh-frame.ll
ips/eh-frame.s
ips/fde-reloc.s
|
| 732f4bc7c4baa7546b0942f69562d4fb3f474999 |
01-Apr-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips direct object exception handling regression
Revision 177141 caused a regression in all but
mips64 little endian. That is because none of the
other Mips targets had test cases checking the
contents of the .eh_frame section. This patch fixes
both the llvm code and adds an assembler test case
to include the current 4 flavors.
The test cases unfortunately rely on llvm-objdump. A
preferable method would be to use a pretty printer output
such as what readelf -wf <elf_file> would give.
I also changed the name of the test case to correct a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178506 91177308-0d34-0410-b5e6-96231b3b80d8
ips/eh-frame.s
ips/fde-reloc.s
|
| af7da5cb993d1a2afad4816fe22c497d5adbef91 |
29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction
to have an immediate parameter. This patch adds an instruction
alias that converts this macro into a Mips ORI instruction.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
|
| c26392aa5d9c2dbca2909d6874d181455f8aeb8f |
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-rand-encoding.s
|
| 94fcfaf3a9f1179edb3b8053fe7b23eab6fb83bb |
29-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
[Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs
This patch provides alias definitions in td files and test cases to show the usage.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-jump-instructions.s
|
| ce888351106a72825e2a107cb08d7130f3dce0ee |
28-Mar-2013 |
Gordon Keiser <gkeiser@arxan.com> |
Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
They should always be zero-extended, not sign extended. Added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 30509ee8a348116335475beaf9e5504471c86e73 |
28-Mar-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move test since it depends on the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178249 91177308-0d34-0410-b5e6-96231b3b80d8
LF/fde-reloc.s
86/fde-reloc.s
|
| 42a1b2f0b196633c0327801e810fc98849a00c47 |
28-Mar-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: implement GICv3 system registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/gicv3-regs-diagnostics.s
Arch64/gicv3-regs.s
isassembler/AArch64/gicv3-regs.txt
|
| 21fb0193b2fe92794e83e14388e18590d3771150 |
28-Mar-2013 |
Michael Gottesman <mgottesman@apple.com> |
Revert "Updated ELF relocation test for .eh_frame section"
This reverts commit c8d65364223a04b179958a50a4bf0f89b21dd7d2.
This broke a bunch of the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178222 91177308-0d34-0410-b5e6-96231b3b80d8
LF/fde-reloc.s
|
| c8d65364223a04b179958a50a4bf0f89b21dd7d2 |
27-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
Updated ELF relocation test for .eh_frame section
Made sure we were looking a correct section
Added Mips32/64 as an extra check
Updated llvm-objdump to generate symbolic info for Mips relocations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178190 91177308-0d34-0410-b5e6-96231b3b80d8
LF/fde-reloc.s
|
| dd40e8cd54805aa81c8548ac8c87755c562c1723 |
27-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support of imm displacement before bracketed memory
expression. Specifically, this syntax:
ImmDisp [ BaseReg + Scale*IndexReg + Disp ]
We don't currently support:
ImmDisp [ Symbol ]
rdar://13518671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178186 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-ms-inline-asm.s
|
| 09d27fb6ab81b5ee09d15d7fac692945214bf6c9 |
27-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
test file name change to correct typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178174 91177308-0d34-0410-b5e6-96231b3b80d8
ips/ef_frame.ll
ips/eh-frame.ll
|
| b78821d380b6f9514bd3b56b1c27ba367660228b |
26-Mar-2013 |
Joe Abbey <jabbey@arxan.com> |
Patch by Gordon Keiser!
If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 9b3939983fd0103b102c7aec0ed08d1e8bd28214 |
25-Mar-2013 |
Dave Zarzycki <zarzycki@apple.com> |
x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-rtm-encoding.s
|
| 97a80092d3e4413d43e4632a3ec92fcabfd9b378 |
25-Mar-2013 |
Dave Zarzycki <zarzycki@apple.com> |
x86 -- disassemble the REP/REPNE prefix when needed
This fixes Apple bug: 13493622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| d3107fbc54a5b5156f0aabc8788724f1469eb9df |
22-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
Fix the invalid opcode for Mips branch instructions in the assembler
For mips a branch an 18-bit signed offset (the 16-bit
offset field shifted left 2 bits) is added to the
address of the instruction following the branch
(not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
Previously, the code generator did not perform the
shift of the immediate branch offset which resulted
in wrong instruction opcode. This patch fixes the issue.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-jump-instructions.s
|
| 25df6a93f3324bd30f44dcb95fd17aff0a92d438 |
22-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
This patch that enables the Mips assembler to use symbols for offset for instructions
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-expansions.s
|
| c91b5e197bb41ccb2f9f78b6176e61c848df9e15 |
21-Mar-2013 |
Jack Carter <jack.carter@imgtec.com> |
This patch enables the Mips .set directive to define aliases
The .set directive in the Mips the assembler can be
used to set the value of a symbol to an expression.
This changes the symbol's value and type to conform
to the expression's.
Syntax: .set symbol, expression
This patch implements the parsing of the above syntax
and enables the parser to use defined symbols when
parsing operands.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 580f9c85fd7a3c90884ed7ee7c2d613923a53bb3 |
20-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
Fix pr13145 - Naming a function like a register name confuses the asm parser.
Patch by Stepan Dyatkovskiy <stpworld@narod.ru>
rdar://13457826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463 91177308-0d34-0410-b5e6-96231b3b80d8
RM/2013-03-18-Br-to-label-named-like-reg.s
|
| 8ee1c1cfaff9eece05ecabfa267cd68c98af5dd2 |
18-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| 4bef961baf9660f1ac5a5b80378631cd942636b2 |
18-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Refactor some duplicated code into helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| 7a86ffb19fd9e74960690cb41caae390832d3b5a |
15-Mar-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix the FDE encoding to be relative on ELF.
This is a very late complement to r130637 which fixed this on x86_64. Fixes
pr15448.
Since it looks like that every elf architecture uses this encoding when using
cfi, make it the default for elf. Just exclude mips64el. It has a lovely
.ll -> .o test (ef_frame.ll) that tests that nothing changes in the binary
content of the .eh_frame produced by llc. Oblige it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177141 91177308-0d34-0410-b5e6-96231b3b80d8
LF/fde-reloc.s
|
| 9d3f3c5f400578855f6f7b71670cb8514b4fac0f |
14-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-fma4-encoding.s
|
| 12dccaed9c0368f4f5ef4312c32b375c725c9daf |
11-Mar-2013 |
Kevin Enderby <enderby@apple.com> |
Fixes disassembler crashes on 2013 Haswell RTM instructions.
rdar://13318048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
|
| 462bba39c232350894c254d42fbe55f9ff78df56 |
09-Mar-2013 |
Nick Lewycky <nicholas@mxc.ca> |
We need a shndx if the number of sections breaks SHN_LORESERVE. This condition
for choosing to emit a shndx was simply testing the wrong variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176762 91177308-0d34-0410-b5e6-96231b3b80d8
LF/many-sections-2.s
|
| 1ab326310cc9fddf0cc17b981f4f9996f1a19e76 |
05-Mar-2013 |
Eli Bendersky <eliben@google.com> |
Fixes a test by replacing .align by .p2align and setting triples explicitly.
Patch by David Sehr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176502 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_long_nop.s
|
| 81ee0f73685f966ea279b01cbb9587c70ad91bed |
05-Mar-2013 |
David Sehr <sehr@google.com> |
Add a test that .align directives on capable processors use long NOPs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176490 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_long_nop.s
|
| 6c4265a541c9e431961113c1a5d92fb4628bfe13 |
05-Mar-2013 |
David Sehr <sehr@google.com> |
The current X86 NOP padding uses one long NOP followed by the remainder in
one-byte NOPs. If the processor actually executes those NOPs, as it sometimes
does with aligned bundling, this can have a performance impact. From my
micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve
one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch
changes NOP emission to emit as many 15-byte (the maximum) as possible followed
by at most one shorter NOP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
86/AlignedBundling/long-nop-pad.s
|
| df861b3ac4521814903ec39787f5f24c1a79b6a3 |
01-Mar-2013 |
Eli Bendersky <eliben@google.com> |
Rewrite a test to check actual output rather than intermediate implementation
detail.
The was this test was written, it was relying on an implementation detail
(fixups) and hence was very brittle (relying, among other things, on the
exact ordering of statistics printed by MC).
The test was rewritten to check a more observable output difference. While it
doesn't cover 100% of the things the original test covered, it's a good
practice to write regression tests this way. If we want to check that
internal details and invariants hold, such tests should be expressed as unit
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176377 91177308-0d34-0410-b5e6-96231b3b80d8
LF/no-fixup.s
|
| 54a1cf75d2b32cd96ec78f61af5c1bed8d81524d |
28-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: remove post-encoder method from FCMP (immediate) instructions.
The work done by the post-encoder (setting architecturally unused bits to 0 as
required) can be done by the existing operand that covers the "#0.0". This
removes at least one use of the discouraged PostEncoderMethod uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/AArch64/a64-ignored-fields.txt
|
| d65dfd83421f4d26e6dc20476718d7d9b6ba3f3b |
27-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: permit full range of valid ADR immediates.
This fixes an issue where trying to assemlbe valid ADR instructions would cause
LLVM to hit a failed assertion.
Patch by Keith Walker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176189 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| ac67b50fcfaab20829b4bce32cfdce77507f6c72 |
26-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
AsmParser: More generic support for integer type suffices.
For integer constants, allow 'L', 'UL' as well as 'ULL' and 'LL'. This provides
better support for shared headers between .s and .c files that define bunches
of constant values.
rdar://9321056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176118 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_values.s
|
| dca83187b7c4465ad6ff8507052223d31c0ea66a |
25-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for the pushad/popad mnemonics.
rdar://13254235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176036 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-ms-inline-asm.s
|
| 50e75bfc29269def44981ab5f109334d95f55007 |
25-Feb-2013 |
Matt Beaumont-Gay <matthewbg@google.com> |
'Hexadecimal' has two 'a's and only one 'i'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176031 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-hex.s
|
| 1e8ed2537b3e4b2175cd9e62626f07606c62cfa0 |
23-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Convenience aliases for 'srs*' instructions.
Handle an implied 'sp' operand.
rdar://11466783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| 29e05fe7a885bd03d8570d2bcf14193013776bcd |
22-Feb-2013 |
Kristof Beyls <kristof.beyls@arm.com> |
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
RM/neon-vst-encoding.s
RM/neont2-vld-encoding.s
RM/neont2-vst-encoding.s
isassembler/ARM/neon-tests.txt
isassembler/ARM/neon.txt
isassembler/ARM/neont-VLD-reencoding.txt
isassembler/ARM/neont-VST-reencoding.txt
isassembler/ARM/neont2.txt
|
| 77217229ba1bbc92f3a53099fa91bcdaa7797da8 |
21-Feb-2013 |
Jack Carter <jcarter@mips.com> |
Mips specific standalone assembler addressing mode %hi and %lo.
The constructs %hi() and %lo() represent the high and low 16
bits of the address.
Because the 16 bit offset field of an LW instruction is
interpreted as signed, if bit 15 of the low part is 1 then the
low part will act as a negative and 1 needs to be added to the
high part.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175707 91177308-0d34-0410-b5e6-96231b3b80d8
ips/hilo-addressing.s
ips/mips_directives.s
|
| 99e98551bf8719764f9345ce856118f3f1a9c441 |
21-Feb-2013 |
Jack Carter <jcarter@mips.com> |
ELF symbol table field st_other support,
excluding visibility bits.
Mips specific standalone assembler directive "set at".
This directive changes the general purpose register
that the assembler will use when given the symbolic
register name $at.
This does not include negative testing. That will come
in a future patch.
A side affect of this patch recognizes the different
GPR register names for temporaries between old abi
and new abi so a test case for that is included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175686 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
ips/nabi-regs.s
ips/set-at-directive.s
|
| 5cdeca8b1d726790fe9687bc4a4d615d299bc151 |
19-Feb-2013 |
Jack Carter <jcarter@mips.com> |
ELF symbol table field st_other support,
excluding visibility bits.
Mips (o32 abi) specific e_header setting.
EF_MIPS_ABI_O32 needs to be set in the
ELF header flags for o32 abi output.
Contributer: Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175569 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_eflags.ll
|
| c989c61798783f99abe7f8c27baf76bd2aea5067 |
19-Feb-2013 |
Jack Carter <jcarter@mips.com> |
ELF symbol table field st_other support,
excluding visibility bits.
Mips (Mips16) specific e_header setting.
EF_MIPS_ARCH_ASE_M16 needs to be set in the
ELF header flags for Mips16.
Contributer: Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175566 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_eflags.ll
ips/elf_st_other.ll
|
| 8dc741e400213ea8183e09626f0d1f45f14e044f |
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 763c858edeb76173ee4ef5ab9bf7d750db5d8c4f |
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| a970dde9060d8994c242bd186bb3636d2caf22d2 |
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing u10 / lu10 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| cbe6c88b6811e4641629d111f941879982362fe8 |
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing u6 / lu6 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 8a89cf233dcb3359c8649febefb4c38246f2acb4 |
16-Feb-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
MCParser: Reject .balign with non-pow2 alignments.
GNU as rejects them and there are configure scripts in the wild that check if
the assembler rejects ".align 3" to determine whether the alignment is in bytes
or powers of two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175360 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/align_invalid.s
|
| 42edeb1ba8aabcbe0e5cc846d9e5f2a9e2261292 |
16-Feb-2013 |
Joerg Sonnenberger <joerg@bec.de> |
Derive ELF section type from the name in some cases where GNU as does
so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175327 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/section_names.s
|
| 67144e37ba5cd35ee917daac631e03963b05a674 |
15-Feb-2013 |
Derek Schuff <dschuff@google.com> |
If bundle alignment is enabled, do not add data to a fragment with instructions
With bundle alignment, instructions all get their own MCFragments
(unless they are in a bundle-locked group). For instructions with
fixups, this is an MCDataFragment. Emitting actual data (e.g. for
.long) attempts to re-use MCDataFragments, which we don't want int
this case since it leads to fragments which exceed the bundle size.
So, don't reuse them in this case.
Also adds a test and fixes some formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175316 91177308-0d34-0410-b5e6-96231b3b80d8
RM/AlignedBundling/group-bundle-arm.s
|
| 48e841d41c57712f4d6a94b1123f198bdf0bda7d |
15-Feb-2013 |
Joel Jones <joel_k_jones@apple.com> |
The ARM NEON vector compare instructions take three arguments. However, the
assembler should also accept a two arg form, as the docuemntation specifies that
the first (destination) register is optional.
This patch uses TwoOperandAliasConstraint to add the two argument form.
It also fixes an 80-column formatting problem in:
test/MC/ARM/neon-bitwise-encoding
<rdar://problem/12909419> Clang rejects ARM NEON assembly instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| 951d361c2861602d6c886b62318b60a0befee1ac |
14-Feb-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
death to extra whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175200 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-64.txt
|
| 7b672ed380cf44894f8b96c52558dcfc136af383 |
14-Feb-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
isassembler/X86/x86-64.txt
|
| e186d7191c2cf95753a9790b1490df8a07416daa |
14-Feb-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert r15266. This fixes llvm.org/pr15266.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175173 91177308-0d34-0410-b5e6-96231b3b80d8
achO/direction_labels.s
86/intel-syntax-binary.s
|
| b1d081230e40e5c86f3cc44a7cfd7241732eabfb |
14-Feb-2013 |
Kristof Beyls <kristof.beyls@arm.com> |
Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
vld1.8 {d16}, [r0:64]
, while also still accepting the incorrect syntax
vld1.8 {d16}, [r0, :64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
RM/neon-vst-encoding.s
RM/neont2-vld-encoding.s
RM/neont2-vst-encoding.s
isassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
|
| 8915e27704b2afd362a69c6be1111fb06bbcc727 |
12-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for lexing binary integers with a [bB] suffix.
This is complicated by backward labels (e.g., 0b can be both a backward label
and a binary zero). The current implementation assumes [0-9]b is always a
label and thus it's possible for 0b and 1b to not be interpreted correctly for
ms-style inline assembly. However, this is relatively simple to fix in the
inline assembly (i.e., drop the [bB]).
This patch also limits backward labels to [0-9]b, so that only 0b and 1b are
ambiguous.
Part of rdar://12470373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174983 91177308-0d34-0410-b5e6-96231b3b80d8
achO/direction_labels.s
86/intel-syntax-binary.s
|
| 9a790581c01dd6a21e6cc88b18881d08e804c4be |
12-Feb-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
added test cases for r174920 (prefetch disassembly)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174979 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
|
| d556fd129026f6e3fa6ea9c2c70ba489bff18954 |
12-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.
Part of rdar://12470373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174926 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-hex.s
|
| 86494d7991050b4ffbfdcf1d15e1ad5e3c28f07b |
11-Feb-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
*fixed disassembly of some i386 system insts with intel syntax
*added file for test cases for i386 intel syntax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax-32.txt
|
| c37aa995e3e55c1bdb17a73c3160edf0426b1a1a |
11-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: Undo change to how test was run
This broke on Windows, presumably due to interleaving of output streams.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174873 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-a64-diagnostics.s
|
| b5161863866b64498a7faa20e612c55de4bca6f8 |
11-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Make use of DiagnosticType to provide better AArch64 diagnostics.
This gives a DiagnosticType to all AsmOperands in sight. This replaces all
"invalid operand" diagnostics with something more specific. The messages given
should still be sufficiently vague that they're not usually actively misleading
when LLVM guesses your instruction incorrectly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174871 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-a64-diagnostics.s
|
| 0c66403efdf88ff4f247b6a9f45339bb3a893235 |
07-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-jump-instructions.s
|
| cbff068398a84ed488b7fdab5fea8e05500d385a |
06-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 CRC32 instructions
These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-a64-instructions.s
isassembler/AArch64/basic-a64-instructions.txt
|
| 9e3b31345f0d17b757e183a8384db92616256926 |
06-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add icache prefetch operations to AArch64
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-a64-instructions.s
isassembler/AArch64/basic-a64-instructions.txt
|
| f918d7fd7393049bc87bc03fda2d2cd3cec1dacb |
05-Feb-2013 |
Derek Schuff <dschuff@google.com> |
[MC] Bundle alignment: Invalidate relaxed fragments
Currently, when a fragment is relaxed, its size is modified, but its
offset is not (it gets laid out as a side effect of checking whether
it needs relaxation), then all subsequent fragments are invalidated
because their offsets need to change. When bundling is enabled,
relaxed fragments need to get laid out again, because the increase in
size may push it over a bundle boundary. So instead of only
invalidating subsequent fragments, also invalidate the fragment that
gets relaxed, which causes it to get laid out again.
This patch also fixes some trailing whitespace and fixes the
bundling-related debug output of MCFragments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174401 91177308-0d34-0410-b5e6-96231b3b80d8
86/AlignedBundling/relax-at-bundle-end.s
|
| 7304702ef99f98897d15baae0eede55f294bc602 |
05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch that sets the Mips ELF header flag for
MicroMips architectures.
Contributer: Zoran Jovanovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174360 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_eflags.ll
|
| 37ef65b9c1b93c386d13089d9ace6a1cc00e82dc |
05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
ips/mips64-alu-instructions.s
|
| 7bc8414ee99967cb3a89de663c0510563476aa32 |
01-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add explicit triples to AArch64 tests
Only Linux is supported at the moment, and other platforms quickly fault. As a
result these tests would fail on non-Linux hosts. It may be worth making the
tests more generic again as more platforms are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/elf-globaladdress.ll
|
| b11917c1aa7348a67d80149fa9613f09a8d56f14 |
31-Jan-2013 |
Derek Schuff <dschuff@google.com> |
[MC] bundle alignment: prevent padding instructions from crossing bundle boundaries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174067 91177308-0d34-0410-b5e6-96231b3b80d8
86/AlignedBundling/autogen-inst-offset-align-to-end.s
86/AlignedBundling/pad-align-to-bundle-end.s
|
| 72062f5744557e270a38192554c3126ea5f97434 |
31-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
Arch64/basic-a64-diagnostics.s
Arch64/basic-a64-instructions.s
Arch64/elf-globaladdress.ll
Arch64/elf-objdump.s
Arch64/elf-reloc-addsubimm.s
Arch64/elf-reloc-condbr.s
Arch64/elf-reloc-ldrlit.s
Arch64/elf-reloc-ldstunsimm.s
Arch64/elf-reloc-movw.s
Arch64/elf-reloc-pcreladdressing.s
Arch64/elf-reloc-tstb.s
Arch64/elf-reloc-uncondbrimm.s
Arch64/lit.local.cfg
Arch64/mapping-across-sections.s
Arch64/mapping-within-section.s
Arch64/tls-relocs.s
isassembler/AArch64/basic-a64-instructions.txt
isassembler/AArch64/basic-a64-undefined.txt
isassembler/AArch64/basic-a64-unpredictable.txt
isassembler/AArch64/ldp-offset-predictable.txt
isassembler/AArch64/ldp-postind.predictable.txt
isassembler/AArch64/ldp-preind.predictable.txt
isassembler/AArch64/lit.local.cfg
|
| 0f156af8312a0f3ce88e5c006bf2a52691039ceb |
30-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html
Patch by JF Bastien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 97130e2b3de080e231caac86dbce1500e4e7af16 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch implements runtime ARM specific
setting of ELF header e_flags.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-eflags-eabi-cg.ll
RM/elf-eflags-eabi.s
|
| dba14301f0098f9fc5c0d244bf334f55a6a21960 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch implements runtime Mips specific
setting of ELF header e_flags.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_eflags.ll
|
| 9a7bf438b50fed2c77f0e2bc835defa5b4728f82 |
30-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch reworks how llvm targets set
and update ELF header e_flags.
Currently gathering information such as symbol,
section and data is done by collecting it in an
MCAssembler object. From MCAssembler and MCAsmLayout
objects ELFObjectWriter::WriteObject() forms and
streams out the ELF object file.
This patch just adds a few members to the MCAssember
class to store and access the e_flag settings. It
allows for runtime additions to the e_flag by
assembler directives. The standalone assembler can
get to MCAssembler from getParser().getStreamer().getAssembler().
This patch is the generic infrastructure and will be
followed by patches for ARM and Mips for their target
specific use.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-eflags-eabi.s
|
| 0933134a304b47d3767aad202df9f0e09743da6d |
29-Jan-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
[MC][COFF] Delay handling symbol aliases when writing
Fixes PR14447 and PR9034. Patch by Nico Rieck!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173839 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/symbol-alias.s
|
| e6482fabd20a2a5b4f81aff55812782f3b617514 |
29-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Merge SSE and AVX shuffle instructions in the comment printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
86/shuffle-comments.s
|
| 467016e58d57021b14f2ae562d221f00b07cb254 |
28-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix 256-bit PALIGNR comment decoding to understand that it works on independent 256-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
86/shuffle-comments.s
|
| 970a479c02a418726950580e13136acd2a2dc13f |
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| b719d8b1007f6b31ae6d1a66258a26e6a91749bc |
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing l2r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 9d2b1aef1b5bc8926c66b38f03583a77d015e921 |
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 1r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| f5e7e793f196cfba4427321ee9f38ecc8bb8470f |
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 0r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 200b306f2006533a0e7a0ca75cb3103620e7aa84 |
26-Jan-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Decode PALIGN operands so I don't have to do it in my head.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
86/shuffle-comments.s
|
| c47bd9899b639c3384268f871009259c2a94fba4 |
25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l4r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 767295f1143db4ed844ea9d25f9758e624c35302 |
25-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,
use them in tests that run llvm-dwarfdump. This is in order to make tests as
specific as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173498 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comp-dir.s
achO/gen-dwarf-cpp.s
achO/gen-dwarf-macro-cpp.s
achO/gen-dwarf-producer.s
achO/gen-dwarf.s
86/gnux32-dwarf-gen.s
|
| 3b6a5eefe0ab2199bc69094b390b736ae332b905 |
25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l5r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 801c5838830d190a6b0d8e462bd43805f66ba50f |
25-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch implements parsing the .word
directive for the Mips assembler.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| 9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b |
23-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l6r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 0ec35ac4fcd5c83e2ec35d04fc20db9eb387d289 |
22-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for u10 / lu10 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 221514efe92676ce84a5e21bea91d8a6b21f9ed7 |
22-Jan-2013 |
Kevin Enderby <enderby@apple.com> |
Add a warning when there is a macro defintion that has named parameters but
the body does not use them and it appears the body has positional parameters.
This can cause unexpected results as in the added test case. As the darwin
version of gas(1) which only supported positional parameters, happened to
ignore the named parameters. Now that we want to support both styles of
macros we issue a warning in this specific case.
rdar://12861644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173199 91177308-0d34-0410-b5e6-96231b3b80d8
achO/bad-macro.s
|
| 5de048ec30f9ef9f56c89f9fdb50022beca6ae88 |
22-Jan-2013 |
Kevin Enderby <enderby@apple.com> |
Have the integrated assembler give an error if $1 is used as an identifier in
an expression. Currently this bug causes the line to be ignored in a
release build and an assert in a debug build.
rdar://13062484
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173195 91177308-0d34-0410-b5e6-96231b3b80d8
achO/bad-dollar.s
|
| aaf483ff1775a6b7b0022158c59e73e404d568ef |
22-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add forgotten test case for the x32 commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173181 91177308-0d34-0410-b5e6-96231b3b80d8
86/gnux32-dwarf-gen.s
|
| 341c5fbe840cffedc4155a2cf130626d2bba11b5 |
22-Jan-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Make sure we account for the FMA4 register immediate value, otherwise rip-rel relocations will be off by one byte.
PR15040.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-fma4-encoding.s
|
| 849209686f778e5d6fce675bea9a8300aa596d25 |
22-Jan-2013 |
Daniel Dunbar <daniel@zuster.org> |
[MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173120 91177308-0d34-0410-b5e6-96231b3b80d8
achO/linker-options.ll
|
| 8da543434664986ac19f4753a691fb613ba80778 |
21-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for u6 / lu6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 9b709f8b3f3fa6e9bfb5007b70e096f6192f3ef8 |
21-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encoding / disassembly support for ru6 / lru6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| b853c415c663c752c669cb191cea95542c1d21f6 |
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| c78ec6b6bc05572aed6af1eee4349d76a68ded18 |
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l3r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| a68c64fbb2f1bee7f9313f3ee19c35677563f974 |
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembler support for 2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 62b8786d12ceacafd665d4a1fbb6e90af0ec368c |
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| c91cbb9b0c90a480299cc7deaef166d47a61d9df |
18-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.
Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.
The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.
This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172847 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-reginfo.ll
|
| e72fac60e3dbcf14ec68cedc1e86feafec1652eb |
18-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Removal of redundant code and formatting fixes.
Contributers: Jack Carter/Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-coprocessor-encodings.s
|
| 6d49b680be6e24b547e6910c2b64914913915084 |
18-Jan-2013 |
Daniel Dunbar <daniel@zuster.org> |
[MC/Mach-O] Implement integrated assembler support for linker options.
- Also, fixup syntax errors in LangRef and missing newline in the MCAsmStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172837 91177308-0d34-0410-b5e6-96231b3b80d8
achO/linker-options.ll
|
| a94c33942373cb504b6e64c95415165907a89d34 |
18-Jan-2013 |
Daniel Dunbar <daniel@zuster.org> |
[MC/Mach-O] Add support for linker options in Mach-O files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172779 91177308-0d34-0410-b5e6-96231b3b80d8
achO/linker-option-2.s
|
| cddd236e8a5acb80e9a0e79dc63f6cfaa8205b86 |
18-Jan-2013 |
Daniel Dunbar <daniel@zuster.org> |
[MC/Mach-O] Add AsmParser support for .linker_option directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172778 91177308-0d34-0410-b5e6-96231b3b80d8
achO/linker-option-1.s
|
| c147b678206db510336ee95c3b55dc9c0ff19595 |
17-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
ips/mips-alu-instructions.s
ips/mips64-alu-instructions.s
|
| 75c9b9384f50e9387f24dd7ce6af403cbda6d19a |
16-Jan-2013 |
Kevin Enderby <enderby@apple.com> |
We want the dwarf AT_producer for assembly source files to match clang's
AT_producer. Which includes clang's version information so we can tell
which version of the compiler was used.
This is the first of two steps to allow us to do that. This is the llvm-mc
change to provide a method to set the AT_producer string. The second step,
coming soon to a clang near you, will have the clang driver pass the value
of getClangFullVersion() via an flag when invoking the integrated assembler
on assembly source files.
rdar://12955296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172630 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf-producer.s
|
| 457ee1a12e2c52624af7fdb81cf938f6d8d96572 |
16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
reverting 172579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
ips/mips-alu-instructions.s
ips/mips64-alu-instructions.s
|
| 490c7d97737ea7719efcea7321d3cfa3984b0027 |
16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
Akira,
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
ips/mips-alu-instructions.s
ips/mips64-alu-instructions.s
|
| 096d617796228293810cb0443c6617b33c5afdc5 |
15-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch fixes a Mips specific bug where
we need to generate a N64 compound relocation
R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.
The bug was exposed by the SingleSourcetest case
DuffsDevice.c.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172496 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-gprel-32-64.ll
|
| dd2e8950222ab74157b1c083ffa77b0fbaf1d210 |
14-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Extend support for parsing Intel bracketed memory operands that
have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| ec3199f675b17b12fd779df557c6bff25aa4e862 |
12-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
ips/mips64-alu-instructions.s
|
| a1db5de9e70dd8ffda57b1a4373915ea866b6f1d |
09-Jan-2013 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: EH adjustments
This patch adjust the r171506 to make all DWARF enconding pc-relative
for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT
(since the eh_frame will not generate PIC-relative relocation) and also
adds the emission of stubs created by the TTypeEncoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171979 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-initial-cfa.ll
|
| 4a50e53e53816076584c957741cb430899271726 |
08-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch produces the correct addend value for
an R_MIPS_GPREL16 relocation.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171882 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_gprel16.ll
|
| 26853a5d1c39c3e4ddab3dc9f3d1f97815d974d2 |
08-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch produces the correct pointer size
value in the 64 bit .eh_frame section.
It doesn't however allow exception handling to work
yet since it depends on the correct relocation model
being set in the ELF header flags.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171881 91177308-0d34-0410-b5e6-96231b3b80d8
ips/ef_frame.ll
|
| 59d152197d741ab930dfc99ced3cac1b8bc8bef9 |
08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add some additional tests for the .bundle_lock align_to_end feature that didn't
make into the last commit.
Also, update the test-generation script to generate an exhaustive test for
align_to_end as well, and include the generated test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171811 91177308-0d34-0410-b5e6-96231b3b80d8
RM/AlignedBundling/pad-align-to-bundle-end.s
86/AlignedBundling/autogen-inst-offset-align-to-end.s
86/AlignedBundling/bundle-lock-option-error.s
86/AlignedBundling/pad-align-to-bundle-end.s
|
| 6c1d4972cf1cd6b6072e31c05f97abb1ed7a8497 |
07-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add the align_to_end option to .bundle_lock in the MC implementation of aligned
bundling. The document describing this feature and the implementation has also
been updated:
https://sites.google.com/a/chromium.org/dev/nativeclient/pnacl/aligned-bundling-support-in-llvm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171797 91177308-0d34-0410-b5e6-96231b3b80d8
RM/AlignedBundling/group-bundle-arm.s
86/AlignedBundling/asm-printing-bundle-directives.s
|
| f564a9389da68266f44314fe38ab399fd2211134 |
06-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86-32-avx.s
86/x86-32-coverage.s
86/x86-64.s
86/x86_64-avx-encoding.s
|
| 7b449889e7886b263718b5103538970f287bc37e |
04-Jan-2013 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix eh_frame relocation for PIC
This patch fixes the PPC eh_frame definitions for the personality and
frame unwinding for PIC objects. It makes PIC build correctly creates
relative relocations in the '.rela.eh_frame' segments and thus avoiding
a text relocation that generates a DT_TEXTREL segments in link phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171506 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-initial-cfa.ll
|
| 5bf3a28b36c5d95ad3732b749db651630027b09c |
02-Jan-2013 |
Kevin Enderby <enderby@apple.com> |
Adds missing aliases for fcom and fcomp instructions without arguments.
Patch by Michael M Kuperstein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171414 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
|
| 189225369446136f82e080dbdcab3a0fa63c71ac |
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-jump-instructions.s
|
| 15019a8814b7877367ca7bcd7d173710259f7c20 |
20-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Change Lit error redirection to FileCheck to a more common syntax since it
can potentially cause some bots to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170726 91177308-0d34-0410-b5e6-96231b3b80d8
86/AlignedBundling/align-mode-argument-error.s
86/AlignedBundling/asm-printing-bundle-directives.s
86/AlignedBundling/bundle-group-too-large-error.s
86/AlignedBundling/lock-without-bundle-mode-error.s
86/AlignedBundling/switch-section-locked-error.s
86/AlignedBundling/unlock-without-lock-error.s
|
| b17201f1b8c35414e3bbd71c3f37ee6313d77e86 |
20-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Add a largish auto-generated test for the aligned bundling feature, along with
the script generating it. The test should never be modified manually. If anyone
needs to change it, please change the script and re-run it.
The script is placed into utils/testgen - I couldn't think of a better place,
and after some discussion on IRC this looked like a logical location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170720 91177308-0d34-0410-b5e6-96231b3b80d8
86/AlignedBundling/autogen-inst-offset-padding.s
|
| 16996c4940ad4248dc2a874d060b30e94e55b672 |
20-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Tests for the aligned bundling support added in r170718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170719 91177308-0d34-0410-b5e6-96231b3b80d8
RM/AlignedBundling/group-bundle-arm.s
RM/AlignedBundling/lit.local.cfg
86/AlignedBundling/align-mode-argument-error.s
86/AlignedBundling/asm-printing-bundle-directives.s
86/AlignedBundling/bundle-group-too-large-error.s
86/AlignedBundling/different-sections.s
86/AlignedBundling/lit.local.cfg
86/AlignedBundling/lock-without-bundle-mode-error.s
86/AlignedBundling/pad-bundle-groups.s
86/AlignedBundling/relax-in-bundle-group.s
86/AlignedBundling/single-inst-bundling.s
86/AlignedBundling/switch-section-locked-error.s
86/AlignedBundling/unlock-without-lock-error.s
|
| 759e3fa641d0ad01012d16d913015c9f69c8d2ab |
19-Dec-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Remove edis - the enhanced disassembler. Fixes PR14654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/enhanced.txt
|
| f8cd4df30488f182975075be095f3cdd1f9f5a30 |
18-Dec-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/test/MC/ELF/comp-dir.s: Appease MSYS Bash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170410 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comp-dir.s
|
| 1b6e9b867b2d48ec18127960a5d2c1be7e39ca94 |
17-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Add a triple to this test -- it has to be an ELF platform...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170374 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comp-dir.s
|
| 6c31d313575bba1b87b583260f39f0b0dae143f4 |
17-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Prepare LLVM to fix PR14625, exposing a hook in MCContext to manage the
compilation directory.
This defaults to the current working directory, just as it always has,
but now an assembler can choose to override it with a custom directory.
I've taught llvm-mc about this option and added a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170371 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comp-dir.s
|
| c47793c62c434bd27fee1d243c2081a34d4f3817 |
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| a839ffc323396326ebdcf8d065c60be0bf05420d |
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings for PEEK and ENDIN.
Previously these were marked with the wrong format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170334 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 35150cbf4166ae8d69032d355f1e8d83b4a6eb3c |
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| ff6114e872742e966c57202add83b84611e63e97 |
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings for ZEXT and SEXT.
Previously these were marked with the wrong format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170327 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| 1ffe48a84b398e8cebbdc7a47bedb57e1e67e63f |
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for 2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| dd78daa199f653b64b997fdee46db8964e5c50cc |
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for 0r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/xcore.txt
|
| e4e0089e45350f99c80ece1781671028368708c1 |
16-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add tests for disassembly of 1r XCore instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170295 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/XCore/lit.local.cfg
isassembler/XCore/xcore.txt
|
| a827a47923700c16256036ca0bda8c0ff6108fdb |
15-Dec-2012 |
Kevin Enderby <enderby@apple.com> |
Make sure the alternate PC+imm syntax of LDR instruction with a small
immediate generates the narrow version. Needed when doing round-trip
assemble/disassemble testing using the alternate syntax that specifies
'pc' directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 25953bfb0763047df28c01057183493490667531 |
13-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Make this Lit config file a bit slimmer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170083 91177308-0d34-0410-b5e6-96231b3b80d8
86/lit.local.cfg
|
| 659dacd66fce1cff13661976200f6c7125e38678 |
11-Dec-2012 |
Hao Liu <Hao.Liu@arm.com> |
revert the test change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169823 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| 7fc66a22d8a9e099572b05ba38523ac3cc95a87e |
11-Dec-2012 |
Hao Liu <Hao.Liu@arm.com> |
A newbie try a test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169821 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| e1dee8a06e93f38f81f09887361045367a810436 |
10-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Add a test for explicitly exercising the mc-relax-all flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169764 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relax-all-flag.s
|
| 8ddc5a192935728c15602a4c15501e35f116422d |
07-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Add separate statistics for Data and Inst fragments emitted during relaxation.
Also fixes a test that was overly-sensitive to the exact order of statistics
emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169619 91177308-0d34-0410-b5e6-96231b3b80d8
LF/no-fixup.s
|
| 6eb3e87df04f8b035562d9865292c23f5b79f1a2 |
07-Dec-2012 |
Tim Northover <Tim.Northover@arm.com> |
Added Mapping Symbols for ARM ELF
Before this patch, when you objdump an LLVM-compiled file, objdump tried to
decode data-in-code sections as if they were code. This patch adds the missing
Mapping Symbols, as defined by "ELF for the ARM Architecture" (ARM IHI 0044D).
Patch based on work by Greg Fitzgerald.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169609 91177308-0d34-0410-b5e6-96231b3b80d8
RM/data-in-code.ll
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-reloc-condcall.s
RM/elf-thumbfunc-reloc.ll
RM/elf-thumbfunc.s
RM/mapping-within-section.s
RM/multi-section-mapping.s
RM/relocated-mapping.s
|
| f2a1c83c86ceefb9a241aa728d1d1239a64b894e |
05-Dec-2012 |
David Sehr <sehr@google.com> |
Correct ARM NOP encoding
The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which
causes the emission of a coprocessor instruction rather than "mov r0, r0"
as indicated in the comment. The test also checks for the wrong encoding.
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169420 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/nop-armv4-padding.s
|
| d224f28437acb486fcc1c405d8e33302cf0999ab |
05-Dec-2012 |
David Sehr <sehr@google.com> |
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169410 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/nop-armv4-padding.s
|
| 14ccc9007a932a23201251ced4be4c898a62d6a5 |
05-Dec-2012 |
Kevin Enderby <enderby@apple.com> |
Added a option to the disassembler to print immediates as hex.
This is for the lldb team so most of but not all of the values are
to be printed as hex with this option. Some small values like the
scale in an X86 address were requested to printed in decimal
without the leading 0x.
There may be some tweaks need to places that may still be in
decimal that they want in hex. Specially for arm. I made my best
guess. Any tweaks from here should be simple.
I also did the best I know now with help from the C++ gurus
creating the cleanest formatImm() utility function and containing
the changes. But if someone has a better idea to make something
cleaner I'm all ears and game for changing the implementation.
rdar://8109283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169393 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/hex-immediates.txt
isassembler/X86/hex-immediates.txt
|
| a790bc12c147fb716d6979c2279e95e0379eb090 |
04-Dec-2012 |
Eli Bendersky <eliben@google.com> |
A test in thid directory was not being run because lit.local.cfg didn't
include .ll files. Fix that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169283 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/lit.local.cfg
|
| 1c83093cd5f4f6d33e732c817bb5afd033531beb |
30-Nov-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
which would then cause an assert when printed. rdar://11437956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168960 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-BFI.txt
|
| 781dfbd482c5177215ae7a43c9483e641eeb0d47 |
28-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix initial frame state on powerpc64.
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame
pointer register, but on PPC64 the 32-bit R1 register does not
have a corresponding DWARF number, causing invalid CIE initial
frame state to be emitted. Fix by using PPC::X1 instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168799 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-initial-cfa.ll
|
| eb6363adf05b65b0ec079ad7cbcb871acdb60a8c |
27-Nov-2012 |
Eric Christopher <echristo@gmail.com> |
The section is .debug_line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168666 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf.s
|
| 527ba9c88d03b95d7e983dbad4daf5daed0d4885 |
27-Nov-2012 |
Eli Bendersky <eliben@google.com> |
Make this test less sensitive.
It currently assumes register numbering and any harmless change in the X86
register naming makes it fail. It's enough to match the register names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168632 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/enhanced.txt
|
| f4f14f68f6078ea6681ee27b5bf42719d7db3441 |
25-Nov-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .cfi_register now that it is easy to extent the representation
to support it. Original patch with the parsing and plumbing by the PaX team and
Roman Divacky. I added the bits in MCDwarf.cpp and the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168565 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-register.s
|
| c8fec7e21f5c24303eab8a8592f3b8faff347d86 |
23-Nov-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement .cfi_undefined. Based on a patch from PaX team, updated by
Roman Divacky. I just added the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168520 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-undefined.s
|
| 198ad916d736047f8a439f19dee25cee917df8a9 |
22-Nov-2012 |
Jack Carter <jcarter@mips.com> |
Mips direct object xgot support
This patch provides support for the MIPS relocations:
*) R_MIPS_GOT_HI16
*) R_MIPS_GOT_LO16
*) R_MIPS_CALL_HI16
*) R_MIPS_CALL_LO16
These are used for large GOT instruction sequences.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168471 91177308-0d34-0410-b5e6-96231b3b80d8
ips/xgot.ll
|
| 527388dea5b4220f463a7cef6b1012770d1a80a5 |
15-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch is in preparation for adding medium code model support to the
PPC64 target. The five tests modified herein test code generation that is
sensitive to the code model selected. So I've added -code-model=small to
the RUN commands for each.
Since small code model is the default, this has no effect for now; but this
prepares us for eventually changing the default to medium code model for PPC64.
Test changes verified with small and medium code model as default on
powerpc64-unknown-linux-gnu. All tests continue to pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167999 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-relocs-01.ll
|
| de7c8530c85181c78fbb30a305749ee3a71cfc51 |
14-Nov-2012 |
Jakub Staszak <kubastaszak@gmail.com> |
Remove DOS line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167968 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
|
| 3ca6382120c16e30151e19175d40480ee72de641 |
14-Nov-2012 |
Jim Grosbach <grosbach@apple.com> |
X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.
When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.
rdar://12700702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_errors.s
|
| 15ab115df57949fa55d92ffdfba491f7d02ed60f |
14-Nov-2012 |
Alexey Samsonov <samsonov@google.com> |
Emit relocations from .debug_aranges to .debug_info for asm files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167926 91177308-0d34-0410-b5e6-96231b3b80d8
LF/gen-dwarf.s
|
| 4de5872dede6e3dd80f7ab3df5df4fe0e33e3b2e |
13-Nov-2012 |
Michael J. Spencer <bigcheesegs@gmail.com> |
[MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167877 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/weak-symbol-section-specification.ll
|
| 51abc9877e229bddf258d24386ab8d394e93ac33 |
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Add test case to verify correct relocs being generated for
TLS symbols on PowerPC using the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167875 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/ppc64-tls-relocs-01.ll
|
| 785500618afc50f5914f798ea224cf8405dce29d |
10-Nov-2012 |
Evan Cheng <evan.cheng@apple.com> |
Convert an improper CodeGen test to a MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-jump24-fixup.s
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-rtm-encoding.s
|
| 32c1a82a6b1d934e30e05c0e18b9e57fde96c56f |
05-Nov-2012 |
Kevin Enderby <enderby@apple.com> |
Fix for PR14264 cause by commit r167237 which did not take into account a
possible buffer change with a .macro directive.
rdar://12637628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167408 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf-macro-cpp.s
|
| 11a45c214c26bdc49ef58c0eb214df5200867cee |
03-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
ips/sext_64_32.ll
|
| 53e93e85e00693d904861532350383ceaf330bca |
02-Nov-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix disassembler test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167326 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
|
| 938482f522d6d144a9af7897af1433f00f630588 |
01-Nov-2012 |
Kevin Enderby <enderby@apple.com> |
Add support for generating dwarf debugging info with assembly files
run through the 'C' preprocessor. That is pick up the file name
and line numbers from the cpp hash file line comments for the
dwarf file and line numbers tables.
rdar://9275556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167237 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf-cpp.s
|
| 7dd4dc88921421cd2a1e6c1711689d5993106767 |
01-Nov-2012 |
Jim Grosbach <grosbach@apple.com> |
MC: Simple example parser for MC assembly markup.
Nothing fancy, just a simple demonstration parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167181 91177308-0d34-0410-b5e6-96231b3b80d8
arkup/basic-markup.mc
arkup/lit.local.cfg
|
| 8ba1474181fc3997cc8449d75065e1021c72d49b |
30-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Better disassembly for pc-relative LDR.
When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.
rdar://12154503
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
isassembler/ARM/marked-up-thumb.txt
isassembler/ARM/thumb-printf.txt
isassembler/ARM/thumb-tests.txt
isassembler/ARM/thumb1.txt
|
| 445ba85b8d7bc8fb4689ca22131cadc80a034705 |
30-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2-b.w-encodingT4.s
isassembler/ARM/thumb2.txt
|
| 2fbc239e4fbdd12c24fb2cf9e3e915861fc12030 |
29-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] is
equivalent to [expr1 + expr2]. See test cases for more examples.
rdar://12470392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166949 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-ms-inline-asm.s
|
| aa71428378c1cb491ca60041d8ba7aa110bc963d |
25-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
Initial TOC support for PowerPC64 object creation
This patch adds initial PPC64 TOC MC object creation using the small mcmodel
(a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC,
R_PPC64_TOC16, and R_PPC64_TOC16DS).
The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter'
is meant to avoid the creation of an unreferenced ".TOC." symbol (used in
the .odp creation) as well to set the R_PPC64_TOC relocation target as the
temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should
not point to any symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
owerPC/lit.local.cfg
owerPC/ppc64-relocs-01.ll
|
| d95666c226e41218a07541aaa2cc1fba823c25e4 |
25-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
Tell llvm-mc we're using intel syntax, so we don't have to use directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166640 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-ms-inline-asm.s
|
| b3009eec47d2aaa61cc848a66a7bbd69ad9e0f19 |
25-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add back-end test case for r166632. Make sure we emit the
correct .s output as well as get the correct encoding by the integrated
assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166638 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-ms-inline-asm.s
|
| 3ed0316f756e2f1730f46654776fcf77f5ace7aa |
23-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Add support for annotated disassembly output for X86 and arm.
Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.
rdar://11764962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/marked-up-thumb.txt
isassembler/X86/marked-up.txt
|
| 08b6b81ec57e7d8b99844b7f4a211942570ffff1 |
13-Oct-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Depending on the local semantics of .align this test can also emit a nopl instead of nopw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165880 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_nop.s
|
| 126afcbf654e42dc3f659a1a66bfa8a784e7bd46 |
13-Oct-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Disable long nops for all cpus prior to pentiumpro/i686.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165878 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_nop.s
|
| a54b2dfb0a706cdede7be53302d5237ae79f6eed |
11-Oct-2012 |
David Chisnall <csdavec@swan.ac.uk> |
Add test cases for correct parsing of register names in 32- and 64-bit modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165713 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-register-names.s
ips/mips64-register-names.s
|
| aa5b393c69cf24d47a5727d15584f3daeba1aead |
11-Oct-2012 |
David Chisnall <csdavec@swan.ac.uk> |
Expose move to/from coprocessor instructions in MIPS64 mode.
Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode. We should ensure that this is easy to
do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-coprocessor-encodings.s
|
| ebf3a37c0a5cea1ded89750e88d672951bf133cc |
10-Oct-2012 |
Craig Topper <craig.topper@gmail.com> |
Test case for r165480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165594 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| 2f68b311a1b0efb3cafeca3780f5c3d09a762a50 |
10-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Initial assembler implementation of Mips load address macro
This patch provides initial implementation of load address
macro instruction for Mips. We have implemented two kinds
of expansions with their variations depending on the size
of immediate operand:
1) load address with immediate value directly:
* la d,j => addiu d,$zero,j (for -32768 <= j <= 65535)
* la d,j => lui d,hi16(j)
ori d,d,lo16(j) (for any other 32 bit value of j)
2) load load address with register offset value
* la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535)
* la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j)
ori d,d,lo16(j)
addu d,d,s
This patch does not cover the case when the address is loaded
from the value of the label or function.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-expansions.s
|
| de3322746280b957d552cc5e69e121b38c07406c |
06-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Adding support for instructions mfc0, mfc2, mtc0, mtc2
move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
|
| 9d577c861414c28967d77c2a1edf64b68efdeaee |
04-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.
We have identified three possible expansions depending on
the size of immediate operand:
1) for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
2) for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
3) for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)
All of the above have been implemented in ths patch.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-expansions.s
|
| 30116cd2e24a4a2b6c2771ef2665d655de93b984 |
04-Oct-2012 |
Jack Carter <jcarter@mips.com> |
This patch is a partial implementation of mips .set assembler directive. Directive is defined as follows:
.set option
The patch implements following options
at - lets the assembler use the $at register for macros,
but generates warnings if the source program uses $at
noat - let source programs use $at without issuingwarnings.
noreorder - prevents the assembler from reordering machine
language instructions.
nomacro - causes the assembler to print a warning whenever
an assembler operation generates more than one
machine language instruction.
macro - lets the assembler generate multiple machine instructions
from a single assembler instruction
reorder - lets the assembler reorder machine language
instructions to improve performance
The above variants are parsed and their boolean values set or unset.
The code to actually use them will come later.
Following options are not implemented yet:
nomips16
nomicromips
move
nomove
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165194 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| b4316028b3978e65cc2b97042292637857dfad49 |
02-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
MachO: direct-to-object attribute for data-in-code markers.
The target backend can support data-in-code load commands even when
the assembler doesn't, or vice-versa. Allow targets to opt-in for
direct-to-object.
PR13973.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164974 91177308-0d34-0410-b5e6-96231b3b80d8
achO/lit.local.cfg
achO/x86-data-in-code.ll
|
| b7abea08409d4f15063b25e025f160a5469efd54 |
26-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
X86_32: Large Symbol+Offset relocations.
If the offset is more than 24-bits, it won't fit in a scattered
relocation offset field, so we fall back to using a non-scattered
relocation.
rdar://12358909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164724 91177308-0d34-0410-b5e6-96231b3b80d8
achO/i386-large-relocations.s
|
| fe2d5f848764dff8f9ba734a5e2438ca1535890e |
25-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Darwin BL/BLX relocations to out-of-range symbols.
When a BL/BLX references a symbol in the same translation unit that is
out of range, use an external relocation. The linker will use this to
generate a branch island rather than a direct reference, allowing the
relocation to resolve correctly.
rdar://12359919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/long-call-branch-island-relocation.s
|
| fbc21fabaef9a74334c54574a4949f864451f1b6 |
25-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.
rdar://9795790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-arithmetic-aliases.s
|
| 371e17c03c3169459c84986d4a318f6d6d3f8730 |
23-Sep-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit dtors into proper section while compiling in vcpp-compatible mode.
Patch by Kai!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164476 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/global_ctors.ll
OFF/global_ctors_dtors.ll
|
| bb5174246b5d0dfbd057b3641f5e134fe74ea0f4 |
22-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Fix edge cases of ARM shift operands in arith instructions.
As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-shift-encoding.s
RM/thumb-shift-encoding.s
|
| 93c7c449a1351542fa5a275587187154dbedb8e0 |
22-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-shift-encoding.s
RM/diagnostics.s
|
| 7b6f2034ac355bd3b3cc88960bf8d0e694fe3db4 |
19-Sep-2012 |
Preston Gurd <preston.gurd@intel.com> |
Add support for macro parameters/arguments delimited by spaces,
to improve compatibility with GNU as.
Based on a patch by PaX Team.
Fixed assertion failures on non-Darwin and added additional test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164248 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros-darwin.s
smParser/macros.s
|
| 6c9176aeec549adb4bbdd499664c4304ee151f68 |
19-Sep-2012 |
Preston Gurd <preston.gurd@intel.com> |
Support default parameters/arguments for assembler macros.
This patch is based on the one by PaX Team.
Patch by Andy Zhang!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164246 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-args.s
|
| 6579eea90dfeb7540e37307cc30c8677759c5e4d |
19-Sep-2012 |
Preston Gurd <preston.gurd@intel.com> |
Enhance unmatched '.endr' directive error message in assembler.
The directive can be matched with directives other than '.rept'
Patch by Andy Zhang!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164245 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-rept-err1.s
|
| 2811ae66a857691b47fbcf98a12521380c05aad0 |
19-Sep-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.
-mcpu doesn't infer -arch. Consider non-x86 host.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164185 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_nop.s
|
| 36b07f2f07d3dbd4b803a2ac899d6c3c2202ae8c |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Add test for r164132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164134 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_nop.s
|
| 3f90a4c42d1683600e91c2aea325bacf59c37f5e |
14-Sep-2012 |
Jim Grosbach <grosbach@apple.com> |
Assembler: Darwin variables defined via .set are no-dead-strip.
For gas compatibility.
rdar://12219394
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163854 91177308-0d34-0410-b5e6-96231b3b80d8
achO/absolute.s
|
| 2cfe90b1191ea770ce5e47f6536508e89b829b17 |
11-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Add newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163565 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-2.s
|
| 3c4ecd7dab5567017ad573769b0af484479bac6f |
10-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for .att_syntax directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-2.s
|
| a9e37c5eaf79c3a32f2921536fb7e12514e86fb2 |
07-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix alignment of .comm and .lcomm on mingw32.
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't
use the same setting for both. Fix this by reintroducing the LCOMM enum.
I verified this against mingw's gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163420 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/comm.ll
|
| b72a90e05b296d13b6fb4efc54eee9f6f5c0ea7b |
07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
Initial relocations test for the Mips standalone assembler.
This is not an exhaustive set, but something we can build on.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163419 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-relocations.s
|
| 39646d96e76aea5d20bffb386233a0dbb5932a21 |
07-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_lcomm.s
smParser/labels.s
LF/lcomm.s
|
| 8e70b5506ec0d7a6c2740bc89cd1b8f12a78b24f |
07-Sep-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for registers.
gas accepts this and it seems to be common enough to be worth supporting. This
doesn't affect the parsing of reg operands outside of .cfi directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163390 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-reg.s
|
| 04376ebe9f203213ef1eb4c69396fe280dc8c8b1 |
07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler aliased instruction support.
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.
These changes are in the instruction td file.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
ips/mips-jump-instructions.s
|
| acbea45573078631e116c2aa91e57d3a9cb2dde1 |
07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler intial directive support.
Actually these are just stubs for parsing the directives.
Semantic support will come later.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163364 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips_directives.s
|
| f740d6e328bd10904b079e1ce6583f436d6c9817 |
07-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler fpu instruction support.
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-fpu-instructions.s
ips/mips-memory-instructions.s
|
| 6b96c3f71fce6b0a7c380dfc3b7ebf22c40e804b |
06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
The Mips standalone assembler memory instruction support.
This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw
Test case included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163346 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-memory-instructions.s
|
| 24b9f258f194c5e472bf133f9bbf5ca26ad500d3 |
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Diagnose invalid alignments on duplicating VLDn instructions.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt
|
| eae1d34029c159306ce4a0472294de6cf9baedac |
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt
isassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt
isassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt
isassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt
isassembler/ARM/neont-VLD-reencoding.txt
|
| 64eacd9136dc45e54dd2728117f71403701fd39c |
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Use correct part of complex operand to encode VST1 alignment.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neont-VST-reencoding.txt
|
| ad51a4a5984a365d671ddfe9eaa23d2e12ee4281 |
06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific llvm assembler support for branch and jump instructions.
Test case included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-jump-instructions.s
|
| ec65be84cd630d53233e7a37f0ef9d2303ac5153 |
06-Sep-2012 |
Jack Carter <jcarter@mips.com> |
Mips specific llvm assembler support for ALU instructions. This includes
register support. Test case included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163268 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips-alu-instructions.s
|
| 3185f9a2ea80afec30064b7cd095f82c31dc154e |
31-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips64extins.ll
|
| 9765c6ecde9ca96c37fe3e27d360aadc387b6942 |
31-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
X86: Fix encoding of 'movd %xmm0, %rax'
The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162963 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 714313b4828cec98b086b54b356407540aa775c4 |
28-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips64extins.ll
|
| 69dba7e20476ec0e64791e47b498ae3a69619f7d |
28-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Some instructions are passed to the assembler to be
transformed to the final instruction variant. An
example would be dsrll which is transformed into
dsll32 if the shift value is greater than 32.
For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips64shift.ll
|
| 273956d8c6eed86c8b4d616ecb86f7ff17e127d4 |
28-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix mips' long branch pass.
Instructions emitted to compute branch offsets now use immediate operands
instead of symbolic labels. This change was needed because there were problems
when R_MIPS_HI16/LO16 relocations were used to make shared objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8
ips/higher_highest.ll
|
| 6522a9e04bcfa447299f4fd10ee9afffd5834a47 |
22-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add option disable-mips-delay-filler. Turn on mips' delay slot filler by
default.
Patch by Carl Norum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162339 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-N64.ll
ips/mips64shift.ll
ips/multi-64bit-func.ll
|
| 101771ba4d9c2421f836069fcedf9ddc8a0c9dc7 |
22-Aug-2012 |
Jack Carter <jcarter@mips.com> |
For mips64 switch statements in subroutines could generate
within the codegen EK_GPRel64BlockAddress. This was not
supported for direct object output and resulted in an assertion.
This change adds support for EK_GPRel64BlockAddress for
direct object.
One fallout from this is to turn on rela relocations
for mips64 to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162334 91177308-0d34-0410-b5e6-96231b3b80d8
ips/do_switch.ll
|
| 799aacfb27ac51417ad17f4548b9f7743f946e66 |
21-Aug-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix macros arguments with an underscore, dot or dollar in them. This is based
on a patch by Andy/PaX. I added the support for dot and dollar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162298 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros.s
|
| d7ae0f187635003c385901906fe2cdd95bf13057 |
21-Aug-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make the wording in of the "expected identifier" error in the .macro directive
consistent with the other "expected identifier" errors.
Extracted from the Andy/PaX patch. I added the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162291 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/bad-macro.s
|
| 6d2986cd0374b86e23fe60a57b40ae01d057ce3b |
14-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.
These tests weren't actually being run before (missing ':' after CHECK).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161800 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| af402acff30acda75bbdc4aaad653db9dceacaba |
12-Aug-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Give this test an explicit triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161740 91177308-0d34-0410-b5e6-96231b3b80d8
LF/fde.s
|
| 0c5602de8c0dfa716f54306a1c540b98ab803584 |
12-Aug-2012 |
Nick Lewycky <nicholas@mxc.ca> |
When emitting the PC range in an FDE, use the same data encoding for both ends
of the range. Fixes PR13581!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161739 91177308-0d34-0410-b5e6-96231b3b80d8
LF/fde.s
|
| 8d7e5efcaa5a1625e9518d090697f08d6d1110d5 |
09-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Another 32 to 64 bit sign extension bug.
The fields in the td definition were switched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
ips/sext_64_32.ll
|
| 5ac252024180805f455109ab5c7911012378b64b |
08-Aug-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/test/MC/COFF/seh.s: Fixup corresponding to r161487.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161489 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| ef920552d4fb0959097f1c165cfc81c69db19934 |
08-Aug-2012 |
Bill Wendling <isanbard@gmail.com> |
Add `.pushsection', `.popsection', and `.previous' directives to Darwin ASM.
There are situations where inline ASM may want to change the section -- for
instance, to create a variable in the .data section. However, it cannot do this
without (potentially) restoring to the wrong section. E.g.:
asm volatile (".section __DATA, __data\n\t"
".globl _fnord\n\t"
"_fnord: .quad 1f\n\t"
".text\n\t"
"1:" :::);
This may be wrong if this is inlined into a function that has a "section"
attribute. The user should use `.pushsection' and `.popsection' here instead.
The addition of `.previous' is added for completeness.
<rdar://problem/12048387>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161477 91177308-0d34-0410-b5e6-96231b3b80d8
achO/previous.s
achO/pushsection.s
|
| 5b0e9ce2e54726a4b6e2a5008764fe67f3b79c88 |
07-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The define for 64 bit sign extension neglected to
initialize fields of the class that it used.
The result was nonsense code.
Before:
0000000000000000 <foo>:
0: 00441100 0x441100
4: 03e00008 jr ra
8: 00000000 nop
After:
0000000000000000 <foo>:
0: 00041000 sll v0,a0,0x0
4: 03e00008 jr ra
8: 00000000 nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
ips/sext_64_32.ll
|
| 61de70d98e1f752d5482b775f08827f799f4a53b |
07-Aug-2012 |
Jack Carter <jcarter@mips.com> |
The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64
were using a class defined for 32 bit instructions and
thus the instruction was for addiu instead of daddiu.
This was corrected by adding the instruction opcode as a
field in the base class to be filled in by the defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
ips/lea_64.ll
|
| fc54d9e47a1276650f14f38e7d037c9b58c8dc2d |
06-Aug-2012 |
Jack Carter <jcarter@mips.com> |
Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.
These 2 relocations gain access to the
highest and the second highest 16 bits
of a 64 bit object.
R_MIPS_HIGHER %higher(A+S)
The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ].
R_MIPS_HIGHEST %highest(A+S)
The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161348 91177308-0d34-0410-b5e6-96231b3b80d8
ips/higher_highest.ll
|
| 1c3781496081b47412fc70393bcdc5b67b440b02 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Support fpv4 for ARM Cortex-M4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161163 91177308-0d34-0410-b5e6-96231b3b80d8
RM/vfp4.s
|
| fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
isassembler/ARM/thumb2.txt
|
| c1b7ca5ba28ded2d83ae534c8e072c2538d43295 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/thumb2.txt
|
| 1fb27eccf5b7eabde9678d84411eb1df8a693683 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/thumb2.txt
|
| 9714644a38213d059f3ddced08cfc119ca8a0ab7 |
31-Jul-2012 |
Jim Grosbach <grosbach@apple.com> |
Keep empty assembly macro argument values in the middle of the list.
Empty macro arguments at the end of the list should be as-if not specified at
all, but those in the middle of the list need to be kept so as not to screw
up the positional numbering. E.g.:
.macro foo
foo_-bash___:
nop
.endm
foo 1, 2, 3, 4
foo 1, , 3, 4
Should create two labels, "foo_1_2_3_4" and "foo_1__3_4".
rdar://11948769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161002 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-args.s
|
| 5af4de18ef244d2ce52b2f2ac0a703409b6fdfe6 |
30-Jul-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cpp
where the other_half of the movt and movw relocation entries needs to get set
and only with the 16 bits of the other half.
rdar://10038370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160978 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/thumb2-movw-fixup.s
|
| 7f76cb6666194d7269bbd6ee0966eacc709dd10a |
26-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86-32-avx.s
86/x86_64-avx-encoding.s
|
| 75dc33a60b65bbbf2253b0b916df1d36a4da4237 |
18-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
86/intel-syntax.s
86/x86_64-avx-encoding.s
|
| e035f65b16956cdb7ba29e741b7e3c04a8ce4d24 |
16-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Doubleword Shift Left Logical Plus 32
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63
Here is a description of DSLL:
Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits
Description: GPR[rd] <- GPR[rt] << (sa+32)
The 64-bit doubleword contents of GPR rt are shifted left, inserting
zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.
This patch implements the direct object output of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
ips/mips64shift.ll
|
| fd506efec628819f7e6fad8016a9dbb5d8612b8b |
13-Jul-2012 |
Jack Carter <jcarter@mips.com> |
The Mips specific relocation R_MIPS_GOT_DISP
is used in cases where global symbols are
directly represented in the GOT and we use an
offset into the global offset table.
This patch adds direct object support for R_MIPS_GOT_DISP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160183 91177308-0d34-0410-b5e6-96231b3b80d8
ips/r-mips-got-disp.ll
|
| 657c7cb558bcf28dd71456d61100ef19ad5fc08f |
13-Jul-2012 |
Jack Carter <jcarter@mips.com> |
test case for revision 160084: Alignment filling between Mips function units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160177 91177308-0d34-0410-b5e6-96231b3b80d8
ips/multi-64bit-func.ll
|
| 94e36e34e260822bf3249f0a48f400f3d28a4e58 |
12-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
|
| fae96f17b4b022fccd94a143698112a17d8ddf05 |
10-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
isassembler/ARM/neon.txt
|
| 97a0c6bc91bf31fa701dda478d9616c2de6b2393 |
10-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Reverse assembler/disassembler operand order for gather instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
86/x86_64-avx-encoding.s
|
| 270e3625b23174688aa5b6f1e1d0cd42086541de |
09-Jul-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 241b77fa451f8076e47c37212028454ad52ece15 |
09-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Reapply r158846.
Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| 2e7e34ba5485320a84ca69c83d242e24433f7acd |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 8ed97ef5f6980c689a5770ec30488601201e17c3 |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Prevent ARM assembler from losing a right shift by #32 applied to a register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 2b6652fb10d7005e41010b0e0800afe16ae18a34 |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2-narrow-dp.ll
|
| 63d10fbc89c02758cd91e3b53749e55c2bd0cf65 |
06-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
revert r159851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| e32cc0d5456eb7beb4030f0c0205c724a485ff31 |
06-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Reapply r158846.
Include file MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| a101014026be32a27e9d77d01e01ef08eb57e465 |
03-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Add aliases for pblendvb, blendvpd, and blendvps instructions with the implicit xmm0 operand specified. Fixes PR13252.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159644 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
|
| 39ae36337f87b1530c1680ae561c952c827d6e88 |
02-Jul-2012 |
Jack Carter <jcarter@mips.com> |
Pass the correct ELFOSABI enumeration to the MipsELFObjectWriter constructor
Contributer: Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159574 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_basic.s
|
| 1de43ede8904e08de37f601c9bab0b70f71156e1 |
02-Jul-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Fix the remaining TCL-style quotes found in the testsuite. This is
another mechanical change accomplished though the power of terrible Perl
scripts.
I have manually switched some "s to 's to make escaping simpler.
While I started this to fix tests that aren't run in all configurations,
the massive number of tests is due to a really frustrating fragility of
our testing infrastructure: things like 'grep -v', 'not grep', and
'expected failures' can mask broken tests all too easily.
Essentially, I'm deeply disturbed that I can change the testsuite so
radically without causing any change in results for most platforms. =/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159547 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDR_POST-arm.txt
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/invalid-VQADD-arm.txt
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
isassembler/ARM/invalid-t2LDREXD-thumb.txt
isassembler/ARM/invalid-t2STRD_PRE-thumb.txt
isassembler/ARM/invalid-t2STREXB-thumb.txt
|
| 49589f0d0e35f643e697ab7ae8a51a530d38b0d8 |
02-Jul-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Convert the uses of '|&' to use '2>&1 |' instead, which works on old
versions of Bash. In addition, I can back out the change to the lit
built-in shell test runner to support this.
This should fix the majority of fallout on Darwin, but I suspect there
will be a few straggling issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159544 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/purgem.s
isassembler/ARM/invalid-BFI-arm.txt
isassembler/ARM/invalid-Bcc-thumb.txt
isassembler/ARM/invalid-CPS2p-arm.txt
isassembler/ARM/invalid-CPS3p-arm.txt
isassembler/ARM/invalid-DMB-thumb.txt
isassembler/ARM/invalid-DSB-arm.txt
isassembler/ARM/invalid-IT-CBNZ-thumb.txt
isassembler/ARM/invalid-IT-CC15.txt
isassembler/ARM/invalid-IT-thumb.txt
isassembler/ARM/invalid-LDC-form-arm.txt
isassembler/ARM/invalid-LDM-thumb.txt
isassembler/ARM/invalid-LDRB_POST-arm.txt
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
isassembler/ARM/invalid-LDR_POST-arm.txt
isassembler/ARM/invalid-LDR_PRE-arm.txt
isassembler/ARM/invalid-LDRrs-arm.txt
isassembler/ARM/invalid-MCR-arm.txt
isassembler/ARM/invalid-MOVTi16-arm.txt
isassembler/ARM/invalid-MOVr-arm.txt
isassembler/ARM/invalid-MOVs-LSL-arm.txt
isassembler/ARM/invalid-MOVs-arm.txt
isassembler/ARM/invalid-MRRC2-arm.txt
isassembler/ARM/invalid-MSRi-arm.txt
isassembler/ARM/invalid-RFEorLDMIA-arm.txt
isassembler/ARM/invalid-SBFX-arm.txt
isassembler/ARM/invalid-SMLAD-arm.txt
isassembler/ARM/invalid-SRS-arm.txt
isassembler/ARM/invalid-STMIA_UPD-thumb.txt
isassembler/ARM/invalid-SXTB-arm.txt
isassembler/ARM/invalid-UMAAL-arm.txt
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
isassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
isassembler/ARM/invalid-VQADD-arm.txt
isassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
isassembler/ARM/invalid-t2Bcc-thumb.txt
isassembler/ARM/invalid-t2LDRBT-thumb.txt
isassembler/ARM/invalid-t2LDREXD-thumb.txt
isassembler/ARM/invalid-t2LDRSHi12-thumb.txt
isassembler/ARM/invalid-t2LDRSHi8-thumb.txt
isassembler/ARM/invalid-t2PUSH-thumb.txt
isassembler/ARM/invalid-t2STRD_PRE-thumb.txt
isassembler/ARM/invalid-t2STREXB-thumb.txt
isassembler/ARM/invalid-t2STREXD-thumb.txt
isassembler/ARM/invalid-t2STR_POST-thumb.txt
isassembler/ARM/ldrd-armv4.txt
isassembler/ARM/unpredictable-ADC-arm.txt
isassembler/ARM/unpredictable-ADDREXT3-arm.txt
isassembler/ARM/unpredictable-AExtI-arm.txt
isassembler/ARM/unpredictable-AI1cmp-arm.txt
isassembler/ARM/unpredictable-LDR-arm.txt
isassembler/ARM/unpredictable-LDRD-arm.txt
isassembler/ARM/unpredictable-LSL-regform.txt
isassembler/ARM/unpredictable-MRRC2-arm.txt
isassembler/ARM/unpredictable-MRS-arm.txt
isassembler/ARM/unpredictable-MUL-arm.txt
isassembler/ARM/unpredictable-RSC-arm.txt
isassembler/ARM/unpredictable-SEL-arm.txt
isassembler/ARM/unpredictable-SHADD16-arm.txt
isassembler/ARM/unpredictable-SSAT-arm.txt
isassembler/ARM/unpredictable-STRBrs-arm.txt
isassembler/ARM/unpredictable-UQADD8-arm.txt
isassembler/ARM/unpredictable-swp-arm.txt
isassembler/ARM/unpredictables-thumb.txt
isassembler/X86/enhanced.txt
isassembler/X86/invalid-VEX-vvvv.txt
isassembler/X86/invalid-cmp-imm.txt
isassembler/X86/truncated-input.txt
|
| 4177e6fff50552908bab510f1e896fa974a6f155 |
02-Jul-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Convert all tests using TCL-style quoting to use shell-style quoting.
This was done through the aid of a terrible Perl creation. I will not
paste any of the horrors here. Suffice to say, it require multiple
staged rounds of replacements, state carried between, and a few
nested-construct-parsing hacks that I'm not proud of. It happens, by
luck, to be able to deal with all the TCL-quoting patterns in evidence
in the LLVM test suite.
If anyone is maintaining large out-of-tree test trees, feel free to poke
me and I'll send you the steps I used to convert things, as well as
answer any painful questions etc. IRC works best for this type of thing
I find.
Once converted, switch the LLVM lit config to use ShTests the same as
Clang. In addition to being able to delete large amounts of Python code
from 'lit', this will also simplify the entire test suite and some of
lit's architecture.
Finally, the test suite runs 33% faster on Linux now. ;]
For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159525 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-BFI-arm.txt
isassembler/ARM/invalid-Bcc-thumb.txt
isassembler/ARM/invalid-CPS2p-arm.txt
isassembler/ARM/invalid-CPS3p-arm.txt
isassembler/ARM/invalid-DMB-thumb.txt
isassembler/ARM/invalid-DSB-arm.txt
isassembler/ARM/invalid-IT-CBNZ-thumb.txt
isassembler/ARM/invalid-IT-thumb.txt
isassembler/ARM/invalid-LDC-form-arm.txt
isassembler/ARM/invalid-LDM-thumb.txt
isassembler/ARM/invalid-LDRB_POST-arm.txt
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
isassembler/ARM/invalid-LDR_PRE-arm.txt
isassembler/ARM/invalid-LDRrs-arm.txt
isassembler/ARM/invalid-MCR-arm.txt
isassembler/ARM/invalid-MOVTi16-arm.txt
isassembler/ARM/invalid-MOVr-arm.txt
isassembler/ARM/invalid-MOVs-LSL-arm.txt
isassembler/ARM/invalid-MOVs-arm.txt
isassembler/ARM/invalid-MSRi-arm.txt
isassembler/ARM/invalid-RFEorLDMIA-arm.txt
isassembler/ARM/invalid-SBFX-arm.txt
isassembler/ARM/invalid-SMLAD-arm.txt
isassembler/ARM/invalid-SRS-arm.txt
isassembler/ARM/invalid-STMIA_UPD-thumb.txt
isassembler/ARM/invalid-SXTB-arm.txt
isassembler/ARM/invalid-UMAAL-arm.txt
isassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
isassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
isassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
isassembler/ARM/invalid-t2Bcc-thumb.txt
isassembler/ARM/invalid-t2LDRBT-thumb.txt
isassembler/ARM/invalid-t2LDRSHi12-thumb.txt
isassembler/ARM/invalid-t2LDRSHi8-thumb.txt
isassembler/ARM/invalid-t2PUSH-thumb.txt
isassembler/ARM/invalid-t2STREXD-thumb.txt
isassembler/ARM/invalid-t2STR_POST-thumb.txt
isassembler/X86/invalid-VEX-vvvv.txt
isassembler/X86/invalid-cmp-imm.txt
|
| 40307c7dbe2d104784763c28697d7926793674af |
29-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add more GATHER intrinsics in LLVM
Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
86/x86_64-avx-encoding.s
|
| a6d6ef6dac9407840aadf1e657ba58989946173e |
28-Jun-2012 |
Jack Carter <jcarter@mips.com> |
This allows hello world to be compiled for Mips 64 direct object.
It takes advantage of r159299 which introduces relocation support for N64.
elf-dump needed to be upgraded to support N64 relocations as well.
This passes make check.
Jack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159302 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-N64.ll
|
| 4acefe192f02849bcb2fd620a9f507c00d39a686 |
27-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Teach assembler to handle capitalised operation values for DSB instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159259 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 1f7a1b68a07ea6bdf521525a7928f4a8c5216713 |
26-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add GATHER intrinsics (AVX2) in LLVM
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
86/x86_64-avx-encoding.s
|
| 952caee4f66a968f54588cca48215a5008283ea3 |
26-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-avx.s
86/x86_64-avx-encoding.s
|
| b935cd15142491bdee9baff00db8d63c18d402db |
25-Jun-2012 |
Meador Inge <meadori@codesourcery.com> |
PR13013: ELF Type identification fails for MSB type ELF files.
Fix 'sys::IdentifyFileType' to work with big and little endian byte orderings
when reading the ELF object file type.
Initial patch by Stefan Hepp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159138 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-objdump.s
|
| 70c9bf3c1a77b5707c92a7cfe74104c320480391 |
23-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a better diagnostic for some out of range immediates.
As an example of how the custom DiagnosticType can be used to provide
better operand-mismatch diagnostics, add a custom diagnostic for
the imm0_15 operand class used for several system instructions.
Update the tests to expect the improved diagnostic.
rdar://8987109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159051 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
RM/thumb2-diagnostics.s
|
| 02a227af91889d39f5e811e2e27ecce8144499eb |
20-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r158846.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| b66510f309077d9f616462a1696f712236ce5a22 |
20-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
In MipsDisassembler.cpp, instead of defining register class tables, use the ones
that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
|
| c9a4e269d00dc9e2ba0c7b77721fa54cfb5a59fa |
19-Jun-2012 |
Jan Wen Voung <jvoung@google.com> |
Have ARM ELF use correct reloc for "b" instr.
The condition code didn't actually matter for arm "b" instructions,
unlike "bl". It should just use the R_ARM_JUMP24 reloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158722 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-condcall.s
|
| 7e99a60857532ca2973cf9dabc790d84a2e15a8a |
18-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Define generic HINT instruction.
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.
rdar://11600518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| fc9216eb5a437719b3a53d88d79833a8abc93fee |
16-Jun-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement irpc. Extracted from a patch by the PaX team. I just added the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158604 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-irpc.s
|
| f49a4092bcf679d1634a8023efc593e98a3e5663 |
16-Jun-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2-mclass.s
|
| aa7a2f2ba308656e206338fe65c422e0b6781c64 |
15-Jun-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Factor macro argument parsing into helper methods and add support for .irp.
Patch extracted from a larger one by the PaX team. I added the testcases
and tightened error handling a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158523 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-err1.s
smParser/macro-irp.s
|
| a1c7367a5bed459acc88e3ea2a482b4b5dac942a |
14-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Replace assertion failure for badly formatted CPS instrution with error message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158445 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| c8f2fcc9a381f1e024656568f2face2f600e0328 |
06-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Correct decoder for T1 conditional B encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| f6a186ed0bd3fecf1a7cd506574a8b219e5d55b9 |
31-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157725 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/lit.local.cfg
|
| 1386e9b7b16a8138ae7060c2dbb8b029f7c4fce2 |
29-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
isassembler/X86/x86-64.txt
86/x86_64-sse4a.s
|
| 3e96531186ba574b0c25a4be62d24b8b7d752c9f |
18-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Refactor data-in-code annotations.
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.
Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.
data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"
The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.
rdar://11459456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
achO/ARM/data-in-code.s
|
| 59c15e920c9873804f3150d0c13357696f09e300 |
18-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed a bug in llvm-objdump when disassembling using -macho option for a binary
containing no symbols. Fixed the crash and fixed it not disassembling anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157031 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/llvm-objdump-macho-stripped.s
|
| 0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe |
18-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2-mclass.s
|
| e545c4e45d989bcb3e6d18e090f417fd41fb9c63 |
15-May-2012 |
Kevin Enderby <enderby@apple.com> |
Add a test case for r156840, a fix to llvm-objdump when disassembling using
-macho to disassemble the last symbol to the end of the section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156850 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/llvm-objdump-macho.s
|
| 2ec304c0bf308c5c304412c56ca8f6d69c0b94fc |
12-May-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the .rept directive. Patch by Vladmir Sorokin. I added support
for nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156714 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-rept-err1.s
smParser/macro-rept-err2.s
smParser/macro-rept.s
|
| 6a80f9da8c2cb2cbf931ec8cf2a72b5f288c1bc6 |
12-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
ELF: Add support for the asm .version directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156712 91177308-0d34-0410-b5e6-96231b3b80d8
LF/version.s
|
| bc3b27ccd964df7627ecff4a62715ff72f1c4a7f |
12-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
AsmParser: Add support for the .purgem directive.
Based on a patch by Team PaX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156709 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/purgem.s
|
| e14a3c5084838b40bca4b006cbf78500c874a043 |
12-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
AsmParser: ignore the .extern directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156707 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/extern.s
|
| dec06ef43114ca0f7e5a616ca7437be6e98ea0b3 |
12-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
AsmParser: Add support for .ifc and .ifnc directives.
Based on a patch from PaX Team.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156706 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ifc.s
|
| a3dd0eb93c764905dac919851bca12517e7e8757 |
12-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
AsmParser: Add support for .ifb and .ifnb directives.
Based on a patch from PaX Team.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156705 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ifb.s
|
| 4147e4d054b62eb2ea8259db0385791ec23c460b |
12-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make the following changes in MipsAsmPrinter.cpp:
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156689 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-bigendian.ll
|
| 27ba61df9f9decc70124b7559f777ad596dfda29 |
12-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Insert instructions to the entry basic block which initializes the global
pointer register.
This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:
- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
allocator decide which register to assign to it or whether spill/reloads are
needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156671 91177308-0d34-0410-b5e6-96231b3b80d8
ips/sym-offset.ll
|
| 169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23 |
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-AExtI-arm.txt
isassembler/ARM/unpredictable-SEL-arm.txt
|
| ca3cd419a52c1dedee133d79772ef97f30e5d20b |
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 2d524b0765145f1c7888166c985a25452f16b2bc |
04-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
isassembler/ARM/thumb-tests.txt
achO/ARM/thumb-bl-jbits.s
|
| b422d0b65e15435b6aef4a92f5663db9ec6659d4 |
03-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed disassembler for vstm/vldm ARM VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/fp-encoding.txt
|
| 2727930ab4ce260fef0487bc878c1cd4c3769cef |
02-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add missing two-operand VBIC aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| 0a552d611efe9d1070aff1d35c7f169dd1ab0be7 |
02-May-2012 |
Richard Barton <richard.barton@arm.com> |
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
RM/thumb.s
isassembler/ARM/thumb1.txt
|
| 54319e2a8c22e7ee7044e398fbd8d4287e2b7c4f |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
adds.w r2, #-16
adds.w r2, r2, #-16
addw r2, #-16
addw r2, #-16
addw r2, r2, #-16
rdar://11330769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 94b590f8faf4dbba406f263e6a839882b0c68a94 |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.
rdar://10550147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_fixups.s
|
| 686c01854e49748ef2e23851bd0abfa8b9b414f3 |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
MC: Unknown assembler directives are now hard errors.
Previously, an unsupported/unknown assembler directive issued a warning.
That's generally unsafe, and inconsistent with the behaviour of pretty
much every system assembler. Now that the MC assemblers are mature
enough to be the default on multiple targets, it's reasonable to
issue errors for these.
For target or platform directives that need to stay warnings, we
should add explicit handlers for them in, e.g., ELFAsmParser.cpp,
DarwinAsmParser.cpp, et. al., and issue the warning there.
rdar://9246275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155926 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros-parsing.s
smParser/macros.s
|
| a9cc08f24f61e2663a131d7ac16c329b75162e7b |
28-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.
rdar://11219154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb-diagnostics.s
|
| 04a09a461beb4ec629fe53e601b7665547ac35c3 |
27-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Fix ARM assembly parsing for upper case condition codes on IT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 71275b129b3d085af239b3a00899b63f8c2988a8 |
27-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Missed some register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155706 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/enhanced.txt
|
| a356e9414c0ce591dee07af1b7ca8f2b894e5d87 |
27-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Update edis test for r155704.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155705 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/enhanced.txt
|
| cac31de146e7131f411715dc6cb1958ea59bd754 |
26-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Specify cpu to unbreak tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
RM/neont2-absdiff-encoding.s
RM/neont2-dup-encoding.s
RM/vpush-vpop.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/fp-encoding.txt
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/invalid-VQADD-arm.txt
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
isassembler/ARM/neon-tests.txt
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
isassembler/ARM/thumb-tests.txt
isassembler/ARM/thumb2.txt
|
| 14ce6fac242228dacc5c08040e544141a96880e5 |
25-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://11257547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| 24e767d076cb17838c2c13cabe9d275bea34a6d8 |
24-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| 2c66edf434f136d78e4b311a5a4777d8ecc9635b |
24-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| c34954d432cce4bf09d30b3ec13e46d577909fa7 |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155391 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shiftaccum-encoding.s
RM/neont2-shiftaccum-encoding.s
|
| 10a3933c5f03e331b1d3912c0f0eb37bacb152ca |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode tests for the NEON vector shift-accumulate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155390 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shiftaccum-encoding.s
|
| 2b8525068a9b90760d9286a2f4802470b844303d |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Reformat for ease of reading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155389 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-shiftaccum-encoding.s
|
| d8b3ed8f25c1ba76a6db875cd2d6eaa016bd4646 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Update NEON assembly two-operand aliases.
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
RM/neon-sub-encoding.s
|
| 181b14797518e714e1b6112db849ca53192b8f23 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM some VFP tblgen'erated two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| bfb3c5a50c0c01073658ec9d3504532c6eeb2115 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155177 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for disassembling unpredictable swp/swpb ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-swp-arm.txt
|
| 6b9f97dd892b0d61d8a1f0ee4f837058f2ca4552 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-MRS-arm.txt
|
| fa1ebc6abe95b79b7f82030eea53586a8704eb7e |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MRRC2-arm.txt
isassembler/ARM/unpredictable-MRRC2-arm.txt
|
| e546c4c9c3004274c8e275e8303ca078b794bf28 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 9e71231309e8924b89aa94ca86cae883db1d2916 |
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-AI1cmp-arm.txt
|
| ecdc9d5bb26936a68060f1238abc6c1d6b3c2a01 |
17-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add disassembler to MIPS.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
|
| c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1 |
17-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| bf42f24e6e2347fbd28abb9d442a6cd9d95fcc3b |
17-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand forms for vhadd and vhsub instructions.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-add-encoding.s
RM/neon-sub-encoding.s
|
| 68f89a61587e8d482347cf892c2670a869a1ad61 |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
MC assembly parser handling for trailing comma in macro instantiation.
A trailing comma means no argument at all (i.e., as if the comma were not
present), not an empty argument to the invokee.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154863 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-args.s
|
| 1fbfea7b06928efe822b12a1d1d0af01fe2f50d1 |
16-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
This patch fixes 3 problems:
1. CHECKNEXT was used instead of CHECK-NEXT which caused the line to be
ignored which in turn hid the next 2 problems:
2. ('sh_offset', 0x{{{[0-9,a-f]+}}) had one too many leading curly braces and
failed to do it's job of accepting all hex digits and:
3. The check for the hex values for the code instructions didn't account for
blank separators.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154842 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-bigendian.ll
|
| 199366a6a6b59717cd1b98d8d5df521e3981de19 |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly two-operand forms for VRSHL.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 695eca66b1b7b429f2b3d2ae1d583a426cb9c227 |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Test formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154839 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 3ef7edc77ace78ba6382adb63c1ac03326d4a615 |
16-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Do not add offset in applyFixup. This has already been accounted for in Value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154838 91177308-0d34-0410-b5e6-96231b3b80d8
ips/sym-offset.ll
|
| 705e2572b442c34d65a3b667e008327b50bac06b |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VRHADD instructions.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-add-encoding.s
|
| dbd6ba36e44d822054574f2013809e0f027853dd |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Testcase formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154831 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-add-encoding.s
|
| d0c478d95f440b4db76279fe47d6cf734a28fa9a |
16-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Add -disassemble support for -show-inst and -show-encode capability llvm-mc. Also refactor so all MC paraphernalia are created once for all uses as much as possible.
The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154809 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
|
| b318cc16c9e959adb96294b3aa4940e74f68dde3 |
12-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
|
| 1835547ec195c35b3a59bf834f4df942c61a5c53 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VUZP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.
rdar://11222366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.s
|
| 6073b30b053da2c2ac6150dd67cecb304bc614f1 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VZIP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.
rdar://11221911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.s
|
| bee78fe5fcd8464f58bc729dede1a87d763ac3ae |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?
rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
RM/vfp4.s
|
| 0d82fe77f2b6f48b5fab131c1671169d154f8c69 |
11-Apr-2012 |
Charles Davis <cdavis@mines.edu> |
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
ret instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
86/intel-syntax-encoding.s
86/x86-32.s
86/x86-64.s
|
| a69da35c127dd7e35ae6216d965670643dc55bb6 |
11-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VLD instructions with writebacks. Â And add test a case
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| a5378ebe7890aa9a4974f2872aa6632f1b7f2400 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
rdar://11222742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 82509e5c62a99912c636b22e227b810eaf6eda78 |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a number of problems with ARM fused multiply add/subtract instructions.
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
RM/vfp4.s
isassembler/ARM/vfp4.txt
|
| a23ecc2ba945c9685a76552276e5f6f41859b4ab |
10-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix cc_out operand handling for t2SUBrr instructions.
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.
rdar://11216577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e45cddfa08992ccac052b344f52c92d66e4797ea |
06-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add the tests that were supposed to go with r153935 that I forgot svn add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154165 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/invalid-cmp-imm.txt
isassembler/X86/x86-64.txt
|
| 4e53fe8dc61ad48650ac6fe30d7268ec92b7fc1a |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for add negative immediates using sub.
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.
rdar://11192734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 1c01249191ba5d3648e7bedaf8233c41cc103551 |
05-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-ADC-arm.txt
|
| 82e1bba0e4afaf3769fc46819c1601e387ffb56e |
05-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for handling unpredictable arithmetic instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRT-arm.txt
isassembler/ARM/unpredictable-SHADD16-arm.txt
|
| 22378fd664fed97c296878d8d188ab06e2c89395 |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for two-operand V[R]SHR instructions.
rdar://11189467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| b657a90929867716ca1c7c12d442bb5d32281bd4 |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for 'msr' plain 'cpsr' operand.
Plain 'cpsr' is an alias for 'cpsr_fc'.
rdar://11153753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 769bbfd951018f9b36f3d2f0d70a23d81f2d3287 |
03-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
86/x86_64-avx-encoding.s
|
| 9dd16d41a2fb5f7db2e2bd87ee8181159284254c |
03-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
|
| 02365945a62f368c18547da57a4ef3382beb89d0 |
03-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r153924. There were buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
|
| 885020a7a7299c0cfc12f691bc298e0f41d02190 |
03-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS disassembler support.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/Mips/mips32.txt
isassembler/Mips/mips32_le.txt
isassembler/Mips/mips32r2.txt
isassembler/Mips/mips32r2_le.txt
isassembler/Mips/mips64.txt
isassembler/Mips/mips64_le.txt
isassembler/Mips/mips64r2.txt
isassembler/Mips/mips64r2_le.txt
|
| a551a48402385cf3f4b754dc72264b2f0974b1a6 |
02-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Initial 64 bit direct object support.
This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.
The test case checks for both big and little endian flavors.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_basic.s
|
| 50ac2e9229044681b1c060125cf4d0ce1fc44d71 |
02-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/ldrd-armv4.txt
|
| ad353c630359d285018a250d72c80b7022d8e67e |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler should prefer non-aliases encoding of cmp.
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a45e3747e612c00ca4933087d883db77f4547571 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base
class encoding handler expects.
rdar://11157236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vswp.s
|
| 2d30d947ec2626e8b1a9b577cdfa4121f476c3f5 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM integrated assembler should encoding choice for add/sub imm.
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.
rdar://11156277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| c0164f86080bc9d7a41fd5eabd0d6556396f5b38 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing needs to be paranoid about negative immediates.
Make sure to treat immediates as unsigned when doing relative comparisons.
rdar://11153621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| cb0809b82b126e79b99755ae4fc3d9733faea038 |
30-Mar-2012 |
James Molloy <james.molloy@arm.com> |
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_fixups.s
RM/basic-arm-instructions.s
RM/elf-reloc-condcall.s
|
| b22e70d835a88753d3ec6d5ee5e85b23fa6834b1 |
29-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 6e9d66c756a3d3f0d1636a9f1143dedd2f58138b |
28-Mar-2012 |
Richard Barton <richard.barton@arm.com> |
Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| cc85160672e3b2d5ec363cc4e151e5b944a60454 |
25-Mar-2012 |
Eli Bendersky <eli.bendersky@intel.com> |
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
RM/lit.local.cfg
smParser/lit.local.cfg
OFF/lit.local.cfg
isassembler/ARM/lit.local.cfg
isassembler/MBlaze/lit.local.cfg
isassembler/X86/lit.local.cfg
LF/lit.local.cfg
Blaze/lit.local.cfg
achO/ARM/lit.local.cfg
achO/lit.local.cfg
ips/lit.local.cfg
|
| 6fe310e1555dedba2b36dedae9a88eb900ad1804 |
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-LDRD-arm.txt
isassembler/ARM/unpredictable-ADDREXT3-arm.txt
isassembler/ARM/unpredictable-LDRD-arm.txt
|
| b7c2ed66642b141a768b3074c465eba9d98665d8 |
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-LDR-arm.txt
|
| a0c48eb8f69bcb619a2c2cc0044375bb4171cebe |
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictable-MUL-arm.txt
|
| f0586f08dfd5bf1889c15849e9c603b3985fce4a |
21-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| 4fd3d292753bd8232a76d5ac6b107f5899e5bfaa |
21-Mar-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Fix generation of the address size override prefix. Add assertions for
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
86/address-size.s
|
| fb54afbcb8f460c5c4cafa605259ba0dd77504dc |
21-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Incremental big endian patch by Jack Carter.
These changes allow us to compile big endian from the command line for 32 bit
Mips targets. This patch will result in code and data actually being produced
in the correct endianess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153153 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-bigendian.ll
|
| 48c9533181ec7ef24e49a4f5bca9151dc6886bad |
20-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Assembler should accept redefinitions of unused variable symbols.
rdar://11027851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153137 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/variables-invalid.s
|
| 9f2e160f7ae90a7a80b17e38ad06f2c706515115 |
20-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix assembling ARM vst2 instructions with double-spaced registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
RM/neont2-vst-encoding.s
|
| 07cdd80ccc1a07edc565199c62d35ea0d80c6c1c |
20-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM non-scattered MachO relocations for movw/movt.
Needed when building -mdynamic-no-pic code.
rdar://10459256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153097 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/static-movt-relocs.s
|
| 5c062ad92672f22e61a4b20a9954af3db3b72bd6 |
20-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LSL-regform.txt
isassembler/ARM/invalid-RSC-arm.txt
isassembler/ARM/invalid-SSAT-arm.txt
isassembler/ARM/invalid-STRBrs-arm.txt
isassembler/ARM/invalid-UQADD8-arm.txt
isassembler/ARM/unpredictable-LSL-regform.txt
isassembler/ARM/unpredictable-RSC-arm.txt
isassembler/ARM/unpredictable-SSAT-arm.txt
isassembler/ARM/unpredictable-STRBrs-arm.txt
isassembler/ARM/unpredictable-UQADD8-arm.txt
|
| ae151ed87d4100ec352fee8fc70e2c8c26281c69 |
17-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
MC asm parser macro argument count was wrong when empty.
evaluated to '1' when the argument list was empty (should be '0').
rdar://11057257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152967 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-args.s
|
| be7cf2b377d987f46d10f54f89ae4e1a71c37f55 |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM ldm/stm register lists can be out of order.
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| 213d2e7dc31bef3ceeef0cefa703cb4ce52de51a |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM optional operand on MRC/MCR assembly instructions.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 9426ac7b575de9e1297a01f27307d858343ac4ed |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vmrs system registers mvfr0 and mvfr1 handling.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| b84ad4aa7dacfba5337520740d47770f2200201c |
15-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM case-insensitive checking for APSR_nzcv.
rdar://11056591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 8a6bcc3722729803a16b5885de1ff85a3752e6a0 |
15-Mar-2012 |
Kristof Beyls <kristof.beyls@arm.com> |
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 0f5ab7c5f392d8207a4b0c5bf1f8b274a9f410df |
13-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Change the X86 assembler to not require a segment register on string
instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 8b1527896455812b83615e23a753c6181f977159 |
12-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Change the second line of the test added for r152414 to use CHECK-NEXT.
Suggestion by Bill Wendling!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152582 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 84faf659125cb354794e457fa5a8a8daad84760d |
12-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Added a missing error check for X86 assembly with mismatched base and index
registers not both being 64-bit or both being 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_errors.s
|
| e060eb8916820fb7a2035dd14c848aa1fd545efe |
10-Mar-2012 |
Bill Wendling <isanbard@gmail.com> |
Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.
Patch by Kay Tiong Khoo!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
|
| 58dfaa14651f36fc9fce2031eb011e65ae267b9f |
09-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Add the missing call to Error when a bad X86 scale expression is parsed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152443 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_errors.s
|
| faf72ffda3bf83b08769428129ee4755787ee6cf |
09-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the x86 disassembler to at least print the lock prefix if it is the first
prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 63054f99af1fd013322e8081227b29656d49a2d2 |
09-Mar-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152406 91177308-0d34-0410-b5e6-96231b3b80d8
86/lit.local.cfg
|
| 6507d84d6cf078fdbb398dcc6d3e70e89ed94b96 |
07-Mar-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use llvm-mc instead of llc. Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152242 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_basic.s
|
| 54427e52197ecd8c748736d7bbb431f2bf65c90e |
06-Mar-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 158c8a49c23d01297e7913c03c1fdb0760aee3a8 |
06-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| bc978a60d90a06b2d879b6f4db22b3760168df7f |
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
rdar://10988114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
RM/vpush-vpop.s
|
| ec93b6decad4b95fd8a9531dc024b2b1881019bf |
05-Mar-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Make aliases for shld and shrd match gas. PR12173.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| b0578512c79134136e8b53c62a8677ab8e600be2 |
01-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
runs into the undefined 15 condition code value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-IT-CC15.txt
|
| 562a67db329b7867dac50ccad9ca19c5554a3d9e |
01-Mar-2012 |
Richard Trieu <rtrieu@google.com> |
Fix flags for test in MC/MachO/ARM/empty-function-nop.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151778 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/empty-function-nop.ll
|
| c01810eeb7227010f73cb39e3c4fa0197a3c4ef0 |
29-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM implement TargetInstrInfo::getNoopForMachoTarget()
Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.
For example,
define internal fastcc void @empty_function() {
unreachable
}
rdar://10947471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/empty-function-nop.ll
|
| c46255a32ec92c427e621b6d7eabd887962ce4a4 |
29-Feb-2012 |
David Meyer <pdox@google.com> |
In the ObjectFile interface, replace isInternal(), isAbsolute(), isGlobal(), and isWeak(), with a bitset of flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151670 91177308-0d34-0410-b5e6-96231b3b80d8
LF/many-section.s
|
| 489d67927172941bf59b9f4829ab8910814fea24 |
28-Feb-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
On ELF, create relocations to the abbreviation and line sections when producing
debug info for assembly files. We were already doing the right thing when
producing debug info for C/C++.
ELF linkers don't know dwarf, so they depend on these relocations to produce
valid dwarf output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151655 91177308-0d34-0410-b5e6-96231b3b80d8
LF/gen-dwarf.s
|
| 7b25ecf6adbf3c4709c48033acfeb6ebbb4452ab |
27-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_fixups.s
RM/basic-arm-instructions.s
|
| 930a1ebd929aa0ab4c2610e7f7a721c18dcfe052 |
27-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 32d22ee11dc03a69ef22b0794e301cd32176019d |
23-Feb-2012 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Emit global ctors into .CRT$XCU instead of .ctors on Win32. Patch by Joe Groff!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151289 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/global_ctors.ll
|
| b80d571ea85db5d52fafed0523cf59e693502198 |
23-Feb-2012 |
Kevin Enderby <enderby@apple.com> |
Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| 28a713b20ad17f9a02d4677d8a2fea0edb208418 |
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add vmfunc instruction to X86 assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86-32-coverage.s
86/x86-32.s
|
| 9e3d0b335111b2df73984a6cfd9ef1cd5d323872 |
18-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86-32-coverage.s
86/x86-32.s
|
| 0f0c411079cd21bb3a81a1b70bf8c67539a16c22 |
16-Feb-2012 |
Eli Bendersky <eli.bendersky@intel.com> |
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
RM/dg.exp
RM/lit.local.cfg
smParser/dg.exp
smParser/lit.local.cfg
OFF/dg.exp
OFF/lit.local.cfg
isassembler/ARM/dg.exp
isassembler/ARM/lit.local.cfg
isassembler/MBlaze/dg.exp
isassembler/MBlaze/lit.local.cfg
isassembler/X86/dg.exp
isassembler/X86/lit.local.cfg
LF/dg.exp
LF/lit.local.cfg
Blaze/dg.exp
Blaze/lit.local.cfg
achO/ARM/dg.exp
achO/ARM/lit.local.cfg
achO/dg.exp
achO/lit.local.cfg
ips/dg.exp
ips/lit.local.cfg
86/dg.exp
86/lit.local.cfg
|
| 5f7692604d44192206fbaf390085a95c9fb1a40b |
15-Feb-2012 |
David Meyer <pdox@google.com> |
For ELF, also call fixSymbolsInTLSFixups() on expressions passed to EmitValue (literal values). Previously only called on expressions in instructions. New test cases added to tls.s, tls-i386.s. Resolves PR11981.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150582 91177308-0d34-0410-b5e6-96231b3b80d8
LF/tls-i386.s
LF/tls.s
|
| 3015dfb7d739f4cc0b1408555889ecea880ffac9 |
09-Feb-2012 |
James Molloy <james.molloy@arm.com> |
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/unpredictables-thumb.txt
|
| d49b2a7a9d927bb8c314a8c66f7f2e5f3aef4ffd |
01-Feb-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed a crash in llvm-mc for Mach-O when a symbol difference expression uses a
symbol from an assignment. In this case the symbol did not have a fragment so
MCObjectWriter::IsSymbolRefDifferenceFullyResolved() should not have been
calling IsSymbolRefDifferenceFullyResolvedImpl() with a NULL fragment and should
just have returned false in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149442 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-diff-reloc-assign.s
|
| 885f65b4a1c1ec80cd800a0617c57a2289472165 |
30-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| be3e310d5ed8717f070acc71b0f4dae28cb08c4d |
30-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax. Support .intel_syntax directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-2.s
|
| 2d8955a77c6920d1a50de5ec9094faaa1b2f4e88 |
28-Jan-2012 |
James Molloy <james.molloy@arm.com> |
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
Fixes PR11877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
RM/pr11877.s
ips/pr11877.s
|
| 8b01c82f25aaea12340f53789ba59a2527713b9e |
28-Jan-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Small improvement to the recursion detection logic from the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149175 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/variables-invalid.s
|
| e71cc86ad10143173195182f28bf90844f682436 |
28-Jan-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle recursive variable definitions directly. This gives us better error
messages and allows us to fix PR11865.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149174 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/pr11865.s
smParser/variables-invalid.s
|
| a28101e61aa3aeed5baf3d5b91d0f8bcb4e9e12a |
27-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 34982576a43887e7f062ed0a3571af2cbab003f3 |
26-Jan-2012 |
James Molloy <james.molloy@arm.com> |
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
RM/cxx-global-constructor.ll
|
| 74423e32ce7f426b624bfb0c31481bcf6a36394d |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assemly parsing and validation of IT instruction.
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-it-block.s
|
| a57a36abe7d0b769a495ed886246db157aff4add |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 5e59f7e15ed3770b32481cd72d2c15b159e991e6 |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| c389af94b66d0c5a917f81617bd07ff0864790a0 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM Darwin symbol ref differences w/o subsection-via-symbols.
When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148865 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/no-subsections-reloc.s
|
| 3b96e1fe3b695e6d845668ea90d75016f0f46a17 |
24-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| 88a54de799240d5de2e79dfff4671ad5653e7ceb |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| e983a134e7e40e214f590c3d8ba565bb85f39628 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 1ac2060678edd88726e06ff19c9468211b41fc37 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSRA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 5d9bad40980c0b605f9d69bfa1374292f874a3d7 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148820 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shiftaccum-encoding.s
|
| 5e497d39927d2ddf6bf6adbfac39fe9102a1a305 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| d8ee0cc4e8b67f9d85d08bd55e53ac14c5ca533d |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 28f1f9100f33388f9f439c16051185a2cd0e9388 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148817 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 539aab771fea06bd230789e19c9672ef80ad1c7e |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| 8abe7e33641fccfa70a7e335939e83dfbf654fe8 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 4adb18234278d6d40e5791e0dd6970be9a4b0b57 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST3(single element from one lane) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| d7433e2873706265d545edc5cdd0a728dd71ef66 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| c387fc66bd52e4276fdc2704a3aaed57cc1f9a11 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
RM/neon-vst-encoding.s
|
| f2d213745e07e884c1616f2f3d0b78f9e918e5db |
23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify parsing of memory operand's displacement experssion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 3a678af71dec76a7e1474ad85a99b3588516906d |
23-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3 lane-indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| 16d7d437e03ce87fdaef7971919302920d54a966 |
23-Jan-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .cfi_signal_frame. Fixes pr11762.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148733 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-signal-frame.s
|
| 3e08131185d5b3245065eb027900aed56b607970 |
23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 8b31f95bdde1e3809a1c9fdb6926b1840effcf9c |
23-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| 7c64fe651ad4581ac66b6407116144442a8a7f03 |
23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 1aea430b8834f7bed3a14eda5027eac2133d6496 |
20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify register parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| fdd3b30151bc391efce74f4592a9a3bb595565a2 |
20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse ... PTR [-8]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| cf0e269d16f3d784b428c9b1b1e22d1f9e8bb91d |
20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| 51222d1551383dd7b95ba356b1a5ed89df69e789 |
20-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| a951f77ca31b43551bd41765504519d6d76e6cbf |
19-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Post process 'and', 'sub' instructions and select better encoding, if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| e60540f380cc9466f3b2f7d17adfd37db137689c |
19-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: There is no need to create unary expr for simple negative displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| ac0f0486022fb1798579c9a550154e839770efa9 |
19-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax-encoding.s
|
| 904b7be27ef12bf3c31a37e97710bd167fe37fda |
19-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Add testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148454 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/thumb2-function-relative-load.s
|
| 0b4c6738868e11ba06047a406f79489cb1db8c5a |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| b8ba13f0096b560ee618512019ca86969a9fa772 |
18-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Process instructions after match to select alternative encoding which may be more desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 256ba4f42a16da2b3ffc757aa7bf191890765580 |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 relaxation for LDR(literal).
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.
rdar://10711829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/relax-thumb-ldr-literal.s
|
| 8b9300b972745a6d89b482cbcd4206c01359f7df |
17-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
MC tweak symbol difference resolution for non-local symbols.
When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.
For example, on ARM:
_foo:
ldr lr, (_foo - 4)
rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148341 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/darwin-ARM-reloc.s
achO/reloc-pcrel-offset.s
achO/reloc-pcrel.s
|
| 283f1fff47db3a483ab94e4b49cc39eb39dd48ea |
17-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148339 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc-pcrel.s
|
| 2f8af1d643cde711b292117e50b30452877432ef |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Fix parser match class to check memory operand size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 6220fea2a877e5cff559ed38e98c59a076ea9825 |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 9a3d293cf3f72b3c0ed5d4474fc5d4d12fd36be2 |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 40bced0306e953c3d0fec19db4c4770b0e3c787e |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Ignore mnemonic aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| d37ad247cc04c2a436e537767ac1aec709901594 |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify memory operand parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 4a5c0fd70e7a2001b682c8972dab6b0127313c8f |
13-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Add new test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.s
|
| 989a6814643dba79d5add649695c0523edafc026 |
12-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Remove test case, as Chris suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148039 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.ll
|
| 21d3c40fb04a8d9d9c44597c662b31569e74ff69 |
12-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Add test case to check intel syntax parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148034 91177308-0d34-0410-b5e6-96231b3b80d8
86/intel-syntax.ll
|
| 8704b7897db5d877970bde2c8d6766488c457b90 |
11-Jan-2012 |
Kevin Enderby <enderby@apple.com> |
The error check for using -g with a .s file already containing dwarf .file
directives was in the wrong place and getting triggered incorectly with a
cpp .file directive. This change fixes that and adds a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147951 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_file-errors.s
|
| 29a17145ad4985df032785cc1b4716fd7875d47b |
11-Jan-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add big endian mips support. Based on a patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147924 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_basic.s
|
| fddf80459747198d2ee33974c90f6137ea29cbd8 |
11-Jan-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add the skeleton of an asm parser for mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147923 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf_basic.s
|
| 38fdb7d9fc40e9f29c3156b6625cac8d91d562e1 |
10-Jan-2012 |
Kevin Enderby <enderby@apple.com> |
Various crash reporting tools have a problem with the dwarf generated for
assembly source when it generates the TAG_subprogram dwarf debug info for
the labels that have nothing between them as in this bit of assembly source:
% cat ZeroLength.s
_func1:
_func2:
nop
One solution would be to not emit the subsequent labels with the same address
and use the next label with a different address or the end of the section for
the AT_high_pc value of the TAG_subprogram.
Turns out in llvm-mc it is not possible in all cases to determine of two
symbols have the same value at the point we put out the TAG_subprogram dwarf
debug info.
So we will have llvm-mc instead of putting out TAG_subprogram's put out
DW_TAG_label's. And the DW_TAG_label does not have a AT_high_pc value which
avoids the problem.
This commit is only the functional change to make the diffs clear as to what is
really being changed. The next commit will be to clean up the names of such
things like MCGenDwarfSubprogramEntry to something like MCGenDwarfLabelEntry.
rdar://10666925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147860 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf.s
|
| 99b4237c1647156f0e1d3d7e03efdab23ed79778 |
07-Jan-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Split Finish into Finish and FinishImpl to have a common place to do end of
file error checking. Use that to error on an unfinished cfi_startproc.
The error is not nice, but is already better than a segmentation fault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147717 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/cfi-unfinished-frame.s
|
| 06f554d06ab0f9390d04bcbaabb76f572d940249 |
30-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| e6a3a2990e3f783c906e9db58e55439cb06f9fa5 |
30-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Add FMA4 instructions to disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| ed23bdb65fe86cdb7a38c8c1998ec965e6973966 |
29-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement cfi_restore. Patch by Brian Anderson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147356 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-restore.s
|
| 1604ccfc01f1151537350c07bcbce0f9816b57c4 |
29-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 6f0b181bc70318f8d5d4b9bdead7fc748677fe2a |
29-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement .cfi_escape. Patch by Brian Anderson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147352 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-escape.s
|
| 19f18be449268605ea210e68b02220a0e7bd0c15 |
29-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Expose FMA3 instructions to the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 4050bc4cab61f8d3c7583a9b60f17c7da47bbf69 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| b975c27adc2371a9666fa9b8cecd9487966ec5b1 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix incorrect relocation generation. Patch by Kristof Beyls.
Fixes PR11214.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc-reloc.s
|
| 8d9550bde95c8d128e7bf62e9e65dec1854e2d1d |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-aliases.s
|
| bc24985c5ff01fc25336896c388bd8e4e02ffd95 |
22-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
ELF relocations.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-tls.ll
|
| af33a0cfe092afd327e1b8b05c655d9eab689eed |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP optional data type on VMOV GPR<-->SPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 520dc78d92a47af5e644b09f401d278cb1d5d196 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 2cc5cda464e7c936215281934193658cb799c603 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e6949b13997e6d31aa4719a0e80c4b6b405e42a9 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 3471d4fbbd50eabb12511b711cbd2afd7bb9d962 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 06d738c76a1ce4fe17fa8fc4a62288a09d1ae5ec |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable and fix a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-encoding.s
|
| 5b484312c66f8d125c072517947538f301c5a805 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VST2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| 514806b52e88aca0c30f55763a997d1befa7c2ba |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM enable a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| 95fad1c6034cdf8010428e61b71cd196ee1698ad |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 04b5d93250bef585631a583a85f6733b1bdc8c52 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 2f196747f15240691bd4e622f7995edfedf90f61 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| d22170e16a42aed0212e1e52f189bfb8b7c7105d |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VPADD.
rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-pairwise-encoding.s
|
| 61b74b42478474534827070cdd703811ddc9ce19 |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON implied destination aliases for VMAX/VMIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-minmax-encoding.s
RM/neont2-minmax-encoding.s
|
| eeaf1c1636c664c707fd9ecc96916fd20ddf137a |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 8f7d12ccfd8feb258bdf4e582592bc00beacc7c6 |
17-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
asm parsing and testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/secrel32.s
|
| 7e840efc238db1123ea625b3d4e9893d6ea1bc50 |
16-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-avx-encoding.s
|
| a738da7bd30819f1bc710d313c9ecb06c56f1a4f |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.s
|
| 60d99a5278e4a0e7116a05c01cececb07ca1362a |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VTBL/VTBX assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-table-encoding.s
RM/neont2-table-encoding.s
|
| 9b1b3902882675e5ce35eacd639456bd648324b7 |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
RM/neon-vst-encoding.s
|
| c3fc3136a1760601458267163ea0fe6d7e4af72b |
14-Dec-2011 |
Kevin Enderby <enderby@apple.com> |
Improve the implementation of .incbin directive by replacing a loop by using
getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_incbin.s
|
| ec04a3f8db9ab9db3bbec3ce32baaa2ea2cb853f |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON fix alignment encoding for VST2 w/ writeback.
Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| c55accaddb472a517f697d4b0c44017f40c2a5a7 |
14-Dec-2011 |
Kevin Enderby <enderby@apple.com> |
Add the .incbin directive which takes the binary data from a file and emits
it to the streamer. rdar://10383898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_incbin.s
smParser/incbin_abcd
|
| e90ac9bce9aa6de288568df9bf6133c08534ae2f |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
isassembler/ARM/neont2.txt
|
| 8d11c6349f9bf276534907245946518042c1bb60 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| a39cda7aff2d379ad9c15500319ab037baa48747 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for the target-specific .req directive.
rdar://10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
RM/dot-req.s
|
| 863d2af9477e331955a9bee8be1969ce658b59b5 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler aliases for "mov(shifted register)"
rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 27debd60a152d39e421c57bce511f16d8439a670 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDM/STM system instruction variants.
rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 0da6e867cf10a0bcca56df8d854355025e1d6f91 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Test for 146516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 55b02f28c1a2960ebb88cf5019cc5b36bb2eabf4 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM thumb2 parsing of "rsb rd, rn, #0".
rdar://10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0f293de207fa0e9461a9dbee95bed9a6a2c52f76 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VQDMULH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.s
|
| e91e7bcadc445381adef5c5154e8e2cba074505f |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-UAL NEG mnemonic for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| d1472e8657e4ee4c4bc0e30a928d6cab47798319 |
13-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add test/MC/Mips/dg.exp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146472 91177308-0d34-0410-b5e6-96231b3b80d8
ips/dg.exp
|
| 692be5491adf977e5bbb14e17c2afb88c1c2e0dc |
13-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Move direct object emitter test to directory test/MC/Mips. Rename it to
elf-relsym.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146470 91177308-0d34-0410-b5e6-96231b3b80d8
ips/elf-relsym.ll
|
| 5a3d4c983069f0646065b773a7c11a900f9ff94a |
13-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Don't rely on a particular version string for llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146456 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf.s
|
| 37e7ecf52b2f4e282b58ab81e59adc8b9b4ec336 |
12-Dec-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
XOP instructions and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-xop-encoding.s
|
| a0c17a495b12debcb7f206993bbc6020e2e6e8df |
12-Dec-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Add support for gnu_indirect_function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146377 91177308-0d34-0410-b5e6-96231b3b80d8
LF/type.s
|
| 59164b731b36a1018a8ac241b0f2dc0a08dfec90 |
10-Dec-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Don't assume things about the exact details of the LLVM version number,
such as what VCS information is attached.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146333 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf.s
|
| f3aefb56def210eb0c23ecb8f2e0bf7f4be78a37 |
10-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
LF/global-offset.s
|
| 840bf7eda7c81059a0aae9abd51262147c60d814 |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| a4e3c7fc4ba2d55695b0484480685698132eba20 |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 3c68acd202d061c38e9b7744012094b4009d932a |
09-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle reloc_signed_4byte in here. Not doing so was a regression from my
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146273 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 94c2e85bea1ab1b837a4c055ccc83d5cd32dd027 |
09-Dec-2011 |
Kevin Enderby <enderby@apple.com> |
The second part of support for generating dwarf for assembly source files. This
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146262 91177308-0d34-0410-b5e6-96231b3b80d8
achO/gen-dwarf.s
|
| 1d5969d839ddc4d0af93fd035aa13131e5c6fa82 |
09-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146238 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 8759c3f548e03f7caff45f35fde49ed3e8c1cf71 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.s
|
| 6b044c26094a9f86da7d12945b00a47a5f07cf6d |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VSHR implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 318df74104459156222968792018f29a0a530ae3 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 120313435d217d869bd2141b0cd8f4d99ae4b9a4 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VSUB implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.s
|
| beef39ab6326ed162aceb9d2e4ceef98d51d40b2 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.s
|
| 9e7b42a40eb8fbeac92ad2272d983d559a554c37 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VQADD implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-add-encoding.s
|
| 1c2c8a9389526518164ab6386ffcd6a1fa01124d |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM a few more VMUL implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.s
|
| 730fe6c1b686fe71c8e549b0f955e65a6a49d3ff |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VSHL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| ff4cbb4c9a66d313a9f52830620f06c88b43397c |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VSHL(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| a44f2c4a28cd9c43a3d34cbad4f47df77ec686cf |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM optional destination operand variants for VEXT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.s
|
| 71a0a2ec0b367ecbbe1b6e8b528d65c738d7c2d6 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.s
|
| 3bc8a3d3afe3ddda884a681002e24850099b719e |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| af4edea67b007592f9474e07d27182956e37f7f5 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 9fa0a743e6afef4ea5fe7b5115607947696774a8 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VAND/VEOR/VORR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| 30a264eb7fa6c961e94a7eb3d3eaf72d9bc8a44c |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VADDW instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-add-encoding.s
|
| d900441e134564aa396522ab6e4617a98db91e34 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VADD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-add-encoding.s
|
| 577b09155f9a6fa38e5a7918da9701e120b3642f |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Darwin assembler improved relocs when w/o subsections_via_symbols.
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
achO/ARM/darwin-ARM-reloc.s
achO/reloc-pcrel-offset.s
achO/reloc-pcrel.s
|
| 8524bca75076a5e94ba3263968fa4b9e4fc6234f |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alias for long-form pop and friends.
rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 9a70df99ca674b288d50dbf454779ed75d6e48dd |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM support the .arm and .thumb directives for assembly mode switching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
RM/mode-switch.s
|
| 470855b24ff4e82360ce1f84a1088332f3b4c8ea |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.s
|
| d552a644bec41fe137712c9185d4ca4b0bb54489 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Move MachO tests to MachO directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
RM/darwin-ARM-reloc.s
RM/darwin-Thumb-reloc.s
RM/nop-armv4-padding.s
RM/nop-armv6t2-padding.s
RM/nop-thumb-padding.s
RM/nop-thumb2-padding.s
RM/thumb2-movt-fixup.s
achO/ARM/darwin-ARM-reloc.s
achO/ARM/darwin-Thumb-reloc.s
achO/ARM/nop-armv4-padding.s
achO/ARM/nop-armv6t2-padding.s
achO/ARM/nop-thumb-padding.s
achO/ARM/nop-thumb2-padding.s
achO/ARM/thumb2-movt-fixup.s
|
| 18851edbc4666a8c8695b294e8bdfabbe157c086 |
06-Dec-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
RM/relax-thumb2-branches.s
achO/ARM/dg.exp
achO/ARM/relax-thumb2-branches.s
|
| 23261af193e462b73257445053f9f6515e60e8c9 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| cf9814ddd277dfcbb4ec5727e2cb510b8a451e04 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2: MUL two-operand form encoding operand order fix.
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 encoding choice correction for PLD.
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 286ea03382a5daa1b20f780f40807f1a0257a62e |
06-Dec-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
MC/MachO assumes x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
RM/relax-thumb2-branches.s
achO/relax-thumb2-branches.s
|
| d9a6e8978dd65c85d68bf1141d992da576878cd8 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM handling of tBcc branch relaxation.
rdar://10069056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
achO/relax-thumb2-branches.s
|
| 713c70238c6d150d2cd458b07ab35932fafe508e |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ADDrr fix. Bad check for explicit .w
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
RM/mode-switch.s
|
| 6e507c645d469f525a46c4280cc29bd3078bb9d0 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Update tests for r145860. Add a few new ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/mode-switch.s
|
| da84786bee8304588a4325b15e297be1995a5d41 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
rdar://10529348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 253ef7a77930f6855a5bf24037e9dfbc65a1ee85 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for the rest of the VMUL data type aliases.
Finish up rdar://10522016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.s
|
| c4f0b309eeaa479de9bbf62eaf304931a526f622 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for VLD1 single lane w/ writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| dad2f8e7fb2df5fb080a38fa4c33a01f19729f15 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| dd649e35e522f5e0b5da3f9d172e06a375c12f77 |
30-Nov-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
Support for encoding all FMA4 instructions and tablegen patterns for all
remaining FMA4 instructions and intrinsics with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-fma4-encoding.s
|
| e30171ba0ce10c8a37ee1aabc0d5cd13136dc7c4 |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some tests for all-lanes VLD1 parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 4c7edb3ad8bd513c59190f6ebee9bee34af7d247 |
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for four-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| ed1f83f9af83f71b04b2aef820195d8db5dab00a |
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable some VST1 tests and add a few more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| 116bc795da4b10773235a89cc251d31651b3851d |
29-Nov-2011 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC/X86/COFF: Allow quotes in names when targeting MS/Windows,
as MC is the only assembler we support.
This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145409 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/symbol-mangling.ll
|
| d2bf432b2b6ba02e20958953a237213d48b00f20 |
27-Nov-2011 |
Chris Lattner <sabre@nondot.org> |
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
|
| 4c729f115212f6d9a7781745598ddcbd38959521 |
27-Nov-2011 |
Wesley Peck <peckw@wesleypeck.com> |
Add several new instructions supported by the latest MicroBlaze.
These instructions are not generated by the backend yet, this will come in a later commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145161 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MBlaze/mblaze_mbar.txt
isassembler/MBlaze/mblaze_pattern.txt
|
| 1b9b377975b3f437acef8c2ba90de582add52f65 |
25-Nov-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch contains support for encoding FMA4 instructions and
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-fma4-encoding.s
|
| 9d399b1fc2f7dfad72f5ff3328983acb805eaf10 |
24-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: alias cqo to cqto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145121 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 9b1671bae7beeef848f19424c42ad161c6eb1082 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove obsolete test.
The PLD encoding is checked via the .s file now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144853 91177308-0d34-0410-b5e6-96231b3b80d8
RM/prefetch.ll
|
| 2abba8496cb394af53b531e95067d5cae78bb9ee |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 47a906ac2376bd6288270f2f6d4e06b5a988bd14 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for r144842.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144851 91177308-0d34-0410-b5e6-96231b3b80d8
RM/nop-armv6t2-padding.s
|
| e43862b6a6130ec29ee4e9e6c6c30b5607c9a728 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for register range syntax for VLD/VST register lists.
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 9f302c4fb3feeb36561a6eee0168ee5242d8ac20 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing two operand forms for shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 19885de61ddbfe1a0db858e303baf19a190bc57a |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM alternate size suffices for VTRN instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.s
|
| a68e90c36e6a53fb1889b608f44d6244a36b3e97 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| bfb0a1717bb140c418e070042e852f925e92de01 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| d2586daf069f480e924cd7dd2079dd39de331541 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 908f923cfc63c9c941dfa77b13a281f4d845e03c |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcase for r144684.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144685 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| b589be9334ee5352dd263c406b99a90d413c0b2f |
15-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 1de0bd194540f8bab399fb39c4ba615a7b2381d3 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing for mul.w in IT block fix.
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| dd47e0b5d4850fede4b2581c41f1e0a5eff5f05a |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| e052b9afa1301419f8b52eed9ed370393fcad78d |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| ef448767a35148261d6c82a8e55e6e2f4be8e631 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| ffc658b056b7cc0b3f6a2626694b6a4216ed728d |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/fp-encoding.txt
|
| c7352f8ca0fc716c38cb3d81e63e943d47d578b3 |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM optional size suffix for VLDR/VSTR syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| ce485e7f70faed6d19daafff91bb20509403d432 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM allow Q registers in vldm/vstm register lists.
rdar://9672822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 5402637ff283d7397513d5c1699cdf2274c47313 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 1b332860aef0121cf4591f4377a7201ce0ef8366 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| ee10ff89a2934636570cb17b756bf31b2a38aab5 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/thumb-diagnostics.s
|
| 71810ab7c0ecd6927dde1eee0c73169642f3764d |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 3c5d6e4df495316c0d2e0a7bca5ec7a88aa400a5 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing STMDB w/ optional .w suffix.
rdar://10422955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 70be28a5adba5bcae0c6dcd63f17592864c351fc |
07-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
RM/neon-mov-encoding.s
RM/neont2-mov-encoding.s
isassembler/ARM/neon-tests.txt
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
|
| 81550dc0a866e27a1efbc5de616fb366ebb547cd |
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 064e48a3dce1fd29a35b4b1b01a8c4b67e29c74a |
02-Nov-2011 |
Kevin Enderby <enderby@apple.com> |
Fixed a bug in the code to create a dwarf file and directory table entires when
it is separating the directory part from the basename of the FileName. Noticed
that this:
.file 1 "dir/foo"
when assembled got the two parts switched. Using the Mac OS X dwarfdump tool
it can be seen easily:
% dwarfdump -a a.out
include_directories[ 1] = 'foo'
Dir Mod Time File Len File Name
---- ---------- ---------- ---------------------------
file_names[ 1] 1 0x00000000 0x00000000 dir
...
Which should be:
...
include_directories[ 1] = 'dir'
Dir Mod Time File Len File Name
---- ---------- ---------- ---------------------------
file_names[ 1] 1 0x00000000 0x00000000 foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143521 91177308-0d34-0410-b5e6-96231b3b80d8
achO/file.s
|
| 60cb643f7561e5be7a3b5fe705535e96de72cbf5 |
01-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of some VST1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 5e6d54806570db81bbc8bdb480ce049f4bad05cc |
31-Oct-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move test to the X86 directory, note the PR number and only run MC once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143352 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/2011-09-06-NoNewline.s
86/2011-09-06-NoNewline.s
|
| fb6ab2b30e822d292c557bda32f7eb0acd1004e2 |
31-Oct-2011 |
Owen Anderson <resistor@mac.com> |
More not-crashing NEON disassembly updates for the vld refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 89a633708542de5847e807f98f86edfefc9fc019 |
29-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 017f87cf68c48e0b23f6250c86aa13d212ded77a |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix illegal disassembly testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143231 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| cb9fed665550376b7c65c7e1157a58911193e2e2 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-CPS3p-arm.txt
|
| 5d0492cfc4521ccb13b4961227b279991a17c393 |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb-diagnostics.s
|
| 398daae4cc0182f77ff0e68d7ba4b7614ce8af71 |
28-Oct-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction.
FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143195 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/2011-09-06-NoNewline.s
|
| c73d73eb881ebe7493e934c00ca1c474ffd0ed2d |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.
rdar://10348896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 03e03b098462c2715598ca96298110b63c57a2d3 |
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add testcase for r143162.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143163 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 55c4127134d127ccd52cc2f4115af00084b28807 |
27-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143112 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86-64.s
86/x86_errors.s
|
| 88484c00307274568ab068909cb38ecaedd41cbf |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
rdar://10348844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 036a67d670413f8116415b87457f22d256f314ae |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
rdar://10348584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a581328ceb4c9db165d79a4dabd6b28db799d70f |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldr pc-relative encoding fixes.
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 399cdca4d201f7232126c3a0643669971ede780a |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 12431329d617064d6e72dd040a58c1635cc261ab |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
One and two length register list variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| a7c98f58ea939e1dfe40bba725fbac698f36c0bb |
24-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neont2.txt
|
| 1028132b90a10a46c87b2ee2ad0156e2f9143c25 |
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for r142801.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142806 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc-reloc.ll
|
| 5679ec3b528fb897739251b1f66037767ce2f208 |
24-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 SARX, SHRX, and SHLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86_64-bmi-encoding.s
|
| 75485d6746f8b5b23c17cf6d2364e7e1e0705992 |
23-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 RORX instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86_64-bmi-encoding.s
|
| 4fea38f7732bccd1781390aedcef2bbf87e25990 |
23-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 MULX instruction for disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 224180e81b34c99d15e35a4d4de6729357c6d372 |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 4661d4cac3ba7f480a91d0ccd35fb2d22d9692d3 |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| cd20c58e980552daef182247005cf905fe8b06ba |
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/basic-arm-instructions.txt
|
| fe0748d696a69b66e11fce0256663070c0bb7e70 |
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding tests for fixed MSR encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142624 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/basic-arm-instructions.txt
|
| 50965031848f391f98f11770b3823497d5bf5c15 |
20-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix tests for corrected MSR encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142622 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 6b09c77b7a831f57ccedb20c760031492a0af043 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
RM/neon-vst-encoding.s
|
| 760b46ce1851f9414c4d95093e8897cb32734560 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142582 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| d0b614754eb2d5ce9c2b0841270872129f956059 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VTBX (one register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-table-encoding.s
|
| 12ae52767f2d0e4312ba059c0e97ed8beb9777d5 |
19-Oct-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix parsing of a line with only a # in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142537 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/line_with_hash.s
|
| 717cdb0df88ddf704f057fb70ed7093836222609 |
19-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86_64-bmi-encoding.s
|
| 2933e4b2e65a5c5ae9958d4550cd47db793b9e54 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142422 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-table-encoding.s
|
| 39dc2af7f99c92a0c11f19b8b97bd306c75c3bdd |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142421 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-table-encoding.s
|
| 0487e459e06a2ae2b6e9633f17a37027c9e34b8b |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable more encoded immediate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142415 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| ca8d1842cff5cd5866c0d4d46cf736ca9f8718f4 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
More vmov lane testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142414 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mov-encoding.s
|
| aead579017d0f8c43dba3bcb049b1d2576b9f8e3 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmla/vmls assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-accum-encoding.s
|
| 687656c6300138583f2e8e3cdaff6cfeb6261b7f |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmov assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.s
|
| 9120088979dbcd20e8643bc8f5b22bc605c7d974 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmla/vmls assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.s
RM/neont2-mul-accum-encoding.s
|
| e8692ed5a66a4382ee0adca317dd348935426d79 |
18-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Another failing encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142388 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-encoding.s
|
| 82fa5fc7093be4b1180f405c4802150fe830033b |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix NEON mul encoding tests. Wrong file contents previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142387 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.s
|
| 0a0374018f1d17d6d2895fb73026e2942ab111ed |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vqdmulh assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-encoding.s
|
| 37a3ed21c4ed418982805150809b846624b853ea |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove duplicate test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142383 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-encoding.s
|
| 9e7df4ad5b46dbb427499da8d4dfde7460c1c5be |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142382 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-encoding.s
|
| 970f787a7e3929c9cc1c0faabf224d26c1fcd252 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmul assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-encoding.s
|
| ec11d2a1b86378df0d65819b725e2a6b88acafd4 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142380 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-accum-encoding.s
|
| aff187a19ac60fbcbc220f474112d354e57e72b8 |
18-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add a few more testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142379 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-accum-encoding.s
|
| de1ff7f5520989bf20ef391c9eb4aa320d865fbd |
18-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add several FIXME cases for ARM encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142377 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-accum-encoding.s
RM/neont2-mul-encoding.s
|
| 5e3e811bf6d4d3fa9fa1c6abdaa6fd7ee75dddf9 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tests for 142365.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142368 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.s
RM/neont2-mul-accum-encoding.s
|
| 444282461406b45c7770b3161b2e879ec4f64da3 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142367 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.s
|
| f2f5bc60f61acf0490d856ddd09e461bf93c5459 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV.i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.s
RM/neont2-mov-encoding.s
|
| 6248a546f23e7ffa84c171dc364b922e28467275 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.s
RM/neont2-mov-encoding.s
|
| 7c81013c4521ceab3e98d5be1fdcf3853e27e077 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable a few more NEON immediate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142313 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.s
|
| ea46110f57b293844a314aec3b8092adf21ff63f |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mov-encoding.s
|
| 44d798d9763bc32aaf49fe7c10d604845f4b6685 |
18-Oct-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add support for a new extension to the .file directive:
.file filenumber "directory" "filename"
This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142300 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_file.s
|
| 0e387b2877e4eebeedfcb26b08253f9c1b946035 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.s
RM/neont2-mov-encoding.s
|
| ee62e4f6d192ee31d1ad9dd0ba0c41db6663d3c7 |
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86_64-bmi-encoding.s
|
| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86_64-bmi-encoding.s
|
| dc479c4a897bb7cc756370cc2051da79b65e7d16 |
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| d8b7aa26134d2abee777f745c32005e63dea2455 |
16-Oct-2011 |
Chris Lattner <sabre@nondot.org> |
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_errors.s
|
| 17730847d59c919d97f097d46a3fcba1888e5300 |
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86_64-bmi-encoding.s
|
| 566f233ba64c0bb2773b5717cb18753c7564f4b7 |
15-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
86/x86_64-bmi-encoding.s
|
| 008c8384346ddee44b26f0161757432d3137e7b7 |
14-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Update test for disabling of code/data marker labels in ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142003 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
|
| 54a11176f6a5e07e243f1d87ba19ac3f4681976b |
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 ANDN instruction. Including instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 909652f6876a97d63db20606cd1b37e95d016caf |
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 1203fe7fc80d0fe16a30ae3ddb9b0823b17f39ce |
13-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r141854 because it was causing failures:
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 8ab1d1e900a5346db019b6a038e3f497bcfb506e |
13-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| acbaecd4c8e4d19207e63624dcd9e01947b51757 |
12-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Finish supporting cpp #file/line comments in assembler for error messages. So
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141814 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_errors.s
|
| c66e7afcf2810a2c1ebf08514eaf45c478e5ff67 |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDC/STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
isassembler/ARM/thumb-tests.txt
|
| 9f45754750b03516db23b21021db72b20336ea85 |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding tests for STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141787 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 2bd0118472de352745a2e038245fab4974f7c87e |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| fbab2206cfe5573bdc215fb40dc9df0d562cb02f |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for r141704.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141705 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| b1b8f5f7cd4c6baf246aca9f14a70c8f184f9717 |
11-Oct-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141653 91177308-0d34-0410-b5e6-96231b3b80d8
LF/many-section.s
|
| 37f2167f15608ff56d202ff21954a456aab6e534 |
11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 LZCNT instruction. Including instruction selection support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 29480fd798dc6452948f63825ff41c66f09c2493 |
11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 7aabcb1fc0a94becb437134747a63ff686c0661f |
11-Oct-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Also create a shndx even if there are no symbols. This lets us test
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141641 91177308-0d34-0410-b5e6-96231b3b80d8
LF/many-section.s
|
| a0ed0c0fcdd8b94f741f296a67669da3180fb42c |
10-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Insert dummy ED table entries for pseudo-instructions.
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/enhanced.txt
|
| da394041c409cb06008e60b9f9f845e845215b03 |
09-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 051fee03127ed20a6bbe66389c47edcd969f4cc7 |
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable ARM mode VDUP(scalar) tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141447 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-dup-encoding.s
|
| 460a90540b045c102012da2492999557e6840526 |
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-dup-encoding.s
|
| 75fe5f3bab7c33c14e5f7956e01a9d95d2712cc5 |
07-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 1b526a98e367c9a512a082a0d008123206b2a558 |
07-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 25f6dfd108801d1dc5877c420ef0dd47131aeda7 |
07-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| bee5d2fac867a25272bc8a393f3e4f6f581fe07a |
07-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141321 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-dup-encoding.s
|
| 7abb7956350238f2edbc2d8e5d0dec61f44df2c9 |
06-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix and clean up tests. Un-XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141318 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-absdiff-encoding.s
|
| d6f85098e18ee2869e15c41efdff1252f45fa54f |
06-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix and clean up tests. Un-XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141316 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-pairwise-encoding.s
|
| 7ea16b01fad5236cc132cb5fc3e443fcbf70d3b8 |
06-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| 2dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31 |
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 2fec6c5ff153786744ba7d0d302b73179731c5e9 |
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
|
| 0ebefdf8345d0bdfcccde4057f3cce1c2dbbda9b |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| fdf6bb41a4677897e91b181eec849e81a822026c |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Comment out individual failing instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141117 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-bitwise-encoding.s
|
| 20f8eb2fc1d1d45d2645a45fe383f572c98d939d |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141115 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-bitwise-encoding.s
|
| e5c933848a2211f7628b2770a8942d48d5bd4230 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141114 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-bitcount-encoding.s
|
| dc6c93531d2bfa4f5aa6c6ce8163365a4750254e |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141113 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-mul-accum-encoding.s
|
| 100902c6da10f909610d408255c8899fa04c6de8 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141111 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.s
|
| 0c0cf47ed54e5fa37f656e1274aa680d88202de1 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Fix incorrect CHECK line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141110 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.s
|
| 62ea269b9a7d0396d02399bb9a95c5f65ecc552c |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141108 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-dup-encoding.s
|
| a02dfe7a6bd25b7e18ed472cbf556208658581fc |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141099 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| 36db6fbe57ce5ce53c233ea5ac0f6d4d5e628531 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141096 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| 6744a17dcfb941d9fdd869b9f06e20660e18ff88 |
04-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 3207e6c6b78dfe5299cb47c6d04d3ea76dbd0e6d |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. These tests are covered in the .s file tests now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 9d39036f62674606565217a10db28171b9594bc7 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 68259145d9ac1f8d4e2cc9fc73626254fcc5cf08 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing/encoding for VCMP/VCMPE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 5cd5ac6ad455880395e34ac647f1e962a83763a0 |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMRS/FMSTAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| f8bf43ec99d4410c3e351c76f806208d1204129e |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for 141010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| c82c101147ad680d7db45e75886c9a4e8419a2f0 |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.s
|
| 581fe82c84839f769a7275cf4cde7ea209f5ed04 |
03-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 04c5be9f12fbb802ae48791399e999f29c0fb5c9 |
03-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 04b0b34b3aa3be028295e2aeccdfd054c449e310 |
03-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Test updates that were supposed to go with r140993.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
|
| 82f131a017f27462162062bd9ad0d4cea3166c61 |
02-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| 146c6d77f02bfc631ff21f01c14edbf52f1aa884 |
02-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 846a2dcada30a3507a1e9af9eabc2919674e669f |
01-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of INVEPT and INVVPID to take operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| e1b4a1a07ec79440536e4535721f15de3893cd13 |
01-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
isassembler/X86/x86-32.txt
|
| acad68da50581de905a994ed3c6b9c197bcea687 |
28-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2-mclass.s
isassembler/ARM/thumb-MSR-MClass.txt
isassembler/ARM/thumb-tests.txt
|
| 25ddc2bf7ed69f500dd4d3e003004bda28c3dd95 |
28-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 21733e8f80ac3f50af16d11626f5c9aa1bb1e1c9 |
27-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix an incorrect decoder test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 256e10f96461f6a06c0ff3fe892981f40626791e |
27-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Remove incorrect testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140572 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 100d86ada512e495104580b71e28599308fb7365 |
26-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix VEX decoding in i386 mode. Fixes PR11008.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
|
| 4d2a00147d19b17d382644de0d6a1f0d3230e0e4 |
24-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 1f24002ed42fb93662674b3bec36b0d66d9635ee |
24-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix incorrect disassembly test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140423 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 0781c1f700886f94f5430380a5e82d7ccf6bbdc0 |
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 31d485ec9a2afcf83c5354061568b4280d61b574 |
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 4da632e6e09b96db4b3f9202cde4e6ca732001c1 |
23-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
|
| adf01b3f18442ae8db6b8948e70d82d9df415119 |
22-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
|
| 61268701931d747fa95e0be8a368101e7f97b83c |
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e1368729700f1a51ee5cf33431df985e232bcc68 |
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
isassembler/ARM/thumb2.txt
|
| 448d98685847a1daf7451b95904ae92a3cbab2ac |
20-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The wrong relocation was being emitted for several SSSE3 instructions.
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-avx-encoding.s
|
| 9d1a3dea15f33de1c44438dce0676830956f9503 |
20-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port over more Thumb2 encoding tests to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140152 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 50172e77bc3c41320a01776461a0e839d718c297 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke obsolete test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140127 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| ac9c2aa8e1b8ff36934e98287e1733995c5ac20d |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for WFE/WFI/YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140126 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 50f1c37123968b7f57068280483ec78f6ff7973e |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 400b624e02216dcbe1ec0c17963caa088b33c57a |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USUB8/USUB16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140120 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 6053cd956fa6c781a4ee05cbc99ab15db3cf3d13 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 653419fff0420a6c9cfc953c135f1e9dc3420a45 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USAT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140118 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a7e5b01fe1156050ac9174a421ecf90911e1949c |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140117 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| ae13ba774083ef328a08290af649b4cd1156b40a |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140114 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| ad7d7444563b628dd723015e9c44692d5b67067e |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQSAD8/USADA8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140113 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 73e019eb12bda5a3dd6165b749dfa08b8b30e477 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140112 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| ab3bf97fe029e3ce6834b54c4c5a647c0b665546 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d7e2785ea8af746abee99aaef074a610d5ed73d8 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQADD16/UQADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140110 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d91c6e058b3f21a5299e6a2e8b9ed2f6899e0b19 |
20-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140098 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-avx-encoding.s
|
| 9c6712721c114f8e67b9a6b3cb1dd5d18b4cb435 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140096 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 9546de68aac116cdf6f0af5a2972101acc476e0c |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UHSUB16/UHSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140089 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 6729c48b940df5c141eec6375d14544cdbb2ed3f |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 2c1ef5bac85f3ef002047178490a00c5ea2c7cfc |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UHADD16/UHADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140087 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 6451cbf79f75fde6319cd4dbcb8a48aecac702f4 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UBFX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140086 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 4032eaf98c63b0fb1f2418a1cdc56b72bc76c329 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 11f23c1a7260a1cb4b4eee20aea09676e15d55c0 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix copy/past-o. Gotta remember that 'modify' step...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140082 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 661daa481ef438ea797b01df470d2190c93c9863 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UADD16/UADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140081 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| aa70695ef045a54eb8c4f701f9db03179c816b48 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140080 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 7f739bee261debdf56bd89ac922b57eca53e91dc |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 1494c496e2827f991f75eae4acf8f7bf9952abdd |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TEQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140070 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 30b8b970e319b92300a9501f4578cb099e29a920 |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove FIXME. TBB/TBH are Thumb mode only instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140048 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 326efe58918d3f0a431d07938054870fcd0e240f |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/diagnostics.s
|
| ecd1c557904815e568258fc5420de479589b0a93 |
19-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 8a8d28b0392a27ff8e0c60c04561671023a08dc2 |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 9883acd2a6c0851b9095409bcc0541b26165015a |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140025 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 7649b0b8c708f95e318296bd6a4b3968cd6bb38c |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SUB(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140024 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 76034c5f546770faf5e63a878c996a829bcb31c2 |
19-Sep-2011 |
Stepan Dyatkovskiy <stpworld@narod.ru> |
Added regression test for bug #10869.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140012 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/2011-09-06-NoNewline.s
|
| be290af0d8b6d84762384aa08e47e44c2375173f |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add a testcase for another corner-case decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139970 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| f67e8554bf4808ad447ffb5d2deebbb10b810391 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SUB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 89db0f690c3238544e59ea3bf2b7a0d6bc8a6544 |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 47313df81c096005dbbe8dbe729375f7d0bb3e15 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139963 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 18ceae2a705cd4da38a6f67bf0bb9d8615a8b254 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRHT/STRHT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139962 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 4a1d200c2f850dc7b0eda6b8fa89157d21b731c5 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STREX/STREXB/STREXH/STREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139961 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e45451eea9cd7fc78227fdb94f215ff22e9d0f75 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139960 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 75d74282759293b5f5abeae5b3f9e0cec42ae52f |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Simplify comment. There's no Thumb LDRD(register) encoding. That's ARM only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139959 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8a28bdcbcca3328364b86c4010fe96590d1952c8 |
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| e041af7e0e0b6b59457c3218e6489412793a869c |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139957 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| c71ed786c3b7d2e8072483805434e23f77f606c5 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139956 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 59c50760941742870786ca6f497f3dcecfc965e0 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove test of undocumented format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139955 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 76ca6d9bcd093ced4277109e6819d49eead0c956 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139954 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 2e7a94137b742798df9678bff925f17844c1e0ca |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle a few more thumb2 tests to match the comment headings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139952 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 5320b40d9e6f9d0cbabcebaa3f224e8ba1fc00cd |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 tests for STR(literal), STR(register) and STR pre/post indexed immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139951 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0bb7c6e8d627edb8c83599c88ad9315636434418 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle a few tests around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139950 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 705b48ff860e7484f0adee88362dbe1936ae936b |
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 642caea2c624aaeb492a112d60f419ee4d1a10c7 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STR(immediate).
Add aliases for STRB/STRH while there. Tests forthcoming for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 36343d85cd42c5fbeb7556655b9ab48bce8b8fdc |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STMDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139940 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8213c96655e955a0b63b05580bc2f6a55be26083 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STMIA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 3335029b1f4cd663411277aa2f93b4eaa7a0289e |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSUB16/SSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139931 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 50bd470d85c63860f887b7c3e5724c9fd43ef3a2 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139929 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 9f4ddb3efa0f76d7c2463648eca9d82403c2e8a3 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139927 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| b105b997a49c809bfd464ae7691d5ee45d34f446 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 05ec8f7ac90179cccb476512c872db95bfec418d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| dea84127840ad38100569d2cc5045c5086ee668d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMUSD/SMUSDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139923 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 41ca75bed0e32d4ba4fafd445e6641b34e490046 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMULWB/SMULWT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139922 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 3443ed525a3bce98bacabb5aa8e67bee6def3b09 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 3c4c879695eb282f01d89da87d5da0a141e7f6f8 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139919 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| d727148c21f7294032a07f7e66b4aa06085c7f0b |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMULBB/SMULBT/SMULTB/SMULTT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139918 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| c9592cbad501956c71cd9e7f515f48e2b05b6052 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMUAD'dib.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139917 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f3578a84974e0291582966e4a3aebf3802ab211b |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMUL/SMMULR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139916 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a610d619ce545bce7fdd1c6c159fe4a56983188b |
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port over more Thumb2 assembly tests to disassembly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139915 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 1070278efa2f196f49b9ff6794f76e151e9d06c9 |
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port over more Thumb2 assembly tests to disassembly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139912 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| cb574bb71edcb816509db434d220e9e1bb51d53d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMLS/SMMLSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139911 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 3b61d23297a8401fb1aadf129fdfa282f175f88d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMLA/SMMLAR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139910 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 7ff2472b8235d8702bd04bf297d573d06cf6b40d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 920ad2b6810e008ad98ee42b51abf791101aa8df |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLSD/SMLSDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139908 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f566ca741885285d565ad5347baf9663ed7b7d62 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLAWB/SMLAWT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139907 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 231948f860df79b7f0926305caa065a64d758265 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139906 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 4f2999b2969416aefe9328b73a61f5d64e424a92 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLALBB/SMLALBT/SMLALTB/SMLALTT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139905 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 837fc5e9d5138ed48a74a672dc4c1525e5975ce8 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLAL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139902 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e74711b8b0c7abd0383ebb70941cdcb779918e12 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLAD/SMLADX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139884 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 246ae02bce7afb0411d21803eb0ad1b3832189f9 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLABB/SMLABT/SMLATB/SMLATT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139881 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f08084ba4bbabd1c22ad654347e77218a16b9a80 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SHSUB16/SHSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139880 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 5a6370ff99013ce8a9db12e127770395e81767b4 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SHADD16/SHADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139871 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| c075d45364190dfe06eda8aa93b6856d4f55f107 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139870 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d16160f18af7735924ad37e69f54308ba037f1e9 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SEV.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139866 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 56019a32bdfc65b3e97aec3827f4d12b091365bb |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139861 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 7ecedac8b726926cce5758b791c5e78caff8b5ad |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SBFX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139858 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 356c759908e1c6b968293d54bc4aa26bc8415407 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some missing 'CHECK' lines and tidy up others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139849 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| fd8b8519087d19d3ac4c3a0b23e6f7a6c2ced46b |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SBC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139844 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e4e4a93e9ec6040b6466bf067d5e02533471f093 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| ed15ab1aadea6216b30ccfc659b194d09f44ca14 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SADD16/SADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139841 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 191d33fd6d0a91e89f2a8f719e5adbdccf9effa9 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| aba8015cc375ac7de757d92e55d1aad986de6202 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RRX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139831 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 5260be1f2d8a2efe9aea398248736556cab42eeb |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ROR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139830 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 689b86ed2e1f1daf9201f0ef83ff3bc1d5167232 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV16/REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 1b69a128d6b98456c666b4031cc46c3d0fbe6177 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 4bab3c77102954380c923505c413a2df7aca48eb |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RBIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139811 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 3e3a9c796453afed58e27d7bab926061f8dd2d16 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for signed saturating arithmetic insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139810 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 07d7f3d387739b52f0fccd7c9d7bb54b0195f56c |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Re-order test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139795 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f18544d1e55f6e8e3929c1bb840d8fb8709064d0 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139757 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f83e297cd1c36293d8950106b6d87f0558f21e80 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PLD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139756 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0b69247b10ddbce5f0c476c3471918ffc6091ac5 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PKH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8adf62034a874adacff158e8adc9438cb3e67c01 |
15-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0b3ed6de80734c3ac15e1b1f0b5306a1f61f88ce |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139742 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| b72504b4fad51941523b5e6db3edba58a2ebbd90 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ORN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139741 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 5c5eca3534b616fbdb8d2c7c56ab2182f4a9ef05 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for NOP.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139740 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb2.s
|
| d32872f9ca446fc48084082fcb88255a55405cc2 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 64944f48a1164c02c15ca423a53919682a89074c |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| bf841cf3360558d2939c9f1a244a7a7296f846df |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MSR/MRS.
Fix a bug in handling default flags for both ARM and Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb2-instructions.s
|
| 97f50f3870fabfc7358543699fe608c59c61c2e6 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MRC/MRC2/MRRC/MRRC2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139717 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb2-diagnostics.s
|
| 95be01a56905d15f42ca47b793c1af8a5638c89e |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MOVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139715 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| c2d3164ab467bdfa8508b93177e69b99626cd8e2 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing for MOV in IT block.
Select the right 16 vs. 32 bit encoding in an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d0588e2a2ed1f7570f13b78c2042855dc4afae10 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix assembly parser handling of ranges in register lists.
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
RM/reg-list.s
|
| a08e255e1e47d732b31262a95a8ba810f85735c4 |
14-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 3bb43a829e03ed8ea671f5bc331772ef7afc3313 |
14-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139690 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 6a9795a4579bbc58826b32a623670935768cd8b8 |
14-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Add test case for PR10851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139689 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/invalid-VEX-vvvv.txt
|
| 13b8d1e396bc802038332d894d78b999ec067069 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Make use of Eli's FileCheck sorcery to improve this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139645 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 7782a58b87923cc293d4e4422729ac0a582bb5c1 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 12c7e90d369b4605aac0ddbd252231beacb2aabb |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb2 shifted register operands with RRX shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 58bbb81764ccd20d06018b407d2698e4f1ad0709 |
13-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 926785487d95e4b0afef2c375a06b41dd317e836 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix a failing ELF Thumb test. I _think_ this is right, but it's not totally clear to me what this test is doing. Could someone on an ELF platform check?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139549 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc-reloc.ll
|
| cd00dc6852d17aa24f667a1060d2de83cd6423f0 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-t2PUSH-thumb.txt
|
| fd92d2e106acfbf13ed29b5d15f3a690cd8699b2 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative LDRSHW with an immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a3157b402695ef9d5f6a03e8e3afc5bddf3a3df7 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 136046c9a2dcb9b5bf539e6c6fcf100c68f9e621 |
12-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 038197988bcd7619657633da7116c7292187d4ae |
11-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 842f58f9be82e1a0d2751e7982ef3641829acf87 |
11-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 1ad60c2adc9ed765a968747d0c548cda53bfd384 |
10-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for MOV(immediate).
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 921d01ae1ff4e1dad2daeed22f8259a7a520412f |
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
LDM writeback is not allowed if Rn is in the target register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDM-thumb.txt
|
| 08fef885eb39339a47e3be7f0842b1db33683003 |
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
isassembler/ARM/thumb2.txt
|
| 51f6a7abf27fc92c3d8904c2334feab8b498e8e9 |
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 468709e43dfff52f48af9ff411d461e22b6e2015 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MLA and MLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 84d043a8b38d43a16549ca7e7cc9b275b2fa3aea |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139397 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 1e0fff17f3182a2bef5e06cca996a8d16e53cb46 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 95102265a96104512abbf0d8e316a1ef8473b994 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LSL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139395 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d4b72de3e2c9bd2397f37272c0904c53036e38d4 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139393 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 56806c29973a801a8311b5501c05a0a49651b42f |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSHT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139392 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a315a9909387cdf8ce36077d7aa91844caa2f19d |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139391 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 578edfbfa072a82ce22790567d3db434710e7551 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139390 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0811fe13d65c67e4c22d9113795deabbd0daa277 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 95d397c3b1e5001e5b25b04c52c13a19ec379c2f |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139386 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 1efd9a0e8b01abf3b3d7048a80c08599f7d3eefd |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139385 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e3a0adf162a849c7dd01514d151651850451db38 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139371 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d3be6ecafec0068e70d034f6467b1d6acf1cb806 |
09-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Add disassembler test for Intel syntax. Tests r139353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139356 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/intel-syntax.txt
|
| d2fc31b3f75700dc89305cb161f3bca7f1a39bef |
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-IT-CBNZ-thumb.txt
|
| a77295db19527503d6b290e4f34f273d0a789365 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
|
| 5afc19002e7a6b949619a5073d8c746985e8d6f2 |
08-Sep-2011 |
Kevin Enderby <enderby@apple.com> |
Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom
without a base symbol that must not have a relocation entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139316 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-nobase-relocs.s
|
| 9ea33b0c03e5c0a66b9d8385e164362b186513b1 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for Thumb2 LDRB indexed addressing w/ writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139292 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| e64fb28da191bc978ab99ea397e6108a15c364f8 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR post-indexed.
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| eeec025cf5a2236ee9527a3312496a6ea42100c6 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f0eee6eca8c39b11b6a41d9b04eba8985655df77 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 489c693f65521649dbee0378dbb465029d71c712 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRB(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139266 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| ab899c1bcca7f1cc85342c3a686464ba4af035df |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8bb5a861a0efae6b9c8f07936ad9bb3508ada23e |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 1aedfb47f96a396e8364ec41c94ee75db84d769e |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR(literal).
Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139257 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8a83f71301fdf0e2cea8ecdf413f192ac48ddc5c |
07-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| ed1cb6defa02d92302288410c35464c764adb060 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for Thumb2 LDR(immediate) from r139254.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139255 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 94f914e3fd4b040edd81abb5f455ed2b99e2572a |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDMDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a5d585685493d85d5cb72b831a68ec747ae55a86 |
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/invalid-VQADD-arm.txt
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
isassembler/ARM/invalid-t2LDREXD-thumb.txt
isassembler/ARM/invalid-t2STRD_PRE-thumb.txt
isassembler/ARM/invalid-t2STREXB-thumb.txt
isassembler/ARM/neon-tests.txt
isassembler/ARM/neon.txt
isassembler/ARM/neont2.txt
isassembler/ARM/thumb-printf.txt
isassembler/ARM/thumb-tests.txt
|
| 90502888f222c10f351def6dafb8560411b680d3 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for 139243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139244 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 76ecc3d35b4d16afb016bb14e29e12802b968716 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDMIA.
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 6de3c6f1a926f49cca2fd207ab4eeb6c35e0e068 |
07-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| aa833e53dc74db6cb6789ef7f05c620d28980983 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ISB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 8f6d8104fc20550da00c3a4a0bc66de64117826d |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for EOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139199 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 94d1c489a5f75f6092de413f7891449008ed91fd |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139194 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 06c1a51241852bd652ae6473afaa71d96d48b0eb |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DMB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 77951908b76c00315f1a74d09fb45530029638ec |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DBG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| ef88a926778b15aa4527a148a514ed0585af7cb1 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CMN and CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0b533a3bd39471d6dce5a4495f25323a0bb515e0 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139177 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| ad2dad930d450d721209531175b0cbfdc8402558 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CLREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 39950595f76e0a787e7373de7d1fd5039832f8e2 |
06-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more encoding tests over to Thumb2 decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139171 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 79d56a66c3d763b3a8147581c75c184cd48abcdc |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CDP/CDP2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139168 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 83452b206459f56454443b4caffa2e5bf1422def |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CBZ/CBNZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139054 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 6c3e11ea55172def6f9829cc24cc5c3b071208ba |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BXJ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| cefd2020a671248b3266bc2e818645db98f3a1d9 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139052 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0b9a3d37c5a6c452b40beede7519be97cad97ef0 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139051 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 7413f41d3b45d9fe851943d110a5ef5a54a5e076 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139050 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a110988b391652e3f4f85cb709a3eeb81c8cdd84 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding of B instruction.
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 5f25fb01b4061725124e34a942809e9c0c6f681c |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ASR.
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| d5705fe50d58dd2b686b26d1683315f785246ce0 |
02-Sep-2011 |
Kevin Enderby <enderby@apple.com> |
Change X86 disassembly to print immediates values as signed by default. Special
case those instructions that the immediate is not sign-extend. radr://8795217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139028 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 5c1ac5554229d5481b772cb017139bdd24d5114d |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for AND (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| f0851e5d95a1d1f746a3b1e9633af76496e316e7 |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADD (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 98f213cd60f21437846ce4075c0fe15d7f09a3fd |
02-Sep-2011 |
Kevin Enderby <enderby@apple.com> |
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
|
| ca52a7e38c0bcdd1a8f32212239606fe1f5e3152 |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tests for Thumb2 AND (immediate) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139013 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb2.s
|
| aca878c5e6d8ed34e436f4a4ec3b4e4dff3616db |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME. Thumb2 ADR encoding choice is non-trivial.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139008 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 5ffedb9352ad24f50fa647153dcf04af4e84dbb1 |
02-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 2f25d9b9334662e846460e98a8fe2dae4f233068 |
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 7f17b5a483ea358f2b9e3958f16cf34d75d5b4da |
01-Sep-2011 |
Owen Anderson <resistor@mac.com> |
t2Bcc is allowed to have a predicate without a preceding IT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 20ed2e7939d6a8e804a51897c3af4588deb48be2 |
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ADD(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb-diagnostics.s
|
| 721cb1fde07423fd1905338d443172a8028ad634 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding for tBcc with immediate offset operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| e0e42bf0bb1280a881450027aaae6490b4c87fd5 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Run the Thumb1 parser tests in Thumb2 mode, as well.
Thumb2 is a superset of Thumb1, so all of the encodings should still work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138883 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| d82175c1f03e6a83b4dbe53f884f72a2441d5c34 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb NOP encoding varies depending on ARCH revision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138876 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-nop.s
|
| 559c277aa9242dd5b32d2f2ccc353d938f886ee9 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 72335d55d972dd7279fe68ed05fa3c4e7fce9345 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADC(register).
Also add instruction aliases for non-.w versions of SBC since they're the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 0f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak Thumb1 ADD encoding selection a bit.
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| eaca928a3798e1fa7072457b94eccdd5b53b5d5f |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 21df36c57afc588c8073a070a47e3ba45fa87270 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| a7710edd98d71a81c43f8e3889cf0c790885d1b8 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 391ac65377f2ad5e48a796e75120959e22430605 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 3318d9c27d5cf4ea7af062ce3a407a06dd3bbe27 |
30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port Thumb2 assembler tests over to disassembler tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138822 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb2.txt
|
| 3daa5c29d444a759a0c60656d1aaf2579e5e447c |
30-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 694e0ffb8aa3a8651003e448135aba0e663782bd |
30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add missing encoding information for some of the GPR<->FP register moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| abd3f6085998e7479cf474d7352c6e1394bcbb68 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant tests from XFAIL'ed test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138779 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| a01e12499f0e9dd0c5dec0650e817a009cdd1238 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding support for ADC(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138778 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
|
| 056cb4c0f63fc7bdb5d5378baec2efeb95efc0b6 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove test file. Superceded by other more exhaustive tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138777 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2_instructions.s
|
| f8e1e3e729473b8b2b7ee6134b6417976af84d05 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb2-instructions.s
RM/thumb2-diagnostics.s
|
| fff64ca9cfdcb8e2fd2e124fcda1c1053523afc6 |
30-Aug-2011 |
Kevin Enderby <enderby@apple.com> |
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
|
| 0da10cf44d0f22111dae728bb535ade2283d976b |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/simple-fp-encoding.s
|
| 63553c77cd1cf3b204d955fb65350db087aaff1d |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| f1eab597b2316c6cfcabfcee98895fedb2071722 |
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/basic-arm-instructions.txt
|
| d7568e1c355f5e364eddafc15c6d5553559f32a5 |
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct encoding of BL with immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 9ab0f25fc194b4315db1b87d38d4024054120bf6 |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDR_PRE-arm.txt
|
| 96425c846494c1c20a4c931f4783571295ab170c |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/basic-thumb-instructions.s
isassembler/ARM/basic-arm-instructions.txt
isassembler/ARM/thumb1.txt
|
| 5a18f20dab483ed20b67252a2eba4e5a5bd71cca |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add a testcase for r138625.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138626 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-IT-thumb.txt
|
| 8fd13b6de51186ba38c69c4043fc7288a6fc6b8b |
26-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of VCVTSD2SI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 99906830e82cf70dbcbed22237c7bd24f9d9ffdb |
25-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 113061d39b32ac2652d237abff7ee5a2a45d45c9 |
25-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| ea03659d2340725c157f1eb0950a1cae08a122c3 |
25-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 5fbe5e783ee0c5ae27c17490a752d7e603e84ed2 |
25-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some autoconf tests use module level inline asm to test compiler's handling of
.cfi_startproc. e.g. libffi:
$ cat confopt.c
asm (".cfi_startproc\n\t.cfi_endproc");
int main () { return 0; }
Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.
rdar://10017184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138504 91177308-0d34-0410-b5e6-96231b3b80d8
achO/debug_frame.s
|
| 070260cb29ca9024d4fa1d3aabd6c8320b747f5e |
25-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Update tests for 138501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138502 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc-reloc.ll
|
| f69c80403620ef38674e037ae2664f1bbe5a4f3c |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SUB (SP minu immediate).
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 72f39f8436848885176943b0ba985a7171145423 |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| ddaa513fceb7eaf5efb00692c50f75ef241a4115 |
24-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port over more encoding tests to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138441 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 99e84e07ff94f24fdbd05f21d4cf5afb822542fe |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for WFE, WFI and YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138364 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 3284db5bfbd313da3492bcae36cbe7305071c05c |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for UXTB and UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138363 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 010bebc696156eb4fe346c0d3566fb855ddfc937 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138362 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 4b6658dd0a15fc81f117e672ed1eb72720615d13 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SXTB and SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138361 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| ec8b866434d530dee5b885e9db8da86db053c9ff |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| 414b02357a7a733e3258da1b7c0f2c12b32f193e |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SUB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138359 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 743c0fa7791c1451016a469bb0a5f57d56cd986a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138352 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| aec3a61c8b3fb3fbcafcc493ef38a37e39f039ab |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138349 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 803b1aa8ef00698de62181b9205cfcc0ce6b0ceb |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 4c821d800a50251633c206b9fe42c99e12f3f511 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STR.
Not including tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138347 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| 1e84f19337d44c04e74af4fb005550b525ef60e5 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| 82265a2c72b0f2d0daeab4985c9509d8405f51ef |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| e732cb004379a75efd6d1fd466dbea4cf249de28 |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138337 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| b4ff9698bd72eceedfe6a9c116713cbc0d97e6bf |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port more assemble tests over to disassembly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138336 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 7e99b5c8a36e3e8d611e47122f9c596b58ccf3e8 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SETEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138312 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 04d55f1905748b0d66655e2332e1a232a3f665f4 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SBC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 934755ac040c516eac7fdd974e87590543acd16a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for RSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 3f57a9a2cf375fe54c274e1e52e2b743d452ffac |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for ROR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138304 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| ab585e61464f4b1bcbc01d61d08a7d87c227997d |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for REV/REV16/REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138303 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| c6788c83b491b502482bf7d9a06b403d07f9e77e |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
t2SMLAD is a four-register instruction, not a three-register one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 22d35086fec34fa106d844b9b2204d7c3c20d8bc |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct operand naming of t2USAT16 to allow proper decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 2379fc235f8979f7f1218523672a19af1505e29d |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Match operand naming to allow correct decoding of t2LDRSH_POST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 6dcafc0d0b33bebcac28539257a9a5b250542f6a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve error checking for tPUSH and tPOP register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| 762f70bc49b75fa64a79b4ec87e474253418a5a1 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138293 91177308-0d34-0410-b5e6-96231b3b80d8
RM/reg-list.s
|
| 2c9f83533baa8802ab1d600fd76854125af53076 |
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 0c2165bbd096d49c17562c2951cecca582e01c75 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for PUSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138290 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 10fd9ad8f33815cdbdc0e2db5860f9c5b1954040 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix think-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138288 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| 7260c6a4ea19f5eb94068296c1c8e01a99f17a01 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assemmbly parsing diagnostic improvements for LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| d937d951256372a24eb6ac9f048816b0873ed528 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for POP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138286 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 838130e3b97c2fa77fb9b89eabbdf149d8e519f1 |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138273 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 357ec6850be0dff0038ea3a14f16066705284c0b |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 2cbf2104507c855850b610ed910536058aa0c6ee |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| f1c8e3e70e222365b84f4cb7e87396ee85820711 |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 88b7ccc7f0666fac2564518504a71ee471e62d82 |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port another swathe of Thumb1 encoding tests over to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138250 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| b113ec55e897c85fda606409c1eedec4f89ec53f |
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 011af5ca801cb95117a9abe2b217f78e2a7c8899 |
22-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138245 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| fbe1681490f4386a351e385129f2c3bce516adbc |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix AsmParser binary precedence for shift operators.
rdar://9976729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138208 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 2f4bdc5db92fbf5fd54c3067bb41d47aa3141ddd |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138207 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 0780b6303b99441fef04340b7a083006484f4743 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb.s
|
| 2c3f70e5d4b4f179f21ed1b2ba14674f9d65c9b0 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for NEG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 7a010694209ce46c4f415c0b42c3bc03dc094a5c |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Be more lenient on tied operand matching for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| 0c9acfcb50a844eefe92556e59c81fc302f32d1c |
20-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Re-write part of VEX encoding logic, to be more easy to read! Also fix
a bug and add a testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-avx-encoding.s
|
| c4762a9c912802ef6e81b722ccb7417f259bb49d |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138109 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 88ae2bc6d53bbf58422ff74729da18a53e155b4a |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| 584fb0e6635535130ce321d5af15530a7c2ff05a |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138077 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 4ec6e888ec6d12b5255afd685b05c8fee1f7fc73 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| c7ebca335d841247721128b75f0bc2b98ad6acc0 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138065 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 560ef9f2fe5f0fe0f8603ab3d076dae088efa6de |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSL(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138064 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 1b7b68f08776dc9553399dc3b4e7ab54e5e596c0 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| 05b01567349dc6c98f9e68c1d4a639aca7ad5ac4 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRSB and LDRSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 38466309d5c8ce408f05567fa47aeaa3b5826080 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 09f6e0dfda121251c5da7dba04b8b72d5572b0df |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138056 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 67b95f902a51b591b6178e370d23ffaca841275d |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(literal).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| ecd858968384be029574d845eb098d357049e02e |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(immediate) form T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 60f91a3d9518617e29da18477ae433b8f0069304 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(immediate) form T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| e004d941ec999e0c34772f079e430efe95b0dd9c |
19-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 863e0f25b7b53f6c7f43cdb8a0b900003096595e |
19-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
implementation!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-avx-encoding.s
|
| 78affc9ea1978d707b376180ec559b62fbf9ea05 |
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 846dd95f87f62e2faa6092f99b521ecd9790121a |
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 14090bf2636edf5e46a2c12a312b1889f5335d7d |
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-CPS3p-arm.txt
|
| 93b3eff62322803a520e183fdc294bffd6d99bfa |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
isassembler/ARM/thumb-tests.txt
|
| 847a7ad8003aee177ed93a83c77c0e062fc46a34 |
18-Aug-2011 |
Owen Anderson <resistor@mac.com> |
More Thumb1 decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137974 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 1eba8a66b62e74cc560949ccb0fd9b8af7276aea |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for EOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137964 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 0d1511c022e78e6d8769290b451b98a3b656de63 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| dbe46744c5bbf3c6d8fdfc52f18c6bdee8c37eb4 |
18-Aug-2011 |
James Molloy <james.molloy@arm.com> |
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137960 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRD-arm.txt
|
| 7750b8df6aaf9182b8205b98c335bf0f0b19e1b6 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding test for CMN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137957 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 7cf6d7a083ab096f7aea4c0cbf24ff028a3000c6 |
18-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port over BL/BLX to disassembly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137954 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 6ea80e964ba0f8a3420b10bf21172508f713fafc |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BX/BLX (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137949 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| ded439886aa0a96df55820e6f84342210660e0f4 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BL/BLX (immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137948 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 3230e9537de3e15573a36ebe850f729b5ef74741 |
18-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port new Thumb1 encoding tests over to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137902 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 37f88c7812e4c284bde325e5af583889b6a80fc5 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BKPT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137898 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| 5b657de62ba6e7a7dd873b7a5d10e146b3e35f53 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137895 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 395b453bed53a60c559b679eb92f75d0b140b307 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for B.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 00f5d982057574cf65a4a3f29548ff9fb0ecfbd0 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ASR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
RM/thumb-diagnostics.s
|
| 5a1cd045cd4220f84dae81ab2079e2272dfc51c1 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137864 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 53727fc659af5f8fc51499fd875165533187d734 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add a couple of FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137861 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 4c81cf5dfc8f790fa7ab0169b926bd83ea3ca6b5 |
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137840 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb1.txt
|
| 358499ea3b72dda4392d340ee5a36d1bbe76728c |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADC(register) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137833 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| b1ee18ee69624d51211e59fa42b54a0f5827318a |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add missing '@' delimiter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137832 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 83e3f67fb68d497b600da83a62f000fcce7868a9 |
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRB_POST-arm.txt
|
| 89e2aa6afd408f1b4c6b47c53bbf31d48463bcab |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb ADD(immediate) parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| 194bd8982936c819a4b14335a4d08f28af8f3d42 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| 3912b73c74dc9c928228504e9a23c577b57c4e12 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADD(register) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-thumb-instructions.s
|
| c2408d3ce5fcd1fd4861772fdbe3b6447836e254 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add testcase for r137746.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137754 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb-diagnostics.s
|
| be2ac8ca7bc02f9139c6f8de1ab1db3df743d969 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137747 91177308-0d34-0410-b5e6-96231b3b80d8
RM/mode-switch.s
|
| 47a0d52b69056250a1edaca8b28f705993094542 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM thumb assembly parsing for arithmetic flag setting instructions.
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
RM/mode-switch.s
RM/nop-thumb-padding.s
RM/nop-thumb2-padding.s
|
| d0d3f7e01ff7f83575816f6e1d75aa2224ebc2cb |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
RM/nop-armv4-padding.s
RM/nop-armv6t2-padding.s
RM/nop-thumb-padding.s
RM/nop-thumb2-padding.s
|
| a9c989d55a10fa4ebacc0b8d84e3daca9e5d01d8 |
16-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add a test file for Thumb2 NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137687 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neont2.txt
|
| 1deddbbd5659edc92028c2278018d21375ce3c81 |
16-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reorder declarations of vmovmskp* and also put the necessary AVX
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137684 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-avx.s
|
| c4bda5633a4ebdef9871a35aea13ee54c339be1a |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add some more comprehensive VFP decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137657 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/fp-encoding.txt
|
| c537f3be0c4ff7030afcdcd9f55133ce68eef773 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/memory-arm-instructions.txt
|
| 95d01b88987699efd2059f9969ba8a76422242c5 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add a test for Thumb1 LDRSH decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137645 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| bd37b721c84f33cb23683dc81dfe13b43399e5c8 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add testcase for STRH. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137644 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 5df7ef6cdbdaaa6bf3bf12b959557a44fbf250a6 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/basic-arm-instructions.txt
|
| 305e046e539a2713190be6de5ffb3f57708ef45f |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 7a2e1770ead7c2e3b7292ae466a41b560f3d272c |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon.txt
|
| 0d09499cf3e2d927cdc53ec79895303ac12808ac |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/memory-arm-instructions.txt
|
| a211c2c7e974908dcf18838f07d85cc65a7b5e0f |
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137495 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/basic-arm-instructions.txt
|
| 7a8729effc8e6f825cb87e0f95e25b1861bebc1f |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137471 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-dup-encoding.s
|
| 46c38aff89c36a95bc9e61c6133056a5de9e5e59 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137464 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| 0d46ccfc5c2f5d0894e340907f6e58067cce5b03 |
12-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137414 91177308-0d34-0410-b5e6-96231b3b80d8
achO/x86_64-reloc-arithmetic.s
|
| 29e7b7deb4d582926299c9e69d59e7be45e6ef75 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up formatting a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137393 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.s
|
| 857e1a7b3fcc848a6508f9205f22e8e0d293dcae |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vector compare to zero instruction assembly parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.s
|
| c69c26d95e4dcffb3ab98c49f3672386b401d0f9 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix tests per now-correct encoding as of r137371.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137376 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 342ebd5f380637d965504dcc350f9d0d79bbe599 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| dd32ba337aab88c215108ca8bf4a0267fce1e773 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load shifted register pre-index fix shift value asm parser encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 2ef8241ce7898d49f882e2124064ea953bf9f512 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137358 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 7b8f46cf9e31d730acc25be771462e2a6a1a1dfb |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 508e1d3db536b736063385eb1f885b446a1385ca |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 9fe72bcd3714d136b371aa85d293e16363c29914 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve operand validation for Thumb2 addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-t2LDRSHi12-thumb.txt
isassembler/ARM/invalid-t2LDRSHi8-thumb.txt
isassembler/ARM/invalid-t2STR_POST-thumb.txt
|
| 14605d1a679d55ff25875656e100ff455194ee17 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRD assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 26d2f0ac919f6ae868fe901fd4ad64af6f92da4d |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Continue to tighten decoding by performing more operand validation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MSRi-arm.txt
isassembler/ARM/invalid-STMIA_UPD-thumb.txt
isassembler/ARM/invalid-STRBrs-arm.txt
|
| 10348e70d567fb61f6c762d99e91e215c720ebd1 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 961afdf1b641cfa9ed66a6705046393e1dea8847 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137336 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 534de6cad8654af30982edde7dc59d9472a6d2f6 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRB assembly parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137335 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| c15bd92d2f4beba90b991d10f6df2f74f8cd8f1e |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix a copy/paste error so that LDRB(register) actually gets tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137333 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| f91c14920c8cb66195380b5f83e8a98852bedd6a |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(register) assembly parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137332 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 548340c4bfa596b602f286dfd3a8782817859d95 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(immediate) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
RM/basic-arm-instructions.s
|
| 71156a6e00d3dc4c531a421a76b3b6ee0ae7d0ab |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRB_POST-arm.txt
|
| 2b7b238e843cbbe0682a3cc001fe514f4270a984 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDR_PRE-arm.txt
|
| 3dac0bec7e7874ffb378385b6160bd2117184ca9 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| ae0bc5deaa30f1e20a6189e42ca412ba27ec7153 |
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve error checking in the new ARM disassembler. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
|
| f6713916fb4504aab617f0e317689acd878cc37f |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| f8fce711e8b756adca63044f7d122648c960ab96 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 64104f48f23ff46538e46f01c076fef2ff55d97f |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137274 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| e0109c07ff2861cbfbcbcd0ff69acd420c82ca9f |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137272 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 7d179b59cd7ae2594ef9f25e0b8369ad98f97386 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137271 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 5e921594007c4f8b587b8bf15825af0fe8998497 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSB assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137270 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 263bb07135bc34982fca7efc7c4ed56abee21281 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137265 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| de2f526c7cb2acd0447b59f3def40d35c8bc80f7 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137263 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 46b355479f6e2da25bde2df09874c5da690ddd3c |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRH(register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137261 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 623a454b0f5c300e69a19984d7855a1e976c3d09 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRH(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| c7de52fcff2d8021fcd68c97cdbf2010b7068e47 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137258 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 251bf25e7ee9702fed2a66deeb404ce473f7bac1 |
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 2fd2b87ded53f6b87eb240c17d62a23fb4964ba0 |
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
RM/diagnostics.s
|
| 8533ebad6f6e407215497ca50771f323058f5576 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add initial support for decoding NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 33e57515b173baf572398fafeffcf4644c2a7381 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MOVTi16-arm.txt
isassembler/ARM/invalid-SBFX-arm.txt
isassembler/ARM/invalid-SMLAD-arm.txt
isassembler/ARM/invalid-SSAT-arm.txt
isassembler/ARM/invalid-SXTB-arm.txt
isassembler/ARM/invalid-UQADD8-arm.txt
|
| de317f40f7a9962372adea162a12ec35a628efa1 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking of register-shifted-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LSL-regform.txt
isassembler/ARM/invalid-RSC-arm.txt
|
| c36481c4744cdbddec91dc3eca9245acaf2982da |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking on memory barrier instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-DMB-thumb.txt
isassembler/ARM/invalid-DSB-arm.txt
isassembler/ARM/invalid-t2Bcc-thumb.txt
|
| 35008c2f8dcfe55960fe4efea3a26e526d437ad6 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking on CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-CPS2p-arm.txt
isassembler/ARM/invalid-CPS3p-arm.txt
|
| 51c9805c4bcca635bc6a854e4a246ebd4258f512 |
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-BFI-arm.txt
|
| 793b811c5057365d847b7f9ae326358e76facfe2 |
10-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM Disassembler: sign extend branch immediates.
Not sure about BLXi, but this is what the old disassembler did.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| bd9091c18d85d6649763165c4951d7b5ff2e31a9 |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten Thumb1 branch predicate decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-Bcc-thumb.txt
|
| 8d7d2e1238fac58c01ccfb719d0cc5680a079561 |
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-BFI-arm.txt
isassembler/ARM/invalid-Bcc-thumb.txt
isassembler/ARM/invalid-CPS2p-arm.txt
isassembler/ARM/invalid-CPS3p-arm.txt
isassembler/ARM/invalid-DMB-thumb.txt
isassembler/ARM/invalid-DSB-arm.txt
isassembler/ARM/invalid-LDC-form-arm.txt
isassembler/ARM/invalid-LDRB_POST-arm.txt
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
isassembler/ARM/invalid-LDRT-arm.txt
isassembler/ARM/invalid-LDR_POST-arm.txt
isassembler/ARM/invalid-LDR_PRE-arm.txt
isassembler/ARM/invalid-LSL-regform.txt
isassembler/ARM/invalid-MCR-arm.txt
isassembler/ARM/invalid-MOVTi16-arm.txt
isassembler/ARM/invalid-MOVr-arm.txt
isassembler/ARM/invalid-MOVs-LSL-arm.txt
isassembler/ARM/invalid-MOVs-arm.txt
isassembler/ARM/invalid-MSRi-arm.txt
isassembler/ARM/invalid-RFEorLDMIA-arm.txt
isassembler/ARM/invalid-RSC-arm.txt
isassembler/ARM/invalid-SBFX-arm.txt
isassembler/ARM/invalid-SMLAD-arm.txt
isassembler/ARM/invalid-SRS-arm.txt
isassembler/ARM/invalid-SSAT-arm.txt
isassembler/ARM/invalid-STMIA_UPD-thumb.txt
isassembler/ARM/invalid-STRBrs-arm.txt
isassembler/ARM/invalid-SXTB-arm.txt
isassembler/ARM/invalid-UMAAL-arm.txt
isassembler/ARM/invalid-UQADD8-arm.txt
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
isassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
isassembler/ARM/invalid-VQADD-arm.txt
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
isassembler/ARM/invalid-t2Bcc-thumb.txt
isassembler/ARM/invalid-t2LDRBT-thumb.txt
isassembler/ARM/invalid-t2LDREXD-thumb.txt
isassembler/ARM/invalid-t2LDRSHi12-thumb.txt
isassembler/ARM/invalid-t2LDRSHi8-thumb.txt
isassembler/ARM/invalid-t2STRD_PRE-thumb.txt
isassembler/ARM/invalid-t2STREXB-thumb.txt
isassembler/ARM/invalid-t2STREXD-thumb.txt
isassembler/ARM/invalid-t2STR_POST-thumb.txt
isassembler/ARM/neon-tests.txt
|
| 3148a654909e55e8511a1c23991bf0ae8d3f9204 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| bc6fc20fcc94d5492a5e5604137a46fd9cffb040 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for LDRB instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 8668a5b0c86ba070176a76accfd48586c0442399 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 0d6fac36eda6b65f0e396b24c5bce582f89f7992 |
06-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| f4fa3d6e463e88743983ccfa027a7555a8720917 |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 6fc1c08635a6bdd6caea234b756f0dd62581e73c |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add ARM LDR parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-memory-instructions.s
|
| 5c4e52e49648c196f629b8623b4aca7e4c0080e3 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix the bitwidth of the remaining fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136884 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias-reloc.s
LF/align-bss.s
LF/align-nops.s
LF/align-size.s
LF/align-text.s
LF/align.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-offset.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-same-value.s
LF/cfi-sections.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/comdat.s
LF/common2.s
LF/debug-line.s
LF/debug-loc.s
LF/diff.s
LF/empty-dwarf-lines.s
LF/empty.s
LF/entsize.ll
LF/entsize.s
LF/ident.s
LF/leb128.s
LF/merge.s
LF/n_bytes.s
LF/noexec.s
LF/norelocation.s
LF/org.s
LF/pic-diff.s
LF/relax.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/section.s
LF/symref.s
LF/weak-relocation.s
LF/weakref-reloc.s
LF/x86_64-reloc-sizetest.s
LF/zero.s
|
| 251a2bbfb00ceb254d7ac1d35ae975ad9e2145cf |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
print st_shndx with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/comdat.s
LF/common.s
LF/file.s
LF/local-reloc.s
LF/merge.s
LF/noexec.s
LF/pic-diff.s
LF/pr9292.s
LF/relocation-386.s
LF/relocation.s
LF/rename.s
LF/set.s
LF/symref.s
LF/tls-i386.s
LF/tls.s
LF/type.s
LF/undef.s
LF/weak.s
LF/weakref-reloc.s
LF/weakref.s
|
| 67ac0c0d630aa823f31632beecef520df1d7c48b |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
print st_other with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136877 91177308-0d34-0410-b5e6-96231b3b80d8
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/comdat.s
LF/common.s
LF/file.s
LF/local-reloc.s
LF/merge.s
LF/noexec.s
LF/pic-diff.s
LF/pr9292.s
LF/relocation-386.s
LF/relocation.s
LF/rename.s
LF/set.s
LF/symref.s
LF/tls-i386.s
LF/tls.s
LF/type.s
LF/undef.s
LF/weak.s
LF/weakref-reloc.s
LF/weakref.s
|
| 71a8f5ca12e8536e6050cc7a09fa2a87ea629cfa |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
print st_type with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc.s
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/comdat.s
LF/common.s
LF/file.s
LF/local-reloc.s
LF/merge.s
LF/noexec.s
LF/pic-diff.s
LF/pr9292.s
LF/relocation-386.s
LF/relocation.s
LF/rename.s
LF/set.s
LF/symref.s
LF/tls-i386.s
LF/tls.s
LF/type.s
LF/undef.s
LF/weak.s
LF/weakref-reloc.s
LF/weakref.s
|
| d7c278326f333f41d8ec8d19f817a117e3f11190 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print st_bind with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc.s
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/comdat.s
LF/common.s
LF/file.s
LF/got.s
LF/local-reloc.s
LF/merge.s
LF/noexec.s
LF/pic-diff.s
LF/pr9292.s
LF/relocation-386.s
LF/relocation.s
LF/rename.s
LF/set.s
LF/symref.s
LF/tls-i386.s
LF/tls.s
LF/type.s
LF/undef.s
LF/undef2.s
LF/weak.s
LF/weakref-plt.s
LF/weakref-reloc.s
LF/weakref.s
|
| a83f8ef9b4d727011ee43743810ef1f6ec12bb81 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print r_sym with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-thumbfunc-reloc.ll
LF/call-abs.s
LF/relocation-386.s
|
| f81f6758f3188e1fd8be6b3707301959268dbbf0 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print r_type with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-movt.s
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-thumbfunc-reloc.ll
LF/basic-elf-32.s
LF/call-abs.s
LF/relocation-386.s
|
| 65ad8dc807174b53615181a8170befdf60b6771d |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Another counter goes decimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136871 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-thumbfunc-reloc.ll
RM/elf-thumbfunc.s
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/comdat.s
LF/common.s
LF/file.s
LF/local-reloc.s
LF/merge.s
LF/noexec.s
LF/pic-diff.s
LF/pr9292.s
LF/relax.s
LF/relocation-386.s
LF/relocation.s
LF/rename.s
LF/symref.s
LF/tls-i386.s
LF/tls.s
LF/type.s
LF/undef.s
LF/weak.s
LF/weakref-plt.s
LF/weakref-reloc.s
LF/weakref.s
|
| f7179de2a5c127d08e6d24e507abec516f2fc597 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change anther counter to decimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-movt.s
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
RM/elf-thumbfunc-reloc.ll
LF/alias-reloc.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/call-abs.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-offset.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-same-value.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/diff.s
LF/got.s
LF/local-reloc.s
LF/merge.s
LF/pic-diff.s
LF/plt.s
LF/relocation-386.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/symref.s
LF/weak-relocation.s
LF/weakref-reloc.s
LF/x86_64-reloc-sizetest.s
|
| 014180d387a875f7e04fd3532eab24dd0794db08 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't print a counter in hex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136869 91177308-0d34-0410-b5e6-96231b3b80d8
RM/xscale-attributes.ll
LF/align.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-def-cfa-offset.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-same-value.s
LF/cfi.s
LF/comdat.s
LF/debug-loc.s
LF/empty-dwarf-lines.s
LF/entsize.s
LF/local-reloc.s
LF/merge.s
LF/n_bytes.s
LF/noexec.s
LF/relocation-386.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/section.s
|
| d7c9b63b583ac05fc03c9a242c1bb8f12d27acf0 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print all the bits in the addend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136867 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias-reloc.s
LF/basic-elf-64.s
LF/cfi-adjust-cfa-offset.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-offset.s
LF/cfi-rel-offset.s
LF/cfi-rel-offset2.s
LF/cfi-remember.s
LF/cfi-same-value.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/diff.s
LF/merge.s
LF/pic-diff.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/symref.s
LF/weak-relocation.s
LF/weakref-reloc.s
LF/x86_64-reloc-sizetest.s
|
| e651983e71a0fbe624a1441dfc8b747ca1a038f1 |
04-Aug-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Fix http://llvm.org/bugs/show_bug.cgi?id=10568
Move the reloc size assert into AsmBackend - where it is more apropos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136855 91177308-0d34-0410-b5e6-96231b3b80d8
LF/x86_64-reloc-sizetest.s
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode3.s
RM/thumb2_instructions.s
isassembler/ARM/arm-tests.txt
|
| e1cf5902ec832cecdd5a94b9701930253d410741 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
isassembler/ARM/arm-tests.txt
|
| 2c6363a62df95b74468d9a561bbcb9edddeb3507 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 71d3d67508176091575714dddf008b77db4089c9 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM update tests for CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136472 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| c5b3c58ae8f954587bbb651dec7990744a29f12d |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136408 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| cf121c35c484ee17210fde1cecbd896348cd654a |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 43afb6ff1cf7b040e2d70abb47679e1357a329d5 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove obsolete FIXME reference in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136400 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 293a2ee3063953bb6f5bc828831f985f054782a3 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 70a0915cd135b48c557a5bc81b37e33f54fe150e |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 19b9d6912ab4d61666d5eed0a9c7d407d564ce1d |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136358 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 8050a619145f30cdfee9c6ae1c5bdb1a32a4a71e |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests.
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136312 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 5de728cfe1a922ac9b13546dca94526b2fa693b6 |
28-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
86/3DNow.s
86/x86-32-coverage.s
86/x86_errors.s
|
| ed398468b51c6eb5b2c9a5bccc8669854cf589a8 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for USUB16 and USUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136289 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 953e2e81dec27fe40315100714eb15c967a9fc1e |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136288 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| c37d4bbf1f33c5e4b1c2f1bf1a6e2cae2ae5603a |
28-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-avx.s
86/x86-32-coverage.s
|
| fc2eb31a3c054f9611a2e88238fbb5a8842064a6 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136286 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| addec77b54fd77e99fd01f462a3fb8c3c89066fa |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 5f33d13da41f55e7421eee3bbfa410d07bd7af19 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for USAD8 and USADA8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136284 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 144da2c8f03834e76ddb617498be7ed864a5c192 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136282 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 41438398c13be01ec53c3ad6b08a6cab47e96735 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix comment copy/paste-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136281 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 29e85bc7285337973924501cad7e7effafd91e65 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQASX and UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136280 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 24a541b79fb9694b6edf19ee288b7c9063653512 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 49f2ceddd25c75373f8a39fa25e8b9db33bcdacc |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 71725a099e6d0cba24a63f9c9063f6efee3bf76e |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 2adba4156b83bd005bb704908bb36697e1ecabda |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UMAAL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| f36b0a2ee4fe1e67778b60daf6020574e62ca672 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 66c898224456990e511b71e498046736c0478079 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| b6854ad2b1aad78660e7a3421d9c0dbdeaa3c975 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 8b3fd56e0f61038ea45b0d1eaff57196d80579aa |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for TST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| f1ae78af1796ec122e3cf75ab4826495eb5a4e8d |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for TEQ instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 06470311c574da4f83f91400234a1e1fc4c9ea1b |
27-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| 7e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 189610f9466686a91fb7d847b572e1645c785323 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostics for ldrexd/stredx out of order paired register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| 36711e4a3c0b53000ea594233bd619dbf252558c |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for load/store exclusive instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 4f6f13db1a8a491ecab6af64549fbdc23cb5ba56 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SWP[B] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| ed8384806e56952c44f8a717c1ef54a8468d2c8d |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 873db3eebae3cf1e0931149896f262d17a4dc79d |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SUB instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136089 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| a46c658c6619e979a54ec1e4dc919b3a0319129a |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM STM tests. Fix check: prefix for diagnostic tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 185f92e7d019bc52413a2b082d61e35c80f8b597 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136013 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| f49433523e8a39db6d83503e312ae55160eed90a |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9f |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| f2a35fbd60fbb86465ad2fb4d801cd5c240decd7 |
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Move some ELF directives into ELF asm parser.
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.
rdar://9827089
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135921 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| 6ab4e3dd2375c3dcee06dde37437dc0c5a99aa24 |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135819 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 0e76edf8c05c5107acb687b898fea686ae756c38 |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135818 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| bf2845c0d8a77d24e9971871badeba8cee7b2648 |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 6808f21757f4f2be05a3b12a67d9360b4f9f62e2 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests.
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135810 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 44a456332f1f41d1e0b2815d93e47a88d501ee6e |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135800 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| ce501030d9b0213d951fbf05f928ac75b06b5a3a |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests.
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135798 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| b544f68b70475f06a8ec39c874297549edc0f695 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| b206daaec1a2ec25e99fbdc413cd0866cec160b2 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 0ffd4a09dfb1ee56ec335fed0d15954f92cfa5b3 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for assembly parsing and encoding SMLA* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 7c9fbc0340aff9e20fd9009be23ffd279c1c0a7d |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 248e6c328c06afc2a6af6b95a1a8a41c1b53055c |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing tests.
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| c27d4f9ea0cb9064d3e2cadb384d73e95e9de449 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 9076b6e8f43c7eade7e0b667081f94df097e85c3 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SEL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 8409f047312da0318af2a2fce162810ca3a95da3 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for SBC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 8ae45af7941dc3e78859ba3624676081590c435d |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for SADD/SASX parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| f790193aec11747bb35206d2c79e0c5ffbc6dc7f |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 86fdff0fa79b2c00cb68a2961cca0466eb50d666 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 616fbdf987170addd0d8f75f4fd677589d54cd75 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135710 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| a4c34ab54485f64d3b962a499526825a7a0d4bbc |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encodings tests for saturating arithmetic insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 10c7d70a4e843b3006db9f5f583d6f6f56cc245e |
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 61b1b21e9ad2b8af163a352766eeb159979f4ff2 |
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM PKH assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| a4d0bd84f7bdc78784e44b623ded448988022e4b |
20-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
LF/global-offset.s
|
| 88d1bc832ca5b458c8460929227be8eae6c6bdc3 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add parsing/encoding tests for ARM ORR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| a67851445902d1fc01fa2a37a3dfc347af949f84 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Consolidate ARM NOP encoding test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| c3635c2e928a7ecde11398ff272411f6dea2dcd2 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for MVN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| ab40f4b737b0a87c4048a9ad2f0c02be735e3770 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| b29b4dd988c50d5c4a15cd196e7910bf46f30b83 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/thumb-tests.txt
|
| 80d01dd3d19a84621324ac444c6749602df7a513 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| ccfd9313d11aa29551f93fe99428946837c97729 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| 2317fe1584e02582c616c1c4d15954999ff5525a |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Move mr[r]c[2] ARM tests and tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 1a2be4db5b12cb7bfa351bcebd5e94b0decb021f |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for MOVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 5f16057d1e4b711d492091bc555693a03d4a1b6e |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| ffa3225e26cc1977d20f0d9649fcd6f38a3c4815 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_fixups.s
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 0ec2aa21d0286339961a5c331ca289751ab1396c |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135499 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_fixups.s
|
| 7105259ce8e9fd78ce9fc1b7a9aaab123fb5db64 |
16-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/x86-32.txt
|
| 5232cc675c59ac04df616c45158f15c3c166f5d8 |
15-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
PR10370: Make sure we know how to relax push correctly on x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 43967a97cf9a296623e1cf5ed643e2f40b7e5766 |
15-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| 33c16a27370939de39679245c3dff72383c210bd |
15-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| 70d8fcfaa04eb20541b006a8fb97cbc1d3033cc4 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some testcases for ARM MLA/MLS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| c8ae39e746a20dc326def0ccfc052df3e21f16d3 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| e540c7422ca13c950f0e8f6f93af7225bb7742a9 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 1134be2428f0f26314ae25020f0081b860a0084d |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable some tests we now handle correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135185 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 3b14a5c5469176effb921d91d4494f0aa2919fd0 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 791feea10071223886e2fe2bfa0e1f4cb2c0ce74 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB assembly parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 9dec507ecb212a7c94659e9b5a9da66cb4b39ea3 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 00a66653cbe56dfbdb831172b54097bf8256a191 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for EOR instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 6a86feafa8c26ffd4b9edb3a3eab946724842051 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove duplicate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| e77494e3e3da59afaa51d1bbcf732fa2851d865d |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 032434d622b6cd030a60bb9045a520c93b0d7d68 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 6f9f8845028d4d3b96c33417398034a71137d867 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 14ab1c3387a240a914cf8b1907bb3609bae72269 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for CMN/CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| d986bc66bc56251c2b7d5b9a89df14c4760568fc |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle ARM assembly tests a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/basic-arm-instructions.s
|
| 83ab070fc1fbb02ca77b0a37e6ae0eacf58001e1 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 9bb098ad3a3c93aec50a4a63e6894472727f8d88 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
RM/thumb2.s
|
| f333d471d2cdd47d830dfe3a3e40efbb106c100d |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcases for ARM assembly BX/BXJ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 37023b05c84000373fcfc0871edad3c2b995be33 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcases for ARM assembly BLX/BL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| fff76ee7ef007b2bb74804f165fee475e30ead0d |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
RM/diagnostics.s
|
| 21101d60ce94f51651f71eeb61ceb8264eccac83 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'BKPT' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 76cbe02cdd57a297d9c6f1e5106e4718abd7ff9f |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix copy-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| e52240c3705f3133eb8c4ebb4220054c68de2651 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'BIC' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 7ed6d22e9637c52b3511ac6907830251d1124e60 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some FIXMEs.
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 59642c260064a0c9140e048d702a21830020487f |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'AND' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 19906729a490744ce3071d20e3d514cadc12e6c5 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
RM/diagnostics.s
|
| da9f278c741e8ced7c1652720270918eb04ed348 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'ADD' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 37ee464ea98544d3ed84cec6dde5f769ce003d5f |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| e8606dc7c878d4562da5e3e5609b9d7d734d498c |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| dc89561fecf100d6c32d73c7b009fd73e51be688 |
12-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add check for predicate w/o S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 3f00e317064560ad11168d22030416d853829f6e |
11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
RM/basic-arm-instructions.s
|
| 589130fac11bc8c186736161600575c3ed6acc5b |
11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
isassembler/ARM/arm-tests.txt
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
RM/mode-switch.s
|
| 32869205052430f45d598fba25ab878d8b29da2d |
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add support for ARM / Thumb mode switching with .code 16 and .code 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
RM/mode-switch.s
|
| 39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
RM/prefetch.ll
|
| d7c7e2ff7d3305e4bc5634902ec4b8406e9cefca |
06-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134511 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| d521f2d2f1a866ba9f9e73ca566e2b486c15dc74 |
06-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| af45b3d8cb1b88d3cf775542996d78d8ce009274 |
05-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| ca0ede7655cbe126441dd13599eafdf442eff3a9 |
30-Jun-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize the xstorerng alias for VIA PadLock's xstore instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8
86/padlock.s
|
| 254cf03a45534ccfdcc7d223fbebc07d4a0562a7 |
29-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Asm parser range checking on .<size> <value> directives.
For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.
rdar://9686950
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134069 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs-invalid.s
|
| adf7366771ebc78b3eee3c86b95e255ff5726da7 |
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff
rdar://9672867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 6b8f1e35eacba34a11e2a7d5f614efc47b43d2e3 |
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| fbd01783a67dd2bedd8197308ef00d4ad767fcd3 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for ldmfd/stmfd mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 0d06bb954881dc7ff0e2333d5a3e249b7bb304d0 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.
rdar://9683231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
RM/vpush-vpop.s
|
| 0ff9220ccb6ef419ba4d3a4daf98f4658a9e5134 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly syntax support for arithmetic implied dest operand.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
sub r2, r2, #6
sub r2, #6
rdar://9682597
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm-arithmetic-aliases.s
|
| 75c2b2028bd898cb8448fcf0fa76c3d47843a164 |
25-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Move ARM-specific test to ARM directory.
Hopefully make the x86-target-only Windows bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133856 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2-movt-fixup.s
achO/thumb2-movt-fixup.s
|
| 56fc6420000876460e8c89c0e7c0ae83ebb5ccf0 |
24-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcase for r133818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133823 91177308-0d34-0410-b5e6-96231b3b80d8
achO/thumb2-movt-fixup.s
|
| a390a1aa48d8fa5085aa51b950f00d79dbb0c646 |
23-Jun-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for movntil/movntiq mnemonics. Reported on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86-64.s
|
| 94d4c91bc5b2a84e6b93250599b6742777dbd35e |
22-Jun-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add support for assembling "movq" when it's correct to do so, while continuing
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133565 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 38c892624bc66cad98a81e080d235f4e33122562 |
21-Jun-2011 |
Bob Wilson <bob.wilson@apple.com> |
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
86/x86_64-avx-encoding.s
|
| 1bd15700a0eb3057d3e2d65070c3fc6b99e0d8a2 |
20-Jun-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Emit movq for 64-bit register to XMM register moves, but continue to accept
movd when assembling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
86/x86_64-avx-encoding.s
|
| 5cc6491f50d0598715d87c69793bfdb2df7cda6f |
18-Jun-2011 |
Hans Wennborg <hans@hanshq.net> |
MC: Allow .common as alias for .comm assembler directive. PR10116.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133349 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_comm.s
|
| 393c4047c05b6d7b5851d339e51bb2cc35f630c2 |
15-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Improve the heuristic to emit the alias if the number of hard-coded registers
are also greater than the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 740e5b3586a474f1cea371cf6f652850e5420b90 |
14-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Heuristic: If the number of operands in the alias are more than the number of
operands in the aliasee, don't print the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| be234dabf4c58a40c2b063f2e3a8c6cb0ab73a3b |
07-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Test that ".byte 1, 2, 3, 4" does the right thing.
Requested by nbjoerg!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132716 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_values.s
|
| 653664471333f316020e96dd3d664f4984f66a65 |
05-Jun-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Basic support for macros with explicit arguments.
We still don't handle
* default values
* :req
* :vararg
* \()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132656 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-args.s
|
| e0b87032f5ac8134b7585bdc4a0f2c77158b962d |
04-Jun-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add support for @GOTPTOFF in i386 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132643 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 895c1e2deea3e6118b159c26b3f86d40a37e8501 |
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| 04507f062f5d61a298d82497db71eff0951b896c |
29-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use %rbp on a 64 bit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132279 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-offset.s
|
| 06a8d5496788ac74a69dc68680bad48ca1814b43 |
28-May-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move ARM specific test into the ARM subdir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132255 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc.s
LF/elf-thumbfunc.s
|
| be64b394317feb8d7bcb732bdfb35e0b286efd4c |
28-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| 88c816453fac630e23785dbd1755675d139603db |
27-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add the suffix to the Win64 EH data sections' names if given. Add a test for
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132220 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh-section.s
|
| 07cbe231738d64d830b77303d664b531130722f7 |
27-May-2011 |
Charles Davis <cdavis@mines.edu> |
Assorted fixes for Win64 EH unwind info emission:
- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.
Add a test for the latter two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132188 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| 3a5d7d0665e2c836fb7619ea1160b29c36827c4a |
27-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add a test for Win64 EH unwind information emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132180 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/seh.s
|
| 3ac7b034d65bb1b78795931287f634d4efd7e151 |
26-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add a test for the chained directives that I forgot last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132110 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_seh.s
|
| ca93138e11f404a19553049a569f1fa6ad491b67 |
26-May-2011 |
Charles Davis <cdavis@mines.edu> |
Test .seh_startchained and .seh_endchained parsing.
Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.
The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132106 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_seh.s
|
| 410ef2b263e92d3de1b2acff7437059400daed7d |
25-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with
them.
I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132084 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_seh.s
|
| 575630ccb8a267405146a0c14fba7a5b74e1e4c3 |
25-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the
buggy methods that parse these directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132045 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_seh.s
|
| 47268164f3d660f6357cc3a59d510efe3bc9152f |
25-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another
one I found by inspection).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132037 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_seh.s
|
| 309213279e5d95826d97b2ab2178db5ddea0ed80 |
25-May-2011 |
Charles Davis <cdavis@mines.edu> |
Add a test for the .seh_handler directive. Fix problems with the parsing
method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132028 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_seh.s
|
| 56926a39619bd644c83c4128f0b55189e52707d7 |
25-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR9762
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 40de0e013a456971697491b428fb903570e8766e |
24-May-2011 |
Charles Davis <cdavis@mines.edu> |
Test basic SEH directive-parsing functionality. Fix a latent bug exposed by
this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132004 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_seh.s
|
| d521d8bf923b2f4b3e44a4ae2ebd0dcb59d7b23b |
23-May-2011 |
Chris Lattner <sabre@nondot.org> |
add test from PR9164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131876 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| b8a21ad91556903d055bb1de47f75655ca4e9ba6 |
23-May-2011 |
Chris Lattner <sabre@nondot.org> |
testcase for PR9378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131875 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| 75f4296c7c96499f4d8cdf90d5159f7965f94fd8 |
22-May-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| b8adb8af0fa9d1405fcf2edb95f4b1b8d1904716 |
20-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
adds some attributes to attribute section when cpu is "xscale"
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
RM/xscale-attributes.ll
|
| 298c8e12ea063f7522c59d2a297b47a879b6ed55 |
20-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
fixes target address tBL and tBLX and sets relocation type
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-thumbfunc-reloc.ll
|
| 861b9c6a397f2ed4b5601cacbc9121d0b07d1f65 |
19-May-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
This fixes one divergence between LLVM and binutils for ARM in the
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-movt.s
|
| a3bff99f0a325092dc1227c036f5def4aa1b9bb5 |
19-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
Fixes PR9934.
We really need to start tblgening the relocation info :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| a96581f4f70fa305e4d0726f20b0ec687fca7b7c |
18-May-2011 |
Johnny Chen <johnny.chen@apple.com> |
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 6469540adf63d94a876c2b623cb4ca70479647f7 |
16-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
sets bit 0 of the function address of thumb function in .symtab
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
LF/elf-thumbfunc.s
|
| 18901d63bf0deb117bd7a1ad69b25faa422ce378 |
11-May-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| e3a0e987f3d4f07512cdb64b9034369f966cb448 |
10-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
On MachO, unlike ELF, there should be no relocation to produce the CIE pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131149 91177308-0d34-0410-b5e6-96231b3b80d8
achO/debug_frame.s
|
| 0d450dc65906a30beb56aeb1ee22b45b1cd4596c |
10-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
In a debug_frame the cfi offset is to the start of the debug_frame section!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131129 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-sections.s
|
| 40a7dbbeff44c4cbd8c7e4f07f28dd614f8a5d08 |
10-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for producing .deubg_frame sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131121 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-sections.s
|
| f695b3ad628625a1b1250c65716df1ee96b3d975 |
04-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Explicitly request -join-physregs for some tests that depend on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130855 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| b65122c8736e6f8795043ca9885feb676781af4a |
04-May-2011 |
Eric Christopher <echristo@apple.com> |
Remove some random comments that snuck in from somewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130812 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
|
| 2fc496fcf5c5caf3e6af755d2c8fc97686cc2dd2 |
03-May-2011 |
Eric Christopher <echristo@apple.com> |
xmm0 is an implicit parameter in this and so shouldn't be in the
string template.
Fixes rdar://8493866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
|
| c8497b6a2565046b5e6b5f2ea9dedc62b53dd966 |
29-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
MCAsmLayout: Add support for computing the symbol offset of variables. Not
currently used, because variables don't get reported as being "defined".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130524 91177308-0d34-0410-b5e6-96231b3b80d8
achO/variable-errors.s
|
| 90604ab725da8a2a57cf3ca1541b14b95d619040 |
29-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130523 91177308-0d34-0410-b5e6-96231b3b80d8
achO/variable-exprs.s
|
| 5a2336e79439281a055b247f54c9d425ea0cd083 |
28-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add tests for A8.6.110 NOP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130345 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/thumb-tests.txt
|
| a4a2a03c311e7a7b64bfba1ae714ae85f74999fd |
25-Apr-2011 |
Chandler Carruth <chandlerc@gmail.com> |
Remove some hard coded CR-LFs. Some of these were the entire files, one of
these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130125 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.s
OFF/bss.s
OFF/simple-fixups.s
OFF/symbol-alias.s
OFF/symbol-fragment-offset.s
OFF/weak.s
|
| 597fa65373b824c840212cf238a73ae13dc35494 |
22-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.
rdar://problem/9267772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-printf.txt
isassembler/ARM/thumb-tests.txt
|
| 1ac7fe0f4dae8a9266fa6ff31ea4939ec64a3e5e |
21-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix relative relocations. This is sufficient for running the rust testsuite with
MC :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129923 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/diff.s
|
| 3660a847f1820d73847539f3959dc069396f8e44 |
20-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Behave like gnu as when a relocation crosses sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129850 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/diff.s
|
| 3a96122c4ae4e7727ba976a9f658626c18997689 |
16-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Thumb2 BFC was insufficiently encoded.
rdar://problem/9292717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| a704bc9354d8b03fd98da9bd7de5ae1dc49af961 |
16-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.315 VLD3 (single 3-element structure to all lanes)
The a bit must be encoded as 0.
rdar://problem/9292625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
|
| c25e8d8cea7af83b5538ac0e521366d06c9720d9 |
15-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add encoding tests for flds/filds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86_64-encoding.s
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-diff-relocs.s
|
| de29a52940101cd162cc9a53cfd3d09d60547e6f |
15-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
(single element or n-element structure to all lanes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
isassembler/ARM/neon-tests.txt
|
| cd695fdac16c206655a19fb1741ab71929f28711 |
14-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-t2LDREXD-thumb.txt
isassembler/ARM/invalid-t2STREXB-thumb.txt
isassembler/ARM/invalid-t2STREXD-thumb.txt
isassembler/ARM/thumb-tests.txt
|
| d336de318eafd7643f65a901315920ec10ce05cd |
14-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
(movzx/movsx) because they give more information. Revert that part of the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| c6df9883da99915d1cfa491b381ffa703c61ed90 |
14-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
Have the X86 back-end emit the alias instead of what's being aliased. In most
cases, it's much nicer and more informative reading the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| e8d087ad351258f3db39f41dc595fae4ddb4f318 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Thumb disassembler did not handle tBRIND (indirect branch) properly.
rdar://problem/9280370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 6c7e4147dc7faf2f7b4bdaaf7940c2fe65d6fbc5 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
rdar://problem/9280470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-t2Bcc-thumb.txt
isassembler/ARM/thumb-tests.txt
|
| 471d73d5d387d52dc854145caca971dfd9fd506a |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
rdar://problem/9279440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-t2LDRBT-thumb.txt
|
| 9bb386a9330f9c26f648ce1009561833fbc59e4b |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
rdar://problem/9276651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-t2LDRSHi12-thumb.txt
isassembler/ARM/invalid-t2LDRSHi8-thumb.txt
|
| 119af20c7b9d6aaae6941d5fc88392efe92eb9f1 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
rdar://problem/9276427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 55e6419b12a5f5c1c5b7e3f5f6bebd6b71df0bd0 |
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
rdar://problem/9273947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRD_PRE-thumb.txt
isassembler/ARM/invalid-t2STRD_PRE-thumb.txt
|
| ec51a6225c59fee9021b8b6c7c813228cb27a3fa |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The Thumb2 RFE instructions need to have their second halfword fully specified.
In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 32cefad4b39e28674805c4704bc8c4c3ca70134a |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add bad register checks for Thumb2 Ld/St instructions.
rdar://problem/9269047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-t2STR_POST-thumb.txt
|
| f9ce2cba42f76ad82bbb17436902f66a9e5f6367 |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 49fdfe3ce5736e8c76cdf512cc0cd5afb3b8f2e6 |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-STMIA_UPD-thumb.txt
|
| 25f492e77858dc5a95fcd7180e73aff47925b668 |
12-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129362 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-rel-offset2.s
|
| c57543964d1382d3d3a5005f415b6c0f49671b3a |
12-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement .cfi_same_value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129361 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-same-value.s
|
| 163b6eaf251306617f54c90dbc3a4b2dbbcae4e2 |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add one test case (svc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129327 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 05f9e4e8bd2347826c50ec391ea4ec8caffe45ef |
12-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Match case for invalid constant error messages and add a new
test for invalid hexadecimals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129326 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs-invalid.s
|
| e77f72d7d236cabee6ce154ade0f5c666ecaaaca |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.16 B
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-Bcc-thumb.txt
|
| 164254d77c36a2f224987406d66f3bacfdbb7652 |
12-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Test for invalid constant expr addition - bad octal constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129323 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs-invalid.s
|
| de16508955698a0f8890e0d54fee24efc9277ecd |
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Thumb disassembler was erroneously rejecting "blx sp" instruction.
rdar://problem/9267838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| a61842bf6ec00385488ef63df00f4627ca22b233 |
11-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement cfi_rel_offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129306 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-rel-offset.s
|
| 787d41aaa0dd5dbbacd760af111aaa7153ff6773 |
11-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add test for previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129304 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-adjust-cfa-offset.s
|
| 35563fee7b52f3bc9ef828abc139e8d9cb4ba2b9 |
11-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
rdar://problem/9266265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| e679d3331b5fb4747c5f03b546376f8fdb6a25d4 |
11-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
invalid instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRB_POST-arm.txt
isassembler/ARM/invalid-LDR_POST-arm.txt
isassembler/ARM/invalid-LDR_PRE-arm.txt
isassembler/ARM/invalid-STRBrs-arm.txt
|
| 15f895179953b258e4ca20860d0d58f25f3a3edb |
09-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| c18214a6e0a22ffa6886c70dbd6176ac9e91c847 |
09-Apr-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Don't store Twine temporaries, it's not safe.
And don't append the name over and over again in the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129210 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/rename.s
|
| c636074afcf95ecd9bb4069a49087a019d5e96b4 |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
PR9650
rdar://problem/9257565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 40de2b3f1529c23fee5de6e8324a1f023b361765 |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Sanity check the option operand for DMB/DSB.
PR9648
rdar://problem/9257634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-DMB-thumb.txt
isassembler/ARM/invalid-DSB-arm.txt
isassembler/ARM/thumb-tests.txt
|
| 084b5df5aedc83af0588ae8c2145e4f98faf1d8f |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.
Add tests for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129137 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-MOVTi16-arm.txt
|
| 97fdff1d3f0d931247aa300a02679681d684b87d |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
Add more test cases to exercise the logical branches related to the above change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-BFI-arm.txt
isassembler/ARM/invalid-SBFX-arm.txt
isassembler/ARM/invalid-UQADD8-arm.txt
|
| 9974b8b3cb49eb937cb148c4199e0d456186c3ca |
08-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Update tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129116 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/section.s
LF/align-bss.s
LF/align-nops.s
LF/align.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-offset.s
LF/cfi-remember.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/comdat.s
LF/common2.s
LF/debug-line.s
LF/debug-loc.s
LF/empty-dwarf-lines.s
LF/empty.s
LF/entsize.ll
LF/entsize.s
LF/global-offset.s
LF/ident.s
LF/merge.s
LF/noexec.s
LF/relocation-386.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/section.s
LF/undef2.s
|
| 3cf3059b119dd995847dc24a08708ef71be43179 |
08-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add a VEXT test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| ce8463f1fb223ecea1243b2274a7c18ddab6e815 |
07-Apr-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .skip.
Patch by Roman Divacky.
Fixes PR9361.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129106 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_space.s
|
| 22dc4d9f59213c51cefe4fe237030c91d92d388b |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
Add some test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-SXTB-arm.txt
|
| 8dbda0b51b7a7a7b4fb16a34b421a658cb86f9f3 |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add sanity checking for invalid register encodings for saturating instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-SSAT-arm.txt
|
| 4d4e25740bd1225f413a10db6166b620d2f5fbbb |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add some more comments about checkings of invalid register numbers.
And two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-LSL-regform.txt
|
| f16f4e09ec28fe2de13a1bcda391d7d16a368e3a |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Sanity check MSRi for invalid mask values and reject it as invalid.
rdar://problem/9246844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MSRi-arm.txt
|
| 8424a60fc9059d4ba7c45c80d28d86e3186fcf4e |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
for USAD8 and USADA8.
rdar://problem/9247060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| 2455268cddf6d5507ab21b59007194e92b0b9af7 |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Should also check SMLAD for invalid register values.
rdar://problem/9246650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-SMLAD-arm.txt
|
| d8b4c4d74f745e6d556e96e056fe774c7cbef697 |
07-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.393
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VST2b32_UPD-arm.txt
|
| 4d81c9a6ba076e86671eebb9a0c533a45f357d2d |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MCR-arm.txt
isassembler/ARM/neon-tests.txt
isassembler/ARM/thumb-tests.txt
|
| a9611549fe5cd06000111851f88b951467695307 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| 6a1220eeca1f3511bcf6ffed43a9ae77624eb8a8 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 2c868d1eef1e52a2b3211050006344e00c461ac3 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| c3281c10c94185e18338764b225a730a7c3e3ec4 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
A7.3 register encoding
Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VQADD-arm.txt
isassembler/ARM/neon-tests.txt
|
| 5438d76416bdb074bd3135a7649b31c563a05dd9 |
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.
rdar://problem/9237734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-RSC-arm.txt
|
| c584e317e9d5795129e747c9b0854165e39933f1 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MOVs-LSL-arm.txt
|
| 2c2130bc64d9a20b8a2681f230b2c03bd18a8c9b |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128922 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| bbc65bbb90e38a4066f0d4f5b403f85c1fecdf13 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-printf.txt
isassembler/ARM/thumb-tests.txt
|
| 5dc0c503725c56aa74656b7c1221340f238bfa3f |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
LDRD now prints out two dst registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128909 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 12bb2958c4f335e79c831136d2dfed9f375f06ff |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
isassembler/ARM/arm-tests.txt
|
| b26d8d7c493ec773661c1d3a7863f798f3786e40 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Check for invalid register encodings for UMAAL and friends where:
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128895 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-UMAAL-arm.txt
|
| 157536b1fb900e57efe042d48c7caeb87b1efd04 |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-RFEorLDMIA-arm.txt
isassembler/ARM/invalid-SRS-arm.txt
|
| 2d66cec9dd54b62c8b1e9b171e87fd17d419b13d |
04-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix incorrect alignment for NEON VST2b32_UPD.
rdar://problem/9225433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| ac79e4c82f201c30a06c2cd05baebd20f5b49888 |
04-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode3.s
|
| 4a8ac8de1ddfeaadb9ff13ce361bfc6435f18028 |
04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add support for the VIA PadLock instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
86/padlock.s
|
| 04187ecd57c6ce2550fbcea43966c5cff234b39a |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 103bf951a4d221a9cff4a5a4766754cf0cb126f4 |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
rdar://problem/9224276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MOVr-arm.txt
|
| 6da3fe68c6e3f5abd520a1bfc8dd8429e6ec6389 |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
rdar://problem/9224120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-MOVs-arm.txt
|
| 857b1939dabefe931e1fd25b20185153ea389587 |
02-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| ec30f6f5e5e53f384f3cbdade08ba654ef3680c7 |
01-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-LDRT-arm.txt
|
| 5307da994aee85c22af26437d45254228898db2d |
01-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
rdar://problem/9219356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| ae0855401b8c80f96904b6808b0bc4c89216aecd |
01-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| 0c630b5f3883aa494eca732f08a547d694d3931a |
31-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which
amounts to an UNDEFINED instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128668 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDC-form-arm.txt
|
| a52d7da1d8c424276f79b80c89ed045166083730 |
31-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix single word and unsigned byte data transfer instruction encodings so that
Inst{4} = 0.
rdar://problem/9213022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-LDRrs-arm.txt
|
| 8901e6ff3da1c1a68ee5c1c24f21e8572ceb57b6 |
31-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add BLXi to the instruction table for disassembly purpose.
A8.6.23 BLX (immediate)
rdar://problem/9212921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 48a36158ec09f3f47e9e84af7feb6fcf9fccfd28 |
31-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Remove stray empty test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128640 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| b41aaab5a1769f4df04d566da37866ac91b6ee9e |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert r128632 again, until I figure out what break the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| bcd3a9cd84d3bb143075d31bdf631f621f44f9e7 |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r128585 without generating a lib depedency cycle. An updated log:
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| e4345c9977e65b14fa4b93d19c7e67a7b15f7f40 |
31-Mar-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| 40829ed6f5e449fa33a9cd7022ce6c3941dace3d |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_addrmode2.s
|
| caee9684813ef97e035604b36842cda4f712fbee |
30-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add a test case for thumb stc2 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128517 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| b715ce35d709e911f0936cfdb6b98aef15d0d5cf |
29-Mar-2011 |
Kevin Enderby <enderby@apple.com> |
Adding a test for "-inf" as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128495 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| e077157e544a7df3e918df6421e0c50bb5f99144 |
29-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add a test case for MSRi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128494 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 360d8d7a02188c694b79e5e4c8fafcfa84257938 |
29-Mar-2011 |
Kevin Enderby <enderby@apple.com> |
Added support symbolic floating point constants in the MC assembler for Infinity
and Nans with the same strings as GAS supports. rdar://8673024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128488 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| 5726005e4f1df81f47af99eebd380fca78577fa4 |
29-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add a thumb test file for printf (iOS 4.3).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128487 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-printf.txt
|
| 9eda569a74377bdcf8ce6073682fb9a4bd8a82ca |
29-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.188 STC, STC2
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 4381dd1f21b90db256b42362f81ec96e045d46f6 |
29-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128477 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-VLDMSDB-arm.txt
isassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
|
| 288a4284bbd15a168d311e6fc97a32527de9687d |
29-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add and modify some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128476 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-VLDMSDB-arm.txt
|
| 848b0c39b11801614c47e460248b60e8d40eb257 |
29-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/invalid-VLDMSDB-arm.txt
|
| c6cf43d25853efb4a6765954eda52a45998a47f2 |
29-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC: Add support for disabling "temporary label" behavior. Useful for debugging
on Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128430 91177308-0d34-0410-b5e6-96231b3b80d8
achO/temp-labels.s
|
| d560a809251e54d7802728b9128dfd3b46f29b81 |
28-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| eca915fb5242442756a80bad7f285cb54d7b8ea4 |
26-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed the t2PLD and friends disassembly and add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| cf0fe4650fff28ecf3fc948d11f0133520d5a4ac |
26-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128306 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/thumb-tests.txt
|
| 65c0a5986906d04acd90ea280bcd635c5d492f75 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128305 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| a2755b9829affb1c2ac07d7710228e80d222f588 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
Also add some test cases.
rdar://problem/9189829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| abeea57639b38b1c3c129a023aecb57eed61355e |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
rdar://problem/9182892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| b66a0976127c7eb491ee0dfd1eeaba81b5d4ac76 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.226 TBB, TBH:
Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128295 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| ceceabd4b1e90bbddfa49799f1b3a4595dd6d99c |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
t2LDREX/t2STREX instructions. Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 8b2b43c41d2f9a25d1eb387bd74dd761fe3cb83b |
25-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC: Improve some diagnostics on uses of '.' pseudo-symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128289 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/dot-symbol.s
|
| 6c3891067b6e2e2aa399a57ecae407677f22391d |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
rdar://problem/9184053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| f14d5cf33a0414637a874ef9a4cbc8e0cf1debee |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Also need to handle invalid imod values for CPS2p.
rdar://problem/9186136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-CPS2p-arm.txt
|
| a7078c4f274e2c2ad431ae9f578624335c81be36 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| ef74e9ab409bd75c3679caae72bf233aa1faae49 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 8c13335c9ad8b558e548e81a5adbd958f1e04753 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since
the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add
test cases for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 1090d7711b145da53089f63336b173941d48d6f2 |
25-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| c39b6271be255a88fc9481d10894899b0f747ee3 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Handle the added VBICiv*i* NEON instructions, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| 9091bf25d97b8b43bd26ea03976d1f320c770a92 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
T2 Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 83ccbff84fd38d8680ae39b3b629aee339478855 |
24-Mar-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Plug a leak in the arm disassembler and put the tests back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-CPS3p-arm.txt
isassembler/ARM/invalid-VLDMSDB-arm.txt
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| 02af767dcaa0ed7677d542212b6c9b7110a425fc |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'.
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128235 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-CPS3p-arm.txt
isassembler/ARM/invalid-VLDMSDB-arm.txt
|
| e6d69e7dbee88a0a88f252a3e1e3f5f81472cf4b |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| b4ac342ea0a416f463f47bf40c0bd7448844e00b |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| ce1868b21ce91245622964da1408cdec76af77a8 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/invalid-CPS3p-arm.txt
isassembler/ARM/invalid-VLDMSDB-arm.txt
|
| 3d793962becf3a345cfff96202f3c6c27a1fb5d4 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 571f290376ad7b84aac6e58dcecd19d9797a3892 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
We now tag them as IndexModePost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 2abc9d2444c81bb5ac5aba0da0c863ec80d8f4b6 |
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The r128103 fix to cope with the removal of addressing modes from the MC instructions
were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 8d668a86055b2c278040a0984ad1ad0fa6631bb6 |
23-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add disassembly test cases for:
A8.6.292 VCMPE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128120 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/thumb-tests.txt
|
| 27c6baeca23be295d13da6a010d203b280058444 |
22-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 83cf2ffdcd5c555bbdaf440a76cf90cfd5a1ce87 |
22-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Add one more test case for VFP Load/Store Multiple (vpop).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128106 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/neon-tests.txt
|
| 758df297412df99d737dfcaea09b5e7857f320e5 |
22-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
A8.6.399 VSTM:
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 7c18fa87a4d4ed8b0cfe1ec65597c748c6d91ca9 |
20-Mar-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Write the section table and the section data in the same order that
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127972 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
LF/alias-reloc.s
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/cfi-advance-loc2.s
LF/cfi-def-cfa-offset.s
LF/cfi-def-cfa-register.s
LF/cfi-def-cfa.s
LF/cfi-offset.s
LF/cfi-remember.s
LF/cfi-zero-addr-delta.s
LF/cfi.s
LF/comdat.s
LF/common.s
LF/got.s
LF/local-reloc.s
LF/merge.s
LF/pic-diff.s
LF/relocation-386.s
LF/relocation-pc.s
LF/relocation.s
LF/rename.s
LF/symref.s
LF/tls.s
LF/undef2.s
LF/weakref-reloc.s
LF/weakref.s
|
| 94dad03a9626511cf16edc90284e873b696c8db2 |
19-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 0082830cb26248178fe5cc9bbdbd00881556c33d |
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 96622aa063435b1de085489f0e3e49b5912c22da |
18-Mar-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Support explicit argument forms for the X86 string instructions.
For now, only the default segments are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| 5e5a40867a1adce1178ed226b77b0a1b0cb6a5c0 |
18-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
Remove the offending logic and update the test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| e68d8ec25296574109b586359d37318c725442ac |
17-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
It used to be that t_addrmode_s4 was used for both:
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 8d06ffca9b72ebef7f5b8830b7ccbd9dd74f8e18 |
17-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have
been removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127812 91177308-0d34-0410-b5e6-96231b3b80d8
achO/section-attributes.s
|
| d02c8b6cc1d07bfe37fc055eefdac21b1c9303cb |
17-Mar-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Fix handling of @IDNTPOFF relocations, they need to get STT_TLS.
While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127780 91177308-0d34-0410-b5e6-96231b3b80d8
LF/tls-i386.s
|
| 276f6f9cf978fa7074687eead10a6db96c5afa6d |
15-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
There were two issues fixed:
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 9a9d8b97325ca5e568afebe54dd0bffd64b3eff1 |
15-Mar-2011 |
Sean Callanan <scallanan@apple.com> |
Basic sanity checks to ensure that 2- and 3-byte
VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/simple-tests.txt
|
| 085ea1b6337ff524edcff3368ee15b5acf9f5e53 |
15-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 899eaa35696bb0a9a625acd70a14876834af6cc5 |
11-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 950d3db5f478a84242a90cafce0d8dfc4f8b1152 |
11-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
created from the", it broke some GCC test suite tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 592ca3fda918c2066d9d78ed360e5fd69066fda7 |
11-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 18b475f95478f130667faa8c74bea4efdf68b1ed |
09-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 620d0cc7ac8319fe66168288f8ca0509f87c46c1 |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
* Correct encoding for VSRI.
* Add tests for VSRI and VSLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| c04a9dea7873bcf2a1e68b9eba9b5854021e989a |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Correct the encoding for VRSRA and VSRA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 7c6b608a7cb33e628e3906a8395a7ba47a6b966b |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
* Update the NEON shift instruction test to expect what 'as' produces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 591432136c78ab61ac1233cb813077e4c7c2f25e |
08-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
A few more tests for instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127209 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 3116dce33840a115130c5f8ffcb9679d023496d6 |
08-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| 89e0f386f3c8bafbbae05d7d32695ce571617397 |
04-Mar-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Be nice to Xcore and the XMOS assembler and avoid quoting section names
that contain only letters, digits and the characters "_" and ".".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section-quoting.s
|
| 86d822df6d9a484b3672b2a909641262663a45dc |
04-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Followup to r126970: add 64-bit encoding tests for str with reg operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| ac39bd534be9a8022c09cc8be81db2de109baecb |
04-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
PR9377: Handle x86 str with register operand in a way consistent with gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| ea83b133503afcd6589cf317cbb54ccd9e100f57 |
03-Mar-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Bug#9033: For the ELF assembler output, always quote the section name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section-quoting.s
|
| 78c1e1781cf36dd19988047eac8f664873d35237 |
03-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
PR9352: Always emit a relocation for weak symbols. Not emitting relocations
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126933 91177308-0d34-0410-b5e6-96231b3b80d8
LF/weak-relocation.s
|
| 1473f35c47658775e3a9ec23da2a47ff0ef79ac4 |
03-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
TableGen should not ignore BX instructions for the ARM disassembler. pr9368.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126931 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 181d3fe727022160ce8932e355eae8b3ff478592 |
03-Mar-2011 |
Bob Wilson <bob.wilson@apple.com> |
pr9367: Add missing predicated BLX instructions.
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| d39647d9130a52beb80bdc9116cb0f3a8affe12f |
03-Mar-2011 |
Kevin Enderby <enderby@apple.com> |
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
Patch by Ted Kremenek!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| a656b63ee4d5b0e3f4d26a55dd4cc69795746684 |
01-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Narrow right shifts need to encode their immediates differently from a normal
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.s
|
| d436d5b1c993c78b6c267b5fc1056d593f07921f |
28-Feb-2011 |
Kevin Enderby <enderby@apple.com> |
Fix the arm's disassembler for blx that was building an MCInst without the
needed two predicate operands before the imm operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 98ea4ce516f40beb3efe63e8fb9eee7a3124a7d9 |
25-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
split this test into arch specific pieces, so the ARM
test isn't run when the arm backend isn't built. This
fixes PR9327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126500 91177308-0d34-0410-b5e6-96231b3b80d8
RM/bracket-exprs.s
LF/bracket-exprs.s
|
| 93c65e6e661eda75711363bdd5ca15909920e1f0 |
24-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Restore r125595 (reverted in r126336) with modifications:
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126443 91177308-0d34-0410-b5e6-96231b3b80d8
RM/bracket-darwin.s
LF/bracket-exprs.s
LF/bracket.s
|
| 3fe3424a2149a67f7468fc7a441d6cb6bb79ca33 |
24-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Move arch specific tests in arch specific directories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
RM/darwin-ARM-reloc.s
RM/darwin-Thumb-reloc.s
RM/full_line_comment.s
smParser/full_line_comment.s
achO/darwin-ARM-reloc.s
achO/darwin-Thumb-reloc.s
|
| f95618364396dedb9d926c9989625fd633a24b78 |
23-Feb-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove file. Previous commit deleted content, but left the file around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126337 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/paren.s
|
| 33b7bebca4be7e6759e61223d6b058d47ad0e071 |
23-Feb-2011 |
Jim Grosbach <grosbach@apple.com> |
Revert r125595, which is an X86-only undocumented assembly syntax extension
enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.
Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126336 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
smParser/paren.s
|
| 21451e533f4c46cdb38d338cfed26cece1d7be54 |
23-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Put in the symbol table symbols only used in a .globl statement.
Fixes PR9292.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126330 91177308-0d34-0410-b5e6-96231b3b80d8
LF/pr9292.s
|
| 8fbc00b5bab870d3c756d40add9b0eb27827fb97 |
23-Feb-2011 |
Sean Callanan <scallanan@apple.com> |
Fixed a bug in the enhanced disassembler that caused
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/enhanced.txt
|
| 00743c2218ff3f0f4edce972e2d88893a19e6ef8 |
22-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Use the same (%dx) hack for in[bwl] as for out[bwl].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| ec243ae2b859487bd417a1289da2a4a5901c3469 |
22-Feb-2011 |
Sean Callanan <scallanan@apple.com> |
Added a testcase for the enhanced disassembly bug
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126182 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/enhanced.txt
|
| d86f482e4a9d71596e4f81afb0f7912ab3e40a7f |
22-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize loopz and loopnz as aliases for loope and loopne.
From Dimitry Andric.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| 87ca0e077d91b96a765b3b24cadfa8891026a33a |
22-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement xgetbv and xsetbv.
Patch by Jai Menon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| d45e8bf93b2024213e423b7b40272da6636e78f7 |
22-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Handle FK_PCRel_1 and add a test case for this and FK_PCRel_4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126157 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-pc.s
|
| f7ad048f1e122ee4f735398786f4859392f74144 |
20-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add some limited support for labels in org directives. Hopefully enough to fix
PR9245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126091 91177308-0d34-0410-b5e6-96231b3b80d8
LF/org.s
|
| 824a9076eaf8d109bc79f53e51b7d7a045f42552 |
19-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
implement PR9264: disambiguating 'bt mem, imm' as a btl.
This is reasonable to do since all bt-mem forms do the
same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126047 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 584bf7bb03e4cf1475b26851edcc1ddb66b85028 |
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/thumb-tests.txt
|
| 5ad596f9d27a67767118857471e63b55bfb152d6 |
18-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize monitor/mwait with explicit register arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| 97755a063eb65705e928550b048ecb921c83545c |
18-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize leavel and leaveq aliases for leave.
Validate encoding of leave in 64bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125795 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86_64-encoding.s
|
| 908159b46ae118d36fccbc1d5145dcedfc3d4185 |
16-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Gas is very inconsistent about when a relaxation/relocation is needed. Do
the right thing and stop trying to copy it. Fixes PR8944.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125648 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relax.s
|
| 7768a9dce14431018133cd586f5c8ce3e057f069 |
16-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for pushsection and popsection. Patch by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125629 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/section.s
|
| 738a00eb861c045dc11366b4d3203cde0e528f22 |
15-Feb-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Add support for parsing [expr].
This is submitted by Joerg Sonnenberger and fixes his PR8685.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125595 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
smParser/paren.s
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb.s
RM/thumb2.s
isassembler/ARM/arm-tests.txt
isassembler/ARM/thumb-tests.txt
|
| 26f23100ac8165c510c00f7a37f1ab13bf66f141 |
13-Feb-2011 |
Reid Kleckner <reid@kleckner.net> |
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.
These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86_64-encoding.s
|
| b9db0c50d84b06b4b567c29375b7db92b5dab077 |
10-Feb-2011 |
Jim Grosbach <grosbach@apple.com> |
Do AsmMatcher operand classification per-opcode.
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125245 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 971b83b67a9812556cdb97bb58aa96fb37af458d |
08-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 0fd90bc12f77820e757ef3a427fab9f66aba6381 |
08-Feb-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Support for .ifdef / .ifndef in the assembler parser. Patch by Joerg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125120 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ifdef.s
smParser/ifndef.s
|
| 706d946cfe44fa93f482c3a56ed42d52ca81b257 |
07-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing dmb/dsb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| 953a2a3dee46bebd70b129fd62709710f5f2b033 |
07-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage
failures with relocations.
The code committed is a first cut at compatibility for emitted relocations in
ELF .o.
Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.
Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass
Added reminder fixme to tests for future conversion to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124996 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-reloc-01.ll
RM/elf-reloc-02.ll
RM/elf-reloc-03.ll
|
| 2d7a53aec2c6426eba9e5dd6462cc9e86432b410 |
04-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to
5 to match the current doc.
Added FIXME reminder Make it really configurable later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124899 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-eflags-eabi.s
|
| 685c350ae76b588e1f00c01a511fe8bd57f18394 |
04-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_fixups.s
|
| 4d98ee52348c23a7a2f59a4235941fcbb668a2b9 |
01-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix test for non-darwin targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124640 91177308-0d34-0410-b5e6-96231b3b80d8
RM/prefetch.ll
|
| d11c57a93753e7fd9fdac110e81c88eb56a847e4 |
28-Jan-2011 |
Bob Wilson <bob.wilson@apple.com> |
PR9030: Fix disassembly of ARM "mov pc, lr" instruction.
Patch by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 14e66553d57ebec1d8ca6619f6570c5342a7a764 |
28-Jan-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Add support for parsing .float
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124485 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| 4c4c7329603491838d9c089dfbce19915c1431ea |
28-Jan-2011 |
Nico Weber <nicolasweber@gmx.de> |
PR8951: Support for .equiv in integrated assembler, patch by Jörg Sonnenberger!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124467 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/equ.s
|
| c3a20bab7571ff95525252c379198e67b65d0f1d |
28-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix PLD encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
RM/prefetch.ll
|
| 54b0f4f2a42919e9073c7220394cbc2d2b23f9bf |
27-Jan-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Add support for specifying register name in cfi-register/offset/def
as well as register number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124379 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-offset.s
|
| 106df6da366c0abc6a3937767fe008d02cacef4c |
26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add encoding testcases for ARM vcvtr variations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124289 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 1b10d5be40313b4e246e85cf375dfa3452ab306b |
26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb.s
RM/thumb2.s
|
| 59b8cf4512ab2b748b2e9240839876967be72542 |
24-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Jörg Sonnenberger noticed that we were missing this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124139 91177308-0d34-0410-b5e6-96231b3b80d8
LF/bad-section.s
|
| 184640e96e391ecfc4621156907b29f132c14959 |
24-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle strings in section names the same way as gas:
* If the name is a single string, we remove the quotes
* If the name starts without a quote, we include any quotes in the name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124127 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| 96aa78c8c5ef1a5f268539c9edc86569b436d573 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the --noexecstack option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
LF/noexec.s
|
| 54104db434d400e07cc238c9ac47c5e34e01cb20 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for lowercase variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124071 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 0cf5e3d51dd455a174a8f00cfa6b63c11e535434 |
23-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Delay the creation of eh_frame so that the user can change the defaults.
Add support for SHT_X86_64_UNWIND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| 030160073d8ec7d5fc1d928d9c8b6173d3a5e0cc |
21-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| 1115c472038b19dfcc3ff44b8bf6711ebcfc3dc4 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add testcases for clz encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123937 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| e47f3751d7770916f250a00a84316d412e959c00 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding and parsing of clrex instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| 8dd37f7b7dca7907f9f070dc96359f242e102163 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add cdp/cdp2 instructions for thumb/thumb2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
RM/thumb2.s
|
| b32f7a5f4bc678c052db40cbb4ac8617c134aa24 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 6b3a999f227139a3be7df6b5aea7a7d01ce94851 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr*2 and mr*c2 support to thumb2 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| fa5bd27fbe5188ca708ac0dda4f32d90505da9f5 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr* and mr*c support to thumb targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| 3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b |
19-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 6cd0b17ba7f7efae41966c4a36ee725523d38575 |
19-Jan-2011 |
Owen Anderson <resistor@mac.com> |
When matching asm operands, always try to match the most restricted type first.
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This
is tricky to resolve since neither is a subset of the other.
XFAIL the test for now. The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123786 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 61505907f54d4e7df2f9d90b1ed3a4caa0469d26 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs reg, fpexc
vmrs reg, fpsid
vmsr fpexc, reg
vmsr fpsid, reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
RM/thumb2.s
|
| e7255a80e308c7f67d25b0b247ed791a99ea3a4e |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix MRS encoding for arm and thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| 892fc6d7b64364b230261daa967518a71748c01b |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of t2ISB by using the right class and also parse it correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| fdcee77887372dbf6589d47cc33094965b679f24 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb.s
|
| a461d4222877f43588da38c466145f38dd74e229 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing and encoding ARM's official syntax for the BFI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/thumb2.s
|
| 2e3cea3153ab957af01925580d912be060cb00cf |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Start marking T2 address operands as such, for the benefit of the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2_instructions.s
|
| 1c10db3da9bf7f268cefb6935067ea831c605d15 |
16-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123591 91177308-0d34-0410-b5e6-96231b3b80d8
LF/entsize.ll
|
| f3eb3bba1614a7935b44fc963a805088d71267f3 |
14-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123424 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-movt.s
RM/hilo-16bit-relocations.s
|
| 0fba7143596330eb0e6d5e19777278abe1c9ba70 |
13-Jan-2011 |
Owen Anderson <resistor@mac.com> |
As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123407 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
|
| 7597212abced110723f2fee985a7d60557c092ec |
13-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-movt.s
RM/hilo-16bit-relocations.s
|
| 7caebff83d90a59aa74876ff887e822387f479e0 |
12-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Sort the register list based on the *actual* register numbers rather than the
enum values we give to them. <rdar://problem/8823730>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123321 91177308-0d34-0410-b5e6-96231b3b80d8
RM/reg-list.s
|
| 86a97f2e4d0cde5e992f52ac287da0de687e0110 |
12-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
1. Support ELF pcrel relocations for movw/movt:
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-movt.s
|
| 9081b4b4cf89a161246e037f4817c69de2fcdf82 |
12-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Workaround for bug 8721.
.s Test added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123292 91177308-0d34-0410-b5e6-96231b3b80d8
RM/elf-movt.s
|
| 3a5004dc3ee789bcbafd5b9733d3302e73e1187d |
11-Jan-2011 |
Chris Lattner <sabre@nondot.org> |
Fix PR8946, a missing reg/reg form of movdqu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 352e148cbe6498a6dd31b7fc71df7cd23c4b4d10 |
11-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
carry setting flag from the mnemonic.
Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 8ab1112bdc30b8675bb12431d8b5b270da42f1b5 |
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Flush out hard coded known non-predicated mnemonic list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123189 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-absdiff-encoding.s
RM/neon-bitcount-encoding.s
RM/neon-pairwise-encoding.s
|
| 2f867a63daf99dc27830d4442a574a790e02f27e |
06-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly disassemble truncated asm.
Patch by Richard Simth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122962 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/X86/truncated-input.txt
|
| bbdcd443614fc1ac012227d9975201c18b9e2ab4 |
04-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Convert MC tests to .s so codegen changes won't break them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122786 91177308-0d34-0410-b5e6-96231b3b80d8
LF/basic-elf-32.s
LF/basic-elf-64.s
LF/basic-elf.ll
LF/call-abs.ll
LF/call-abs.s
|
| 7a54997d670d92f7f0ece87911800aa68fcb8c6d |
01-Jan-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix PR8878.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122658 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| c00210cef28b48b17408eb79e94691779da9d474 |
30-Dec-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Add another non-commutable instruction that gas accepts commuted forms for.
Fixes PR8861.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122641 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| b2624eda5ad0ead99ec5ab7ead47b586c96d1109 |
29-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/Thumb: Set the thumb bit in the symbol table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122630 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-Thumb-reloc.s
|
| caf1158b0f4ee5bd1bfc2c275e95e6fbb359df9d |
29-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly encode pcrel|indirect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122624 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
|
| a7e450574c45209ca0b05ff715f9e7dddcbd936c |
29-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix bug when trying to output uint16_t or uint32_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122615 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-advance-loc2.s
|
| b40a71fda188f8ca564e606ac2cb051a44ada311 |
29-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement cfi_def_cfa. Also don't convert to dwarf reg numbers twice. Looks
like 6 is a fixed point of that and so the previous tests were OK :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122614 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-def-cfa.s
|
| b4601bd2ffdde372f1323f6b6ec98acd433501ce |
29-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement cfi_def_cfa_register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122612 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-def-cfa-register.s
|
| b790a17efba26f4365b5ffb847dd53fde063c48d |
29-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Initial .cfi_offset implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122611 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-offset.s
|
| 3b78cdc57ae25ff021fd67171a7c82d533477a19 |
29-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't produce a "DW_CFA_advance_loc 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122609 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-zero-addr-delta.s
|
| fe024d0a624404ada11fb330e7360abc5f88742e |
28-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement .cfi_remember_state and .cfi_restore_state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122602 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-remember.s
|
| 245a1e20419aa5a3c833d7a8e89168e19d5f4d2c |
28-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Relax address updates in the eh_frame section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122591 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-def-cfa-offset.s
|
| 5bba08425374ca36fe5fbc7423ce1a09858e4097 |
28-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Start adding basic support for emitting the call frame instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122590 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi-def-cfa-offset.s
|
| bdc3167c086dd4358e24692075db5e7784140843 |
27-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .cfi_lsda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122584 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
|
| e8624538062da215fe23cfe201b1c905eb7ebb12 |
27-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/Thumb: Select appropriate relocation types for Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122583 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-Thumb-reloc.s
|
| c3a561cb8ed6f04e3cf7b1ff38c9f51a695d196d |
27-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle reloc_riprel_4byte_movq_load. Should make the bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122579 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 3a83c40ab61d5ca624f2bbadd70237c6adbdb304 |
27-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the same encodings of the personality function that gnu as
supports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122577 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
|
| 98976610d2c8067efe04042f17486a4b6c746b31 |
26-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for @note. Patch by Jörg Sonnenberger.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122568 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| d7c8ccae8e48dce3ab7c3e9b4d8a309998c47961 |
26-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add basic support for .cfi_personality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122566 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
|
| 7ab3cc32d6bd3c3166184e27713c91f5317c7f85 |
25-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Generalize a previous change, fixing PR8855 - an valid large immediate
rejected by the mc assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122557 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 4010dd72b81b760daaa0361084de6dca8ed86fa1 |
24-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/ARM: Start handling some Thumb branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122547 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-Thumb-reloc.s
|
| d82ed5b7347173a827969966db740c2b34d605b9 |
24-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
In llvm-mc parse a Hash token as a full line comment. Allows handling of
preprocessed .s files and matches darwin gas. rdar://8798690
Also fix a comment on the next line of AsmParser.cpp after this new code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122531 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/full_line_comment.s
|
| 72123334adfa1b020aa7aecf05ce6d135f9c7ffa |
22-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122441 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-ARM-reloc.s
|
| ecbbf40d5c67f398b70cfed9ed7eaccf52432014 |
22-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add reduced test from 8845.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122438 91177308-0d34-0410-b5e6-96231b3b80d8
achO/loc.s
|
| df561e02347a904de8dcb3a6f6cb42e10a43bddd |
22-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is
esp. important given that the LOCAL_SECTDIFF enumeration got redefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122412 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-ARM-reloc.s
|
| 294e67861c9a497f4b7529a410d8817d36354d5a |
22-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/ARM: Add enough relocation logic to get BR24 relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122407 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-ARM-reloc.s
|
| f01212489be07e261a0302744f878a54a39f05a5 |
22-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Simplify the handling of .size expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122404 91177308-0d34-0410-b5e6-96231b3b80d8
LF/size.s
|
| d66a32c35f06067a2c361e6b92ba86a09ec5cdc6 |
20-Dec-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Teach the MBlaze disassembler to disassemble special purpose registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122269 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MBlaze/mblaze_special.txt
|
| d149186e156fdd44e3cca988949cf3e5e6940863 |
20-Dec-2010 |
Roman Divacky <rdivacky@freebsd.org> |
Set the value of absolute symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122268 91177308-0d34-0410-b5e6-96231b3b80d8
LF/set.s
|
| 1ae3c165f7f6dd265f136d975f255c18de53a960 |
20-Dec-2010 |
Roman Divacky <rdivacky@freebsd.org> |
Print all 64bits for st_value and st_size. Adjust tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122263 91177308-0d34-0410-b5e6-96231b3b80d8
LF/abs.s
LF/alias-reloc.s
LF/alias.s
LF/comdat.s
LF/common.s
LF/file.s
LF/local-reloc.s
LF/pic-diff.s
LF/rename.s
LF/set.s
LF/symref.s
LF/tls.s
LF/type.s
LF/undef.s
LF/weak.s
LF/weakref-reloc.s
LF/weakref.s
|
| 9c0068f0a38597a5914b69a5e1b5a949027a5464 |
20-Dec-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Teach the MBlaze asm parser how to parse special purpose register names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122261 91177308-0d34-0410-b5e6-96231b3b80d8
Blaze/mblaze_special.s
|
| 7529b164104f802b59fbf96f5a88d9709ac3ff1a |
18-Dec-2010 |
Roman Divacky <rdivacky@freebsd.org> |
Add support for lexing single quotes like 'c'.
This fixed 8615.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122150 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_values.s
|
| 54f08852f6c45a1165295d66bd072e2d1da7a6d1 |
18-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a test that shows that we produce no fixups when computing the difference
of two symbols in the same fragment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122145 91177308-0d34-0410-b5e6-96231b3b80d8
LF/no-fixup.s
|
| a5ff979c114a658c69fddd065d702a13c40f6ae1 |
18-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Test for push being relaxed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122124 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 17304b3489b7b8ea06dd4df237f15a381ae181ce |
17-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Expr: Implemnt more aggressive folding during symbol evaluation using
IsSymbolRefDifferenceFullyResolved(). For example, we will now fold away
something like:
--
_a:
...
L0:
...
L1:
...
.long (L1 - L0) / 2
--
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122043 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-complex-difference.s
|
| dfe125cc9cfd524575973daa297c9aad10470390 |
17-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
"Fix" FDE alignment to match what gas does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122006 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
|
| 3ee33aa6f9b961e1c7b6dbb57df6fd53b68fbac4 |
16-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make pushq produce signed relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122005 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 0406356cd4cb7b689e2472faa8dfb7d721f9d274 |
15-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add Neon VCVT instructions for f32 <-> f16 conversions.
Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-convert-encoding.s
RM/neont2-convert-encoding.s
|
| 8d1b7e57e56015576fd489a57d74c53b98c5a56f |
15-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix misspelled target triples in MC/ARM test commands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121901 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-abs-encoding.s
RM/neon-absdiff-encoding.s
RM/neon-bitcount-encoding.s
RM/neon-bitwise-encoding.s
RM/neon-cmp-encoding.s
RM/neon-convert-encoding.s
RM/neon-dup-encoding.s
RM/neon-minmax-encoding.s
RM/neon-mov-encoding.s
RM/neon-mul-accum-encoding.s
RM/neon-mul-encoding.s
RM/neon-neg-encoding.s
RM/neon-pairwise-encoding.s
RM/neon-reciprocal-encoding.s
RM/neon-reverse-encoding.s
RM/neon-satshift-encoding.s
RM/neon-shift-encoding.s
RM/neon-shiftaccum-encoding.s
RM/neon-shuffle-encoding.s
RM/neon-sub-encoding.s
RM/neon-table-encoding.s
RM/neont2-abs-encoding.s
RM/neont2-absdiff-encoding.s
RM/neont2-bitcount-encoding.s
RM/neont2-bitwise-encoding.s
RM/neont2-cmp-encoding.s
RM/neont2-convert-encoding.s
RM/neont2-dup-encoding.s
RM/neont2-minmax-encoding.s
RM/neont2-mov-encoding.s
RM/neont2-mul-accum-encoding.s
RM/neont2-mul-encoding.s
RM/neont2-neg-encoding.s
RM/neont2-pairwise-encoding.s
RM/neont2-reciprocal-encoding.s
RM/neont2-reverse-encoding.s
RM/neont2-satshift-encoding.s
RM/neont2-shift-encoding.s
RM/neont2-shiftaccum-encoding.s
RM/neont2-shuffle-encoding.s
RM/neont2-sub-encoding.s
RM/neont2-table-encoding.s
|
| 2bf6afc277edb32b1d940def5b3eb0e0d32a22b9 |
15-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Relax alignment fragments.
With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).
This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121857 91177308-0d34-0410-b5e6-96231b3b80d8
achO/relax-recompute-align.s
|
| f9a447617329186976fe5ab8b48fe3c9c0698bc7 |
15-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.
Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121856 91177308-0d34-0410-b5e6-96231b3b80d8
achO/relax-recompute-align.s
|
| 53ef11884ff273715f1924ea13853ec18510dae1 |
15-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes. These come from my test generator and are just
the ones that MC currently assembles correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| abfbac52df836460392186a61619fe266b40fa8c |
14-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_fixups.s
|
| 89b9372605db2ce3b0085c84089e389f7bc1fbdd |
10-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fixed version of 121434 with no new memory leaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121471 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
LF/empty-dwarf-lines.s
|
| f7fd4aa2610f46467369de07f3ec669561d79be0 |
10-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert my previous patch to make the valgrind bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121461 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
LF/empty-dwarf-lines.s
|
| 1c952b9cc98e84b28f68f0f6cf11197263f89863 |
10-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Initial support for the cfi directives. This is just enough to get
f:
.cfi_startproc
nop
.cfi_endproc
assembled (on ELF).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121434 91177308-0d34-0410-b5e6-96231b3b80d8
LF/cfi.s
LF/empty-dwarf-lines.s
|
| 193c3acbe5cdb60767d114016970e898c7502d7a |
09-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Add support for parsing ARM arithmetic instructions that update or don't update
the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 76331754d4a06e2394c15ae8f4870f4aeaf5ca1f |
09-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Allow a slash, '/', as a prefix separator for X86. rdar://8741045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121320 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 545b77ef5002402e1f794249801fee14cad54dba |
07-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix absolute recording of differences of symbols in two sections. Reduced from ctor_dtor_count-2.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121152 91177308-0d34-0410-b5e6-96231b3b80d8
achO/diff-with-two-sections.s
|
| 3b3148f8647844b92bb84c7c3e864b5403484a38 |
07-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix relocations with weak definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121114 91177308-0d34-0410-b5e6-96231b3b80d8
achO/weakdef.s
|
| bf60dad984e296d43a8a6b33e8c528e8c8a24394 |
07-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix pcrel relocations that cross sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121107 91177308-0d34-0410-b5e6-96231b3b80d8
achO/pcrel-to-other-section.s
|
| f10d2be573f2e1000c2a4497c745367aab7bd9f1 |
07-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix a crash reduced from gcc produced assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121085 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbol-diff.s
|
| eb6779c5b98383e33542207f062102e79263df16 |
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 0bbe0b440ee2cef47dcb7b281825eb70341c16dd |
06-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Second try at making direct object emission produce the same results
as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121006 91177308-0d34-0410-b5e6-96231b3b80d8
achO/empty-dwarf-lines.s
|
| 340a7a1c8f57f738335c8af79320d22832365595 |
06-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't use PadSectionToAlignment on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120978 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.s
OFF/symbol-fragment-offset.s
|
| 5d4918dbd116b0b5e561c431b1ea527ee1b9302a |
04-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
There are two reasons why we might want to use
foo = a - b
.long foo
instead of just
.long a - b
First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.
Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120889 91177308-0d34-0410-b5e6-96231b3b80d8
achO/empty-dwarf-lines.s
|
| 767b1be3900bdc693aa0ad3e554ba034845f67f7 |
04-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Next step: Only pad debug_line when the target is darwin. Add a FIXME to avoid
doing that if the target is darwin10 or newer.
This fixes
*) Direct object emission was producing objects without the workaround on
darwin9.
*) Assembly printing was producing objects with the workaround on linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120866 91177308-0d34-0410-b5e6-96231b3b80d8
LF/empty-dwarf-lines.s
achO/empty-dwarf-lines.s
|
| d91f4e40e6312304c60c83c3dd93f769a39a9772 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
halfword being emitted to the stream first. rdar://8728174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-abs-encoding.s
RM/neont2-add-encoding.s
RM/neont2-cmp-encoding.s
RM/neont2-convert-encoding.s
RM/neont2-minmax-encoding.s
RM/neont2-mul-encoding.s
RM/neont2-neg-encoding.s
RM/neont2-reciprocal-encoding.s
RM/neont2-reverse-encoding.s
RM/neont2-satshift-encoding.s
RM/neont2-shift-encoding.s
RM/neont2-shiftaccum-encoding.s
RM/neont2-shuffle-encoding.s
RM/neont2-sub-encoding.s
|
| 41ad0c4c730bdbd4ec3a03868b81a56b6b1b01a1 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
32-bit wide version by adding the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 9f44724be058d17944dcd9ef6a6b57734b3744b8 |
01-Dec-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Rename temporary symbols if they conflict with artificial symbols created
by the assembler. This was blocking parsing any large .s produced by clang for
example.
Fixes PR8596.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120603 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/rename.s
|
| 9d63d90de5e57ad96f467b270544443a9284eb2b |
01-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/thumb-tests.txt
|
| 7f2abbf268aaa1c010a29649474c8f69e1521e25 |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for more forms of Thumb2 loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120436 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| ef4a68badbde372faac9ca47efb9001def57a43d |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| 6af50f7dd12d82f0a80f3158102180eee4c921aa |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Correct Thumb2 encodings for a much wider range of loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 75579f739fbc99a92a15f3ce75bbd7628ba00f8c |
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for basic loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 8ad87ab166062d7f1c1b936affd6d842b0f56169 |
29-Nov-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix some broken CHECK lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120332 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 2f17bf2a4406d89b5e127306cbd0fc862e0a6bd5 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| 5cbbf68e35a053c904548564da13d4a8596f988b |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
More Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120278 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| d19ac0c75a019273e03922e2252ed262578a43d1 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add Thumb encodings for REV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120277 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| 849f2e381e4e83dc4f60e4a1fe6e6bb47bde8248 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120272 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| d8f717911dcdccb1a60b3049ea22c7767970dcb7 |
28-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
fix PR8686, accepting a 'b' suffix at the end of all the setcc
instructions. I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne". The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120260 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| bfd2d26159c87262fcf462ea442f99478a2093c9 |
27-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement the data16 prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120224 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 44fa0473ae9144a8cfb4a500ae9de17239e69d2e |
27-Nov-2010 |
Daniel Dunbar <daniel@zuster.org> |
macho-dump: Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120185 91177308-0d34-0410-b5e6-96231b3b80d8
achO/absolutize.s
achO/comm-1.s
achO/darwin-x86_64-diff-relocs.s
achO/darwin-x86_64-reloc-offsets.s
achO/darwin-x86_64-reloc.s
achO/direction_labels.s
achO/indirect-symbols.s
achO/lcomm-attributes.s
achO/reloc.s
achO/section-align-1.s
achO/section-align-2.s
achO/string-table.s
achO/symbol-flags.s
achO/symbol-indirect.s
achO/symbols-1.s
achO/tbss.s
achO/tdata.s
achO/tls.s
achO/tlv-reloc.s
achO/tlv.s
achO/values.s
achO/x86_32-optimal_nop.s
achO/x86_32-symbols.s
achO/x86_64-symbols.s
achO/zerofill-1.s
achO/zerofill-2.s
achO/zerofill-3.s
achO/zerofill-5.s
|
| 2ace1b68ac717fc284b64944a38705ff57871ba2 |
25-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120147 91177308-0d34-0410-b5e6-96231b3b80d8
achO/x86_32-optimal_nop.s
|
| 6b8e4357ecb77a97e08557896f06fd45550c9e46 |
25-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Factor some code to parseSectionFlags and fix the default type of a section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120145 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| 25958730dffe0a16f9c251a1fa317799b8419a1f |
24-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Behave a bit more like gnu as and use the symbol (instead of the section)
for any relocation to a symbol defined in a tls section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120121 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 1683fcc82397681a64a35884edc9c62c49f2f179 |
24-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Relocate with the symbol if the relocation is of kind NTPOFF.
Patch by David Meyer, I added the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120104 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| bf8209daf875fa533a379290a91d01be5152597d |
24-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix and add tests for all cases in x86 and x86_64 where gnu as implicitly
sets the type of a symbol to STT_TLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120100 91177308-0d34-0410-b5e6-96231b3b80d8
LF/tls-i386.s
LF/tls.s
|
| 5c7106b2e375edca4b63ab48b218654f978698a4 |
24-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Testcase for r120017.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120099 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 97551276c59d4521200d2a4cf312a3fa885f2507 |
24-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
If a symbol is used as tls, mark it as tls even if not declare as so. Probably
fixes PR8659.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120076 91177308-0d34-0410-b5e6-96231b3b80d8
LF/tls.s
|
| d93ceeb125c11a96eb85618bb9a8a7d664a1d8f4 |
23-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120006 91177308-0d34-0410-b5e6-96231b3b80d8
LF/call-abs.ll
|
| af2b573614c7d853879ff24eb9a86d1c36acc198 |
21-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for ARM "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/simple-encoding.ll
RM/thumb.s
|
| cbf5d74e6a99b6e38c9c05e08b6319ed0ce49650 |
21-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement PR8524, apparently mainline gas accepts movq as an alias for movd
when transfering between i64 gprs and mmx regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119931 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 12203cc7c3f7392d62556946a10b2f10205ea63d |
21-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle PCRel relocations with absolute values. Fixes PR8656.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119917 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| e8e98d7f2eaa0613442ce21ab6a040c0f04f5b4d |
19-Nov-2010 |
Kevin Enderby <enderby@apple.com> |
Added support for the Mach-O .symbol_resolver directive. rdar://8673046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119816 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbol-flags.s
|
| 602890dd8ef53c6e8d60a2752b97940f7a58de1a |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119774 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb.s
|
| 50d0f5894448aff6eb02ad63da55ecf26b54aeb8 |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for parsing the writeback ("!") token.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| d2f76ce159cf7b04eb1658bf5d7b0e010909e0e3 |
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119756 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 71c11825bf1673baad44274ff71e8df1be938f5e |
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119755 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 612fb5b9a6472f8e1cea8a4f771238840f4eaa1c |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119737 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 821752e2e601b2e4c0bb83cb341892c853f16d0a |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out the set of Thumb2 multiplication operator encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119733 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 35141a9ba3ce92281cdbe1ccd0f6b5a42398249c |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Try again at providing Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119601 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 424216453fe2d16379fbb6c3310004b997d3771d |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119593 while I figure out my testing disagrees with the buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119597 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 18333616cd824bee3abecd607d3aa432b5cf507d |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119593 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| e7c682b54390b87cc2264963e957e9b754b59162 |
17-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Now that the MBlaze backend is in its own directory, split the test cases into multiple files for different types of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119580 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/MBlaze/mblaze-tests.txt
isassembler/MBlaze/mblaze_branch.txt
isassembler/MBlaze/mblaze_fpu.txt
isassembler/MBlaze/mblaze_fsl.txt
isassembler/MBlaze/mblaze_imm.txt
isassembler/MBlaze/mblaze_memory.txt
isassembler/MBlaze/mblaze_operands.txt
isassembler/MBlaze/mblaze_pattern.txt
isassembler/MBlaze/mblaze_shift.txt
isassembler/MBlaze/mblaze_special.txt
isassembler/MBlaze/mblaze_typea.txt
isassembler/MBlaze/mblaze_typeb.txt
|
| 2f7aed39a3082a3e0bb35475e8ed0cb782fef4b5 |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at correct encodings for Thumb2 bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119575 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 5aba9f694fbfb78df2aa2a228e85ba4c27f3037b |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119551, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119555 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 23465a06f4f4fa098f99cf91e81ed8f26f962f3f |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119551 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 46c478e80255bb1475e712ebb119808a9d0b9e12 |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More miscellaneous Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119546 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 435279b1a6dd5f48d30b1ca793cb661a271c4157 |
17-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .int.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119512 91177308-0d34-0410-b5e6-96231b3b80d8
LF/n_bytes.s
|
| 110f22aae897c348c97c09bbab8de12b3e82251d |
17-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .2byte, .4byte and .8byte.
Fixes PR8631.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119511 91177308-0d34-0410-b5e6-96231b3b80d8
LF/n_bytes.s
|
| 0f6307561359fac4425a0b9e512931cf96c1ec5b |
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 2c920850343810535c0cd8720a81eddf7997663a |
16-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
A bit more of gnu as compatibility when handling relocations with aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119328 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relax.s
|
| a295eb34a5c8bffa66ffd46b6f9b8e960930eae3 |
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Test encodings for LDM and STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119315 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| c56dcbf641f1675579e23064b1c7db1c73ca712b |
16-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for mov and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119295 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 7339fb5dae58df55857a97058d7905aed5868308 |
16-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change the 11 byte nop to be a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119286 91177308-0d34-0410-b5e6-96231b3b80d8
achO/x86_32-optimal_nop.s
|
| 2c4c45deb6a7a8521f6039e3da9688be4cac09d2 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for sxtb and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| bb6315d1e48f24e0eefa98b0f572fda8dbb3251f |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for comparison and shift operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| a99e778ed894402a4468ad0b695716226471d726 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for mvn and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 94ed5fca3f5ab5acb74e70b8393b837131e7110c |
15-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change MCExpr::EvaluateAsRelocatableImpl of variables to return the original
variable if recursing fails to simplify it.
Factor AliasedSymbol to be a method of MCSymbol.
Update MCAssembler::EvaluateFixup to match the change in
EvaluateAsRelocatableImpl.
Remove the WeakRefExpr hack, as the object writer now sees the weakref with
no extra effort needed.
Nothing else is using MCTargetExpr, but keep it for now.
Now that the ELF writer sees relocations with aliases, handle
.weak foo2
foo2:
.weak bar2
.set bar2,foo2
.quad bar2
the same way gas does and produce a relocation with bar2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119152 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias-reloc.s
|
| db9835d0895337eb94c19e3a30b7d3fc8fcddfd5 |
15-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix PR8565.
This moves most of the isUsed logic to the MCSymbol itself. With this we
get a bit more relaxed about allowing definitions after uses: uses that
don't evaluate their argument immediately (jmp foo) are accepted.
ddunbar, this was the smallest compromise I could think of that lets us
accept gcc (and clang!) assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119144 91177308-0d34-0410-b5e6-96231b3b80d8
LF/set.s
|
| 1f52dfe69ee7d0a49a6bfe6dfec6aeb8e416e313 |
15-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move the logic to decide with which symbol we produce a relocation (if any) to
a central location. This also makes us a bit more compatible with gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119094 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias-reloc.s
|
| 55d02f3a138badd5b1f96240b4d4b416d9026e2c |
14-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix another case of a .comm directive without a corresponding .type
directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119073 91177308-0d34-0410-b5e6-96231b3b80d8
LF/common.s
|
| 765fb1a446e0f1f338858dc628b4a7a60da37e80 |
14-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix the type of a symbol created with .comm and no corresponding .type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119060 91177308-0d34-0410-b5e6-96231b3b80d8
LF/common.s
|
| 2ae2302abc9d1e57dc6476603616e9f6722a5f6e |
14-Nov-2010 |
Dale Johannesen <dalej@apple.com> |
Segregate tests by target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119050 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/ARM/arm-tests.txt
isassembler/ARM/dg.exp
isassembler/ARM/neon-tests.txt
isassembler/ARM/thumb-tests.txt
isassembler/MBlaze/dg.exp
isassembler/MBlaze/mblaze-tests.txt
isassembler/X86/dg.exp
isassembler/X86/simple-tests.txt
isassembler/arm-tests.txt
isassembler/dg.exp
isassembler/mblaze-tests.txt
isassembler/neon-tests.txt
isassembler/simple-tests.txt
isassembler/thumb-tests.txt
|
| 1f4f9e3d35a2264d86f97dfb6d1e4ccb434f449b |
14-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle a peculiar comdat case: Creating a section with an undefined
signature symbol causes a local symbol to be created unless there is
some other use of the symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119026 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comdat.s
|
| 90eff7337d36b0398a22eac29da87c9c07b03b78 |
13-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Fixed error and re-enabled MBlaze MC disassembler tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118987 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/mblaze-tests.txt
|
| e13a0ff8ac6c86a04397801061e1a702d4e0eab1 |
13-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Parse and record the gnu_unique_object type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118980 91177308-0d34-0410-b5e6-96231b3b80d8
LF/type.s
|
| 4f8b791d0f0116211ae92b928ed0129f2ce59cd3 |
13-Nov-2010 |
Dale Johannesen <dalej@apple.com> |
This test stops after disassembling 1 instructions on
darwin and, judging from the buildbots, Linux.
Removing it for now, but this is not the right fix,
Wesley please look at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118977 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/mblaze-tests.txt
|
| c50a0fd7cb6da0e674e154205da65241f9c90e1d |
13-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Parse and remember discriminators in .loc line. I try to output them with
another patch.
This lets us parse a bit more of the gcc 4.5 output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118975 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_loc.s
|
| 7247c079f7416d6bb919f792fcfc67797a10a0e2 |
13-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Add test cases that should have been committed with 118969.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118974 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/mblaze-tests.txt
|
| ec57d53342827a17022b710cba9a9f4420d9ddce |
13-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
1. Adding test cases for MBlaze MC disassembler.
2. Fixing several errors in disassembler uncovered by test cases.
3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118969 91177308-0d34-0410-b5e6-96231b3b80d8
Blaze/mblaze_pattern.s
|
| 64185cc6090f695c4f97c51cf2adc731f56d1a20 |
13-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix the encoding of negative line deltas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118962 91177308-0d34-0410-b5e6-96231b3b80d8
LF/debug-loc.s
|
| 24d06f2be538c92104ab6c8ff49885858f44d2ad |
13-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
1. Adding missing immediate mode asm parser test cases.
2. Fixing improper immediate mode reverse subtract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118948 91177308-0d34-0410-b5e6-96231b3b80d8
Blaze/mblaze_typeb.s
|
| 8bfdd8771431cd187794fb185f86727e73748810 |
13-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Fixing improperly encoded reverse subtract instructions in MBlaze backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118943 91177308-0d34-0410-b5e6-96231b3b80d8
Blaze/mblaze_typea.s
|
| 41400da31ead2f61d171381c0945dceddd8fc786 |
13-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
1. Finishing MBlaze MC asm parser test cases
2. Parsing .word directive in MBlaze asm parser
3. Fixing hack where memory instructions reversed order of last two parameters
4. Fixing many improperly encoded instructions
5. Support parsing special instructions (MFS,MTS,etc.)
6. Removing unused functions from inst printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118941 91177308-0d34-0410-b5e6-96231b3b80d8
Blaze/mblaze_branch.s
Blaze/mblaze_fpu.s
Blaze/mblaze_fsl.s
Blaze/mblaze_memory.s
Blaze/mblaze_pattern.s
Blaze/mblaze_shift.s
Blaze/mblaze_special.s
Blaze/mblaze_typea.s
|
| 5de6d841a5116152793dcab35a2e534a6a9aaa7a |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
First stab at providing correct Thumb2 encodings, start with adc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
RM/thumb2.s
|
| 269f10b316b41fde5c9bf3f6e5c471f371862834 |
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
accept lret as an alias for lretl, fixing the reopened part of PR8592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 6b5e3978e3f720f6d2828068157b9d9687aee711 |
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| d4a352609f0ebe8bdea2f70d4e0efae9b5db778e |
12-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
gnu as support both % and @ before types, do the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118893 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
LF/type.s
|
| 8f143913141991baaa535ca0da7c8a81606d6392 |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out support for Thumb2 encodings of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-absdiff-encoding.s
RM/neont2-bitcount-encoding.s
RM/neont2-bitwise-encoding.s
RM/neont2-convert-encoding.s
RM/neont2-dup-encoding.s
RM/neont2-mov-encoding.s
RM/neont2-mul-accum-encoding.s
RM/neont2-pairwise-encoding.s
RM/neont2-table-encoding.s
|
| ef5b390263ebe6e22c89cb16faebf0fb3c4ce1ee |
11-Nov-2010 |
Wesley Peck <peckw@wesleypeck.com> |
Fix tblgen instruction errors exposed by MC asm parser tests
Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118844 91177308-0d34-0410-b5e6-96231b3b80d8
Blaze/dg.exp
Blaze/mblaze_fsl.s
Blaze/mblaze_imm.s
Blaze/mblaze_operands.s
Blaze/mblaze_typea.s
Blaze/mblaze_typeb.s
|
| 57dac88f775c1191a98cff89abd1f7ad33df5e29 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-vld-encoding.s
RM/neont2-vst-encoding.s
|
| 410cb57524e3bfb022df20091ae4a5fa1fa7005d |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Flesh out tests for Thumb2 encodings of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118837 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-cmp-encoding.s
RM/neont2-minmax-encoding.s
RM/neont2-mul-encoding.s
RM/neont2-neg-encoding.s
RM/neont2-reciprocal-encoding.s
RM/neont2-reverse-encoding.s
RM/neont2-satshift-encoding.s
RM/neont2-shift-encoding.s
RM/neont2-shiftaccum-encoding.s
RM/neont2-shuffle-encoding.s
RM/neont2-sub-encoding.s
|
| c7139a6f0d3acd198ab9eb536ea1ec52e61ff130 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neont2-abs-encoding.s
RM/neont2-add-encoding.s
|
| e1a2587ee273943390608df096378116ce52ffba |
11-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Mark labels declared in tls sections as STT_TLS. This matches the behavior of
gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118818 91177308-0d34-0410-b5e6-96231b3b80d8
LF/tls.s
|
| 2ff9e83a826c1c2ee0f1c6072d3d97d5b10678ee |
11-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Initial comdat implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118805 91177308-0d34-0410-b5e6-96231b3b80d8
LF/comdat.s
LF/section.s
|
| 9302bd664d930e7e6b61e208b0cca06fe71e8eb3 |
11-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make AliasedSymbol able to handle MCTargetExpr. They can get here if
a weakref is used with a VariantKind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118798 91177308-0d34-0410-b5e6-96231b3b80d8
LF/weakref-plt.s
|
| 03f1b74aed795110f040b7588c8921c5de4bf1ea |
11-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix the symbol index of weak references. Also make RecordRelocation a bit
easier to read by having const references to the symbol, aliased symbol and
renamed symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118793 91177308-0d34-0410-b5e6-96231b3b80d8
LF/weakref-reloc.s
|
| c24cb3551ed66830b53362f593269873cb53a0c4 |
09-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for ARM's specialized vector-compare-against-zero instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.s
|
| 4faf7c78fe58ba0b9e05e141dc1fec1ff4d98a50 |
08-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Set default flags for .rodata.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118395 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| 187d8339dbc0530850e54a86edf36f1a865a5823 |
07-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Relax dwarf line fragments. This fixes a crash in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118365 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relax-crash.s
|
| 689cf3cb6222652b92fdbd52e96c1d2f421ac44e |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement aliases for div/idiv that have an explicit A register operand,
implementing rdar://8431864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 04a75abe234f1093f69a065d799b3271ccd09f99 |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add aliases for movs between seg registers and mem. There are multiple
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| db28788e4ae01c3fa8003773fc236768e87f6917 |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
go to great lengths to work around a GAS bug my previous patch
exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86-32.s
|
| 8c24b0c6996a8f03ff32766f0695dcf19577af59 |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
rework the rotate-by-1 instructions to be defined like the
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 235705b9ca08b66532528930adf9d9c23fd7b42b |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
change the fp comparison instructions to not have %st0 explicitly
listed in its asm string, for consistency with the other similar
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86-32.s
86/x86-64.s
|
| fb7000fcbde3b5257ac055e1e5abdee5df21842b |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
correct suffix matching to search for s/l/t suffixes on
floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| 080c09229739ec2b13f7bccc361994a8d26b4ed2 |
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add codegen and encoding support for the immediate form of vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| 2f46f1f59c17040f7a2c970342f2f1dcc9b78319 |
04-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 60f4870c221d0496254c78c6e61bc00e4540fc1b |
04-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| d966817f3cb87897cbec29c967b974924fe939ba |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.s
|
| 7a25825033a53925f6039b77c4cb0b975026b4e1 |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.s
|
| 92b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4 |
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| f4b284f99141a1f6da0cb2096b0c948b203487e7 |
03-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
chase owen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118124 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| ca99597ed548aa1de4ffa734199abe9904e81a8b |
03-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
tweak this to pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118122 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| d5b02302f3832f1a412e133de4cf084cb2e05a49 |
03-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
temporarily xfail this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118120 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| 5df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0ad |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/simple-fp-encoding.s
|
| b20594fce621a0b80132a575113c15ad33afc5e9 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the remaining vst variants that we currently generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| a1a45fd25471e1121887b45ddc50f611f3c5f0aa |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for basic variants for vst3 and vst4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| d2f3794e4dba7a397eaae62114fffe46213c7d41 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic variants for vst2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| cfebe3a8b1b5b4654761953a9b695901a1b8eaec |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic form of vst1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vst-encoding.s
|
| f0ea0f2b1575868cd238391868d8f51370041303 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the rest of the vld instructions that we generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 3ff57094a7d176a759ddb1e1668489d89064f56c |
02-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for expressions in .sleb/.uleb directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118023 91177308-0d34-0410-b5e6-96231b3b80d8
LF/leb128.s
|
| cf667be17b479fe276fd606b8fd72ccfa3065bb8 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-vld-encoding.s
|
| 933b314c761f3338ebc59aa089983681274054bd |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use ARM-style comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.s
|
| 95b9766fea46c78f389793d557158077383b9ff4 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Use ARM-style comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117941 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-abs-encoding.s
RM/neon-absdiff-encoding.s
RM/neon-add-encoding.s
RM/neon-bitcount-encoding.s
RM/neon-bitwise-encoding.s
RM/neon-cmp-encoding.s
RM/neon-convert-encoding.s
RM/neon-dup-encoding.s
RM/neon-minmax-encoding.s
RM/neon-mov-encoding.s
RM/neon-mul-accum-encoding.s
RM/neon-mul-encoding.s
RM/neon-neg-encoding.s
RM/neon-pairwise-encoding.s
RM/neon-reciprocal-encoding.s
RM/neon-reverse-encoding.s
RM/neon-satshift-encoding.s
RM/neon-shift-encoding.s
|
| 4845f990081d466ad193d90d1cd6f1d0eb910309 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117939 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-table-encoding.ll
RM/neon-table-encoding.s
|
| 60b75fad7e065254d50894aa13790865e5f2785b |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117938 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.ll
RM/neon-sub-encoding.s
|
| 3b5dfcd8fd9edce8019b6d7541e2a3c5159b2852 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117937 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.ll
RM/neon-shuffle-encoding.s
|
| 2bcb989a0b8ad196473b0560c8e017c2ac387562 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117935 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shiftaccum-encoding.ll
RM/neon-shiftaccum-encoding.s
|
| d1d73b03afec3475dc8e1f2c2de6945116c9581d |
01-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117932 91177308-0d34-0410-b5e6-96231b3b80d8
LF/debug-line.s
|
| c70a1d985aca40b33b3e4b046b179f0d5e5e238b |
01-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Write the line info to .debug_line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117930 91177308-0d34-0410-b5e6-96231b3b80d8
LF/debug-line.s
|
| 833c93c7958dbbd9d648f331091fbfbeabf342e6 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/arm_word_directive.s
RM/neon-abs-encoding.s
RM/neon-absdiff-encoding.s
RM/neon-add-encoding.s
RM/neon-bitcount-encoding.s
RM/neon-bitwise-encoding.s
RM/neon-cmp-encoding.s
RM/neon-convert-encoding.s
RM/neon-dup-encoding.s
RM/neon-minmax-encoding.s
RM/neon-mov-encoding.s
RM/neon-mul-accum-encoding.s
RM/neon-mul-encoding.s
RM/neon-neg-encoding.s
RM/neon-pairwise-encoding.s
RM/neon-reciprocal-encoding.s
RM/neon-reverse-encoding.s
RM/neon-satshift-encoding.s
RM/neon-shift-encoding.s
RM/simple-fp-encoding.s
|
| cc3acee7b3e1f5813ac604bee18928410270f464 |
01-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117922 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_values.s
|
| 484291c27319668ad99cb87def000254357736fb |
01-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement .weakref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117911 91177308-0d34-0410-b5e6-96231b3b80d8
LF/weakref.s
|
| acc473fcf9860567d4da60625944d48b075d28f8 |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
"mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits. Support this memory form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| b501d4f673c0db267a76800339f9943f2ce6fe33 |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Implement enough of the missing instalias support to get
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
|
| b8d14a6611276181f9fd0d9b2a1243150e4a5739 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117900 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.ll
RM/neon-shift-encoding.s
|
| 4164f6bbbf4ebce676e8a6c0a0cf7a78ef46a0f3 |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
make the asm matcher emitter reject instructions that have comments
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
|
| 1a1ecc9f3c2684249bd765d1299302d629aaf4fe |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
for shl. Caught by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| 905b8f76142b43cd33c36c554d359ee8740f51d5 |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add a test for the ud2a alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117803 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| 52925b60f1cd4cf810524ca05b00a207a926ab9f |
30-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
RM/simple-fp-encoding.s
|
| d179886f0595eb3564a9edfdfff79def130d89cc |
30-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Be more strict on when we produce an undefined reference. In gas a file with
just
.type foo,@object
will produce an undefined reference to foo. On the other hand, a file with
just
.weakref bar, foo
will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.
With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.
This is in preparation for a patch implementing .weakref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117735 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
LF/size.s
LF/undef.s
|
| 05cee0cdb4121bbb52c1ecc9d9e996dcf268ac65 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117708 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-satshift-encoding.ll
RM/neon-satshift-encoding.s
|
| 9ae33fe396e5f7c050a60980e00a99435533c02f |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117704 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-reverse-encoding.ll
RM/neon-reverse-encoding.s
|
| 82c85b7490c9f12eccbdf5c69b1116f0eb5af036 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117699 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-reciprocal-encoding.ll
RM/neon-reciprocal-encoding.s
|
| fea34d38b41c42bb5a4d1d6ab8f8c2e7635d8738 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117696 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-pairwise-encoding.ll
RM/neon-pairwise-encoding.s
|
| 5c4966e1e5285b5971f179f8e7b173281a7d92bc |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117694 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-neg-encoding.ll
RM/neon-neg-encoding.s
|
| ffe2a4a77d463ea1921c8d7e521fa74ad6cea776 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117693 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.ll
RM/neon-mul-encoding.s
|
| 9fcafb0269f22a362b4a2637ae78e74a3765c23d |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117690 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.ll
RM/neon-mul-accum-encoding.s
|
| 2457b550036862461706511b9c13e000ce95f121 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117689 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.ll
RM/neon-mov-encoding.s
|
| cd410ac70cb1d8041946291d4bc7bfb9366b7d2c |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117686 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-minmax-encoding.ll
RM/neon-minmax-encoding.s
|
| 95d3711a159b1db06d4233e8670dcc92ac1e3b70 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117685 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-dup-encoding.ll
RM/neon-dup-encoding.s
|
| b0cb6b820b958ea7f92d491bbc8df558a6b7464b |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117684 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-convert-encoding.ll
RM/neon-convert-encoding.s
|
| afe18c7cacf94f665a4f00755c41aa2b39d3941e |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117683 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.ll
RM/neon-cmp-encoding.s
|
| 7af3f381ee1b6765bb588bb43e5ac0e3923119bc |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117682 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.ll
RM/neon-bitwise-encoding.s
|
| a007781bdf0e9147165d3b2e5aa21e58c3b7c8b0 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this file to less fragile .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117681 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitcount-encoding.ll
RM/neon-bitcount-encoding.s
|
| 48469e11c90e70b2821f89a516d25f49d0fc8802 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117679 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-absdiff-encoding.ll
RM/neon-absdiff-encoding.s
|
| 14a596258d299d174ebd47cc501cb019b8c99ba0 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to a .s file to reduce fragility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117676 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-abs-encoding.ll
RM/neon-abs-encoding.s
|
| 1cfb04390157cdba29216e0bbc2f396124ae14a1 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to a .s file, so that it's not sensitive to codegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117633 91177308-0d34-0410-b5e6-96231b3b80d8
RM/dg.exp
RM/neon-add-encoding.ll
RM/neon-add-encoding.s
|
| 14b93851cc7611ae6c2000f1c162592ead954420 |
29-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add simple support for addrmode5 operands, allowing
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| f4b0f3e616272556e8a94d86edd2e4e597183cd6 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Improvements to .section parsing:
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G
We ignore the G arguments and flag for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117608 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| 94074a5e4dc8c8a4338a08a93f9d2d03e1bf0b00 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
most simple arm instructions match correctly now,
it looks like we're not handling [] operands though
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117607 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 4e692ab5eeb6cf49dbb9ec9ade21cd91b081ba10 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the asmmatcher generator to handle targets with no RegisterPrefix
(like ARM) correctly. With this change, we can now match "bx lr"
because we recognize lr as a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
|
| 787c33718da09d3f0e4600b30c7d59e6c2632966 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the .string directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117592 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_ascii.s
|
| 1973d4379250a88938a9358c12d96e96bdc8dede |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Defined weak symbols should have non-zero value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117585 91177308-0d34-0410-b5e6-96231b3b80d8
LF/weak.s
|
| 29129728f1d4febe44792d1481077cc47fe83a08 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix relocations with renamed symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117575 91177308-0d34-0410-b5e6-96231b3b80d8
LF/rename.s
|
| f571f9a8fe764d5010970e45203415cb00eab739 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Aliases defined with .symver should copy the binding of the symbols they alias.
Move the existing patching for undefined symbols so that all the patching
is done in the same function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117570 91177308-0d34-0410-b5e6-96231b3b80d8
LF/symref.s
|
| 50e7a787099b8031c3f9754c30179061eb8233b2 |
28-Oct-2010 |
Roman Divacky <rdivacky@freebsd.org> |
Implement .equ directive as a synonym to .set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117553 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_set.s
|
| aa8f1f01352bdaaabf712369f8a8a615c776b508 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement R_X86_64_DTPOFF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117548 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| b4d1721eff7b43577e5f2e53f885973fb6c43683 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement TLSLD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117547 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 0cf15d61b7e3bf53f5a99f58ada37b93bc039559 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement DTPOFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117546 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| a264f72d3fb9dec1427480fcf17ef3c746ea723a |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement TLSLDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117544 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| a0a2f8734cdfc19d44201b791a969bcdda96bb70 |
28-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117543 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 9c3e8e28bd236e95117a25f07d3b466d2db80285 |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful.
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117530 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-absdiff-encoding.ll
RM/neon-add-encoding.ll
RM/neon-bitwise-encoding.ll
RM/neon-cmp-encoding.ll
RM/neon-minmax-encoding.ll
RM/neon-mul-accum-encoding.ll
RM/neon-mul-encoding.ll
RM/neon-pairwise-encoding.ll
RM/neon-reciprocal-encoding.ll
RM/neon-satshift-encoding.ll
RM/neon-shift-encoding.ll
RM/neon-shiftaccum-encoding.ll
RM/neon-shuffle-encoding.ll
RM/neon-sub-encoding.ll
RM/neon-table-encoding.ll
RM/simple-fp-encoding.ll
|
| cfd0e1f3ae97ac20b92649b4a6c75930b1f8b19e |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vtbl and vtbx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-table-encoding.ll
|
| 3eff4af42ddbac97807348eadd292ff5f276fe69 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shuffle-encoding.ll
|
| 0bccec368a55e80a2911dcb448cdffabf6bcea98 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vrev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117502 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-reverse-encoding.ll
|
| 498ec20703c89d0c2890b0967791f0f5f2b59a2f |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-convert-encoding.ll
|
| d2fbdb7f5c85d2191514953bdba0fae7b788e623 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the get_lane and set_lane variants of vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.ll
|
| 3cede2d0b2b6cc0a06f55da7c2f8e4263ec0091e |
27-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117494 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 529b1a43986265fb399eecd0dcbf9c409d049853 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added the x86 instruction ud2b (2nd official undefined instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| bc82d8b84f6ae15985d1b01e720ed5c37d714012 |
27-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117481 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| f587a9352a80bc62d9d521d5051c69d1fefecca7 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vdup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-dup-encoding.ll
|
| 4fa3478fc2bf622eaa249602c23b9b3c23d7f2eb |
27-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Set default type and flags for .init and .fini.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117471 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| 82203218d1d801e5c0bdc33fe6afac2e91939a03 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117469 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mov-encoding.ll
|
| 027c84dd3ea886c89ddebaa4badce74e2e462c7f |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vcls, vclz, and vcnt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117466 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitcount-encoding.ll
|
| df800f1b1ba1f406596301329797e44d4c4dc918 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vneg and vqneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117463 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-neg-encoding.ll
|
| 83ff4d2b0d6133d48055a27fe25c5d241bca7e9b |
27-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce an error for an invalid use of .symver.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117462 91177308-0d34-0410-b5e6-96231b3b80d8
LF/invalid-symver.s
|
| 633919c79a86e36b26fb62007731341a31f2188d |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vabs and vqabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117460 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-abs-encoding.ll
|
| 0745c389d903bf9d8a8705ff49bea818a6be6c52 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsli and vsri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shiftaccum-encoding.ll
|
| dd31ed67e67ffa9c7817d96d69e98c0eab8d1e90 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsra and vrsra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shiftaccum-encoding.ll
|
| bf052ac5d1c8f21075bc675f629709c20791c5f7 |
27-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Symbols defined as the difference of other two end up in the ABS section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117451 91177308-0d34-0410-b5e6-96231b3b80d8
LF/abs.s
|
| 88182132470527e27231f09b25a885893e528c66 |
27-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the .symver directive. This is really ugly, but most of it is
contained in the ELF object writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117448 91177308-0d34-0410-b5e6-96231b3b80d8
LF/symref.s
|
| e460890351ed36fa518960a417d85964c2b29eee |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| 5a378076a44ef3f507b91aa8e7715fabaec42074 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| f4630ecc3f2b80440b2d9e59add56a3b422de684 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| 41e8cc73cf570754fffdc6963321c153a8010458 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| 86ed2324a6d2fa54d22afa96520de9e7c9fba28d |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-satshift-encoding.ll
|
| 632c235a316e38e5d0c6d66498064bc3e391fab1 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.ll
|
| 6a36ad75a40a5baeb254fc66e26e2f0c9af1a504 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vshll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117399 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.ll
|
| 4ba5d61f2de316d67a73c3536fe146daf9fb7cca |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vshr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117396 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.ll
|
| 3557d00a388585b8827d3e864cb8cd24ee42368a |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vshl, register and immediate forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-shift-encoding.ll
|
| 61e3b91da711659c3cca5c4c6026a4b2aea322b4 |
26-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for .ident.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117389 91177308-0d34-0410-b5e6-96231b3b80d8
LF/ident.s
|
| c8cb3535a9828dc8e8ce8587e35ef77c8e8ef2a0 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117385 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-reciprocal-encoding.ll
|
| 6915cdab8fbda9fd558d538f1b58b2a4eaa16445 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encodings of vpmin and vpmax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117382 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-pairwise-encoding.ll
|
| bc4118bd36d90bf7fba68d6b274afb089f295e98 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encoding for vpadal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-pairwise-encoding.ll
|
| 000e105d0f32db81d8a4913b1f58b78ba0642e3c |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vpadd and vpaddl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117377 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-pairwise-encoding.ll
|
| a88ea03bf22ba098f1b7d3471d98f3303dcbd33f |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encodings for vmov and vmvn of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.ll
RM/neon-mov-encoding.ll
|
| e4f506ff4ba8ddc70b6b7c77feceabb0b53b6ccf |
26-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement some relaxations for arithmetic instructions. The limitation
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117364 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relax-arith.s
|
| 7c730e77908123a83abcfffe781d368e9b873ce9 |
26-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
When the "true" and "false" blocks of a diamond if-conversion are the same,
do not double-count the duplicate instructions by counting once from the
beginning and again from the end. Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end. Radar 8589805.
This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction. That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117333 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 93ef3fd9c0a7737a26fee867a00de7bcf492a430 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vmax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117327 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-minmax-encoding.ll
|
| a13067e3661402262c44f8dd15e23cacffc4392d |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vmin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117326 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-minmax-encoding.ll
|
| 5258b619667c54d3f07c12031fa0d75595a25527 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vabal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-absdiff-encoding.ll
|
| 410aebc670ea1ae0412dc2bbe0b4b79f25e53ce0 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vaba.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-absdiff-encoding.ll
RM/neon-bitwise-encoding.ll
|
| 28bae6106f3f591e6f174fe269d261d710cb0062 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vabdl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117303 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-absdiff-encoding.ll
|
| b7e1d77ff5999ee32e8ea096fe0458d622f83be4 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vabd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117302 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-absdiff-encoding.ll
|
| b1e0f76352cd4a050834f57805e5c6481fd9329f |
25-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Fix relative precedence of {+,-} and comparison ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117299 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| bdf90d679befafe70b93082042266ba58a9ad0b2 |
25-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmLexer: Fix bug in source location for Slash token.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117298 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 048a19abe69d0c7968715ec12637e79a4f3707ca |
25-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
tweak test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117297 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 6b13effe825678634368f925329a0a1d808a9be6 |
25-Oct-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Rewrite test to actually check some parts of expression parsing,
now that we have macros and friends. Uncovered a bug in macro expansion...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117295 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 31e6ed890a5336779fa191a98af1fc0513380180 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.ll
|
| 4110b4325da839e17dae901996b2263a1c672c87 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vbsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.ll
|
| 162875a9f3be40bfccc07c29ea4ad19f599b9ee4 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct instruction encodings for vbic, vorn, and vmvn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.ll
|
| 8c71eff59439708a61a2c65919ccf9c2791d1f1b |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vand, veor, and vorr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-bitwise-encoding.ll
|
| c61ec2a2b0c0f5f64b88b36780b992cfbd4b8f3e |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vtst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117277 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.ll
|
| d0c5b6170f97aff20dbc1e7f24e56a7cfdcb653c |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encoding tests for vcgt and vacgt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.ll
|
| 10c15e5d584d8f9ee44740eca3991a63bb45a90d |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vcge and vacge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.ll
|
| 4fe20bbd668528a82254e4fb9152daa4d30af684 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add a warning about our inability to test the encoding of vceq with immediate zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.ll
|
| a2041f18078e60cdd4f1cf3064c7dd9466c227e6 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vceq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117270 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-cmp-encoding.ll
|
| 8b7ce020c3c471f4ba9caa5cc194cad445cd02c3 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsubhn and vrsubhn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117269 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.ll
|
| c052a8c772b1d55e5ed1a34f1750dac20c66c641 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vqsub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117214 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.ll
|
| 61f34bc4bc52c3ec61dd2c392804e60b65edee47 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vhsub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117189 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.ll
|
| 48c9f2081d9d26a019ecadde5493f7a094896bc8 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a CMP test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117187 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 884f22869248db5eab10abd88f556230ab91b51a |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsubw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117186 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.ll
|
| 2b6b97c815da7d36666638a37ed646a7be0586cf |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsubl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117183 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.ll
|
| 313252022d1612faab610e682ea0d03789506934 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117177 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-sub-encoding.ll
|
| c9db3314333c34458f6648088cdabbbc96696e9a |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vqdmlsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117173 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.ll
|
| 353f8668b8fff8a5e2cfdbb01dc48ae1104d6804 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vmlsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117171 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.ll
|
| 432a8142ef8efc4978ceb8d257a21240e2d29777 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117166 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| f8da5f5dfa5e847d76bf20d0ec4940e3ca51d275 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 458509476bd0f9911965de3b550d3f9c43303b0b |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for the correct encoding of NEON vmls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117145 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.ll
|
| 9b264972734a96b7956d3ff7ad6d7b5dcf5baf39 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqdmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.ll
|
| 385e136dce9f77ad949f54277b33b31c0d1f1588 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add the encoding information for the rest of the ARM mode multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 92205842ca21952929eef1571a9b5b6c758540e0 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.ll
|
| 18341e9e31b95ff865530e04662f540e2cdf3382 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vmla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-accum-encoding.ll
|
| 3870b750e6d8af533926138e670f4643a5953e42 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instuction binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 81faa805ce9f4ec2ff926703671cc76694a925f0 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add testscases for encoding of NEON vdqmull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117115 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.ll
|
| 9463d0e400d4bac590960ba5593d7850870f7187 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instruction encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 0966ec08610c02c8556105f2fff88a7e7247a549 |
22-Oct-2010 |
Andrew Trick <atrick@apple.com> |
Reverting r117031 to cleanup valgrind errors.
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86-32.s
86/x86-64.s
|
| 751752e7caee441c0b50585c77637b36b048f235 |
22-Oct-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed handling of immediate operand sizes, which
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117084 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| 4ceccc4e575b6f51bad18a6c16de1877c756598c |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vmull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117077 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.ll
|
| 3686046a2cad2e3d62c7fbee9aadae1bf242fa4a |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encodings for MVN variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| de5370fcbb332413492c74593e152e7c0c61b8a1 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vqdmulh and vqrdmulh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117074 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.ll
|
| 3fea19105d4929ad694f0b6272de31924c9f9f09 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM Binary encoding information for BFC/BFI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 636ad14c8a93f914330bd7340ce56b030f06ab4f |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON vmul encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117069 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-mul-encoding.ll
|
| 7eca0e17baeb70da9a272f33e06ac542116aed71 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Rename this test to better reflect its contents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117067 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-add-encoding.ll
RM/neon-fp-encoding.ll
|
| 35ea7a4022af6cce13f1ec642c3d607aae05ed45 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vaddhn and vraddhn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117064 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-fp-encoding.ll
|
| 4bcb949e18d930765b4f0aabf93cc484dce9d159 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vqadd, which was already correctly encoded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117059 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-fp-encoding.ll
|
| 1e93466c3a5556db0bd87755e10e2938c2a43c1f |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vhadd and vrhadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-fp-encoding.ll
|
| 9d50559bae511cd75ea61efb7189e4b954ab4175 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vaddw.s* and vaddw.u*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-fp-encoding.ll
|
| e0e6dc3f4ec31c98f6860c56cad406d3882db428 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-fp-encoding.ll
|
| 8c8bc05a383890ab29b288625c746bf24240e9a1 |
21-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Do not recurse into symbol refs that have a variant kind. This prevents us
from losing the variant when producing a relocation on an alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117037 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias-reloc.s
|
| 0b9325c97d031ab0e9a240d69a2be11ec1559e37 |
21-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117031 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32-coverage.s
86/x86-32.s
86/x86-64.s
|
| ba3f88100792b020f69ad1e44ec8c784407435a4 |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117002 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 5b7a825ec5551fd1dff8c9f280cc203da3fdedd9 |
21-Oct-2010 |
Andrew Trick <atrick@apple.com> |
putback r116983 and fix simple-fp-encoding.ll tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| d7795540d0538fb79e70d0519858d463ac4375af |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Implement correct encodings for NEON vadd, both integer and floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
RM/neon-fp-encoding.ll
|
| 01aabdac44af241a9a70c3d6ef8d5007e3e80ce1 |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for moving a value between two ARM core registers and a doublework
extension register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 7d31a169af3c49f54e8dd59bb3a75b37afad890b |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for movement between ARM core registers and single-precision
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 64e6719ee870f88db445feac0a1d5f597a7549e3 |
20-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle _GLOBAL_OFFSET_TABLE_ correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116932 91177308-0d34-0410-b5e6-96231b3b80d8
LF/global-offset.s
|
| f7d5278fb32b84b6218a222346202ab3af17057c |
19-Oct-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Fixing r116753 r116756 r116777
The failures in r116753 r116756 were caused by a python issue -
Python likes to append 'L' suffix to stringified numbers if the number
is larger than a machine int. Unfortunately, this causes a divergence of
behavior between 32 and 64 bit python versions.
I re-crafted elf-dump/common_dump to take care of these issues by:
1. always printing 0x (makes for easy sed/regex)
2. always print fixed length (exactly 2 + numBits/4 digits long)
by mod ((2^numBits) - 1)
3. left-padded with '0'
There is a residual common routine that is also used by
macho-dump (dataToHex) , so I left the 'section_data' test values alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116823 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
LF/align-bss.s
LF/align-nops.s
LF/align-size.s
LF/align-text.s
LF/align.s
LF/basic-elf.ll
LF/common.s
LF/common2.s
LF/diff.s
LF/empty.s
LF/entsize.ll
LF/entsize.s
LF/file.s
LF/got.s
LF/local-reloc.s
LF/merge.s
LF/norelocation.s
LF/pic-diff.s
LF/plt.s
LF/relax.s
LF/relocation-386.s
LF/relocation.s
LF/section.s
LF/size.s
LF/sleb.s
LF/uleb.s
LF/undef.s
LF/undef2.s
LF/weak.s
LF/zero.s
|
| 1dcb1eafbc0c94dc0cb9cd0d3f002524de8a5a92 |
19-Oct-2010 |
Eric Christopher <echristo@apple.com> |
Speculatively revert 116753 and 116756 to attempt to fix the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116777 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
LF/align-bss.s
LF/align-nops.s
LF/align-size.s
LF/align-text.s
LF/align.s
LF/basic-elf.ll
LF/common.s
LF/common2.s
LF/diff.s
LF/empty.s
LF/entsize.ll
LF/entsize.s
LF/file.s
LF/got.s
LF/local-reloc.s
LF/merge.s
LF/norelocation.s
LF/pic-diff.s
LF/plt.s
LF/relax.s
LF/relocation-386.s
LF/relocation.s
LF/section.s
LF/size.s
LF/sleb.s
LF/uleb.s
LF/undef.s
LF/undef2.s
LF/weak.s
LF/zero.s
|
| 87f4a1a4331e40cbba28e829561759d146273840 |
19-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added a few tweaks to the Intel Descriptor-table support instructions to allow
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| e7d4a4c6c882907da11adcaaacf1a2f464214e87 |
18-Oct-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Changed elf-dump to output hex format by default.
Also updated tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116753 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
LF/align-bss.s
LF/align-nops.s
LF/align-size.s
LF/align-text.s
LF/align.s
LF/basic-elf.ll
LF/common.s
LF/common2.s
LF/diff.s
LF/empty.s
LF/entsize.ll
LF/entsize.s
LF/file.s
LF/got.s
LF/local-reloc.s
LF/merge.s
LF/norelocation.s
LF/pic-diff.s
LF/plt.s
LF/relax.s
LF/relocation-386.s
LF/relocation.s
LF/section.s
LF/size.s
LF/sleb.s
LF/uleb.s
LF/undef.s
LF/undef2.s
LF/weak.s
LF/zero.s
|
| eada30479399014c22c7b7edb008177c312eefee |
18-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement R_386_GOT32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116744 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| ce2d3c57758619e99a99104e1168a9558658fab0 |
18-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Relocate with .bss instead of using the symbol. Matches gas behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116741 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| aa85c216334a6adac7e0a154d357b370629dc1bc |
18-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce ELF::R_386_GOTPC relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116728 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| 7aef62ff8c72506cc9b77333d25f4aa8aa9cf9fe |
18-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added a handful of x86-32 instructions that were missing so that llvm-mc would
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
86/x86-64.s
|
| 9edab3a9e15c40c1c9bf70df81c6afdab1cd02c2 |
18-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce a R_386_PLT32 when needed. Moved the default cases of switches to the
start for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116715 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| c97f80efc80030c7544a9903c79d2dccd197a0ff |
18-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle GOTOFF correctly on i386.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116711 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation-386.s
|
| f230df9af4012f9510de664b6d62b128e26a5861 |
16-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a MCObjectFormat class so that code common to all targets that use a
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116675 91177308-0d34-0410-b5e6-96231b3b80d8
LF/diff.s
LF/diff2.s
|
| d30dcfe3312cc0a7c48834b7063a84c111b0b762 |
16-Oct-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Unbreak test on non-COFF targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116669 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/weak.s
|
| 4cee2890a66974af506f2125243114cc14bd5556 |
16-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Add support for default-null weak externals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116666 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/weak.s
|
| 8abe32af38b66bf4577526b23b6af6ec7eb6c155 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for UBFX and SBFX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 5df0b65e8f5ef55f0b515a0b24879f5d117d6042 |
15-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Refactor code a bit and avoid creating unnecessary entries in the string
map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116579 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
|
| cfbece50f602c561c5eac046bcfc9a07c8c006cb |
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 53e7dcbd47c6ca34c0cd00c35b09ee5a2be7afe1 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify test file a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116540 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 8faff9c759f8d87cfb4f0cb604d1dbc9842ae07b |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
are just forms of that instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116538 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 1de588df69ceb999dd4680679cc3fe519bf9a124 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MOVi16 and MOVT ARM mode encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| a0949b50dcea35c08b50542091f97275f401529d |
14-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove some code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116484 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
LF/undef.s
|
| bbbdcd453d22258cb4dd217eddf016668fcebf84 |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 946a2740a54fe2cd57509999384239101bf5b9df |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for 'fmstat'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 88cf038436a142611424c895c601731ffa7c993f |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| b3af5de2d97c30355b8109e149326b0664d34085 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 67a704de03b7466c3bd696c3d40780d277134d57 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| b35ad41fef5d1edd9495f708fb7eae1a0a94ef9d |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 24989ecc70ad7bbbfc135fe341484ef4fdeabd09 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode operand encoding information for ADDE/SUBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 6932643a371b7a6dcc0c2b4f3a38b6b18759da87 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 54908dd72b1c6add6f3d074df1b67060e5b57025 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VCVT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 89c898f8af3e96db25fe4986b7e7f27663ebe26a |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 1fc6d8837f03471b815a9312091b9432939b49fc |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add VCMPZ and VABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| cd776862544518e215b5af8a294f5026ee844684 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor VCMP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 5a1fd8cf68a120e0f4a1e71773422a7d5a284a50 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNMUL[SD].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| caa3d467ab849ebf671441f3adf1ecda715e98fe |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VDIV and VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| c14b80f6d3f93777591fa4619b3f3a2b6f92ffaf |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Be nitpicky and line up the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116365 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| dd3bc112e6545634d9700c777c975f072128a51b |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 6e8bf26342c88940e530cf008ea3fc6be56ec836 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't need to specify calling convention. Add 'readnone' to functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116354 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 174777bb2b0a1896afb5dc5ff96a91d162d00149 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Encoding for VADDD. Plus a test for the VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-fp-encoding.ll
|
| 0de6ab3c43ed2143d661115dddf1480545236c91 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoding information for the remainder of the generic arithmetic
ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 42fac8ee3bc02e18a5887800e812af762b45b9eb |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MC machine encoding for simple aritmetic instructions that use a shifted
register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| 28ca86aa19fe2a5493573164ef0c2c54542ed9da |
09-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116155 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/bss.s
|
| 192d136750b376d46bf030a6d5a4c098b0768826 |
09-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Implement InitSections. Fixes PR8335.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116151 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.s
OFF/module-asm.ll
|
| 7d4900416af3813aa9473e6ec2f0497ad5d208dd |
09-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Add COFFAsmParser. Completes PR8343.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116150 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/align-nops.s
OFF/basic-coff.ll
OFF/basic-coff.s
OFF/simple-fixups.ll
OFF/simple-fixups.s
OFF/switch-relocations.ll
OFF/symbol-alias.ll
OFF/symbol-alias.s
OFF/symbol-fragment-offset.ll
OFF/symbol-fragment-offset.s
|
| 56ac907c57fcfddfd650238f03c856a9d55987e5 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement a few more binary encoding bits. Still very early stage proof-of-
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| ff9dfedd101e1a591ec8f7fac9999777cde80efb |
08-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Call InitSections in llc and clang so that the binaries produced by them
are easier to diff with those produced by llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116095 91177308-0d34-0410-b5e6-96231b3b80d8
LF/entsize.ll
|
| 0f448b5bf682c16c23c7ec239eb74f08d333e8c1 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add test file for simple ARM binary encodings with MC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116024 91177308-0d34-0410-b5e6-96231b3b80d8
RM/simple-encoding.ll
|
| adab850daaed40bc022bd4f37ff643154a9e2bd1 |
08-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Add test for my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116015 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/simple-fixups.ll
|
| b5814a3c152bbb7097a6d90168ce6eabde788c60 |
07-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Fix symbol aliases. Fixes PR8251.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115909 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/symbol-alias.ll
|
| 152c1061e0b4ad379eec5fa38ee0091fc11ff936 |
06-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Get binding and visibility info from the the alias, but Type from the symbol
being aliased.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115836 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
|
| 153666c0384c724c1a935be44a1afe0319649e3e |
06-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
If a symbol is global, reloc against it even if it is in a mergeable section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115817 91177308-0d34-0410-b5e6-96231b3b80d8
LF/merge.s
|
| 3223f19ff0920ffee686faba3bf74babf580e8a5 |
06-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make sure weak symbols are listed after the local ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115795 91177308-0d34-0410-b5e6-96231b3b80d8
LF/weak.s
|
| 8cecf253e45f144b9a7fd0ace85eeeeb0bebfc83 |
06-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly handle GOTPCREL relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115793 91177308-0d34-0410-b5e6-96231b3b80d8
LF/merge.s
|
| 3729d0052bda365d04fee900c6f3d09460f1e108 |
06-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Use a relocation against the symbol if it is a PLT and the symbol is in another
section. Common because of linkonce sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115718 91177308-0d34-0410-b5e6-96231b3b80d8
LF/merge.s
|
| 01f9ea35a71b4efb00de8e4c9e9136c9c88f6273 |
06-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement more alias cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115699 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
|
| 508fc4708bb859391af8969614e67c84ab56c38c |
05-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
gross hack (having the asmmatcher handle the alias).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-64.s
86/x86_64-imm-widths.s
|
| 62fed8bd380b67f47bde3ff2a437db0951c7d186 |
05-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't crash in a strange .size directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115684 91177308-0d34-0410-b5e6-96231b3b80d8
LF/size.s
|
| eb6e77f8cccd14cdba995ff8231f2c9faea9bfcc |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Fix (PR8278) temporary symbol relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115656 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/symbol-fragment-offset.ll
|
| e452b171306ac255dedc46a49defc866a65184c6 |
05-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for a fill value in the .zero directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115655 91177308-0d34-0410-b5e6-96231b3b80d8
LF/zero.s
|
| 737cd213e359c2862253c3a1ee443419566e90b9 |
05-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement a simple alias case and refactor the code a bit so that the
isInSymtab and isLocal logic in the two loops don't get easily out of sync.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115643 91177308-0d34-0410-b5e6-96231b3b80d8
LF/alias.s
|
| a25c0a4283e627a34a3fb3cf0ed2ddde0d886a36 |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
test/COFF: Fix symbol indexes and names. Update tests to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115642 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.ll
OFF/symbol-fragment-offset.ll
|
| f191d120b1ea9cb132270d35dc133b419183e687 |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
test/COFF: Remove temp file usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115641 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/align-nops.s
OFF/basic-coff.ll
OFF/symbol-fragment-offset.ll
|
| cc1f91c83305c446090c0ae127e1324c3c9eae08 |
05-Oct-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Cleanup Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115639 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/align-nops.s
|
| 5c77c16f311d702a315547c0eb32b7a34a9d55c8 |
05-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce a undefined reference to _GLOBAL_OFFSET_TABLE_ when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115623 91177308-0d34-0410-b5e6-96231b3b80d8
LF/got.s
|
| 266a69f3753951fb9a928f214d3e654bef5671b5 |
05-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Tests that now pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115622 91177308-0d34-0410-b5e6-96231b3b80d8
LF/merge.s
LF/undef.s
|
| 90371ad16529099d53e78b1c6ac0c7e8b6374153 |
05-Oct-2010 |
Sean Callanan <scallanan@apple.com> |
Added a testcase for the ENTER instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115580 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| 607d1f6d3216b647c07965bafae8d1aba6312136 |
04-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement ELF::R_X86_64_GOTPCREL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115547 91177308-0d34-0410-b5e6-96231b3b80d8
LF/got.s
|
| 92bf6684f62e1df48ecc0a9b3cc3a99ce7c00747 |
04-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce a R_X86_64_PLT32 when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115541 91177308-0d34-0410-b5e6-96231b3b80d8
LF/plt.s
|
| 28f9ac81012e1e278128a4148e93f6ab873f15d8 |
04-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce a R_X86_64_GOT32 when needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115537 91177308-0d34-0410-b5e6-96231b3b80d8
LF/got.s
|
| 083cf1574facc9ce468fba1735c794bd7e520108 |
04-Oct-2010 |
Jan Wen Voung <jvoung@google.com> |
Add hook in MCSection to decide when to use "optimized nops", for each
section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115523 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/align-nops.s
OFF/dg.exp
LF/align-nops.s
|
| 55fb102130925ada2bbc78abbbb70394d96d945e |
04-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Include the section address in the computation of the relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115509 91177308-0d34-0410-b5e6-96231b3b80d8
LF/pic-diff.s
|
| 01263d35d4c037a882dbfa6364eb0f6c4e0d87a8 |
04-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly compute the relocation when it is not in the first fragment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115506 91177308-0d34-0410-b5e6-96231b3b80d8
LF/pic-diff.s
|
| d32d85e5ba2de223c853b2e1c9bd57a39ebab4ce |
03-Oct-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Add 3DNowA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115477 91177308-0d34-0410-b5e6-96231b3b80d8
86/3DNow.s
|
| 591d76ea5a10062316e18075eccd4c62d60b5a80 |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| cc07d7116a7d398b2e1da9ad8bc17f7bf74164f5 |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add support for the prefetch/prefetchw instructions, move femms into
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8
86/3DNow.s
|
| f132fa0e74b5faa5f7095cbe0dcf87e72939b588 |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
what the heck, add support for the rest of the 3dNow! binary operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115467 91177308-0d34-0410-b5e6-96231b3b80d8
86/3DNow.s
|
| 548abfcbd671b1144bf517b17643259dcae76f4f |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Implement support for the bizarre 3DNow! encoding (which is unlike anything
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
86/3DNow.s
|
| 9d8b7555cde8b9722dd6f8dc77c627bae0718c67 |
03-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement a very basic PIC case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115454 91177308-0d34-0410-b5e6-96231b3b80d8
LF/pic-diff.s
|
| d47691460770c886cf2fdafaf0f53e0cd101ccf1 |
02-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix a regression introduced in r115243, in which the instruction
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
86/x86-32.s
|
| b539b76038ed072be886a1b29fdcd1623b6ad897 |
02-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
actually, move the elf tests into the existing elf dir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115416 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/elf_directive_previous.s
smParser/elf_directive_section.s
LF/elf_directive_previous.s
LF/elf_directive_section.s
|
| 90b12590b6b907f8c3d83bd48e218990b5f1ed53 |
02-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
consolidate ELF tests into asmparser tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115415 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ELF/dg.exp
smParser/ELF/directive_previous.s
smParser/ELF/directive_section.s
smParser/elf_directive_previous.s
smParser/elf_directive_section.s
|
| 9ab044f20b85597cdaed6849dfc2b55af023906a |
02-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move ARM MC tests up one level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115414 91177308-0d34-0410-b5e6-96231b3b80d8
RM/arm_instructions.s
RM/arm_word_directive.s
RM/dg.exp
smParser/ARM/arm_instructions.s
smParser/ARM/arm_word_directive.s
smParser/ARM/dg.exp
|
| 3286db670c689104c0df4f98fbb4a66f6e4d2db5 |
01-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move X86 subdir up a level
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115292 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/dg.exp
smParser/X86/x86-32-avx.s
smParser/X86/x86-32-coverage.s
smParser/X86/x86-32-fma3.s
smParser/X86/x86-32.s
smParser/X86/x86-64.s
smParser/X86/x86_64-avx-clmul-encoding.s
smParser/X86/x86_64-avx-encoding.s
smParser/X86/x86_64-encoding.s
smParser/X86/x86_64-fma3-encoding.s
smParser/X86/x86_64-imm-widths.s
smParser/X86/x86_directives.s
smParser/X86/x86_errors.s
smParser/X86/x86_operands.s
86/dg.exp
86/x86-32-avx.s
86/x86-32-coverage.s
86/x86-32-fma3.s
86/x86-32.s
86/x86-64.s
86/x86_64-avx-clmul-encoding.s
86/x86_64-avx-encoding.s
86/x86_64-encoding.s
86/x86_64-fma3-encoding.s
86/x86_64-imm-widths.s
86/x86_directives.s
86/x86_errors.s
86/x86_operands.s
|
| 7eae36b38b874f417fa191fc1cfec22c100f164d |
30-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Factor some logic into ShouldRelocOnSymbol. This simplifies the code and
fixes some cases where we were producing relocations with at symbol that
should use a section instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115194 91177308-0d34-0410-b5e6-96231b3b80d8
LF/basic-elf.ll
LF/relocation.s
|
| 1344488d65efcc0c738407ef41d86801f20086a8 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
more cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115178 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86-32-avx.s
smParser/X86/x86-32-coverage.s
smParser/X86/x86-32-fma3.s
smParser/X86/x86-32.s
smParser/X86/x86-64.s
smParser/X86/x86_32-avx-clmul-encoding.s
smParser/X86/x86_32-avx-encoding.s
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-fma3-encoding.s
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64.s
|
| 27c5215fbd59c2e8262dd14d63ada96ce3cfd351 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
merge and clean up tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115177 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86-32-coverage.s
smParser/X86/x86_32-bit.s
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-incl_decl.s
smParser/X86/x86_64-operands.s
smParser/X86/x86_64-suffix-matching.s
smParser/X86/x86_64.s
|
| a879dc717ec9e7d7819d2774147cfb0cc8084480 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
merge two tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115175 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit.s
smParser/X86/x86_32-encoding.s
|
| e73774dbb0e427fa170cf2df86adddd9ad3c20c7 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
rename test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115174 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_errors.s
smParser/X86/x86_instruction_errors.s
|
| 84d7ffdede03c17b68fdbd8d9a98b9e67e004712 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
generalize test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115172 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_directives.s
smParser/X86/x86_word_directive.s
|
| 9e46d78809024f15c1b102ba7c0326649b383b7d |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
rename test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115171 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64.s
smParser/X86/x86_instructions.s
|
| ebfa86b4349bb38732f0b927ed2589b176e69cb5 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
merge two tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115170 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
smParser/X86/x86_instructions.s
|
| 905f2e06691672c236ae864faf0ad7220afc2844 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
preemptively add the rest of the non-n fpstack instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115168 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 5660904a2c41e7545debdecc9b3e98962f5f7cbf |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
merge two tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115165 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_32-mismatched-add.s
|
| 198b9797b4447f27de0c28e09602bb2112dd2263 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix this to not be completely broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115164 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-mismatched-add.s
|
| 18e5179f3d944f9edae90d43ced718d4db4f0178 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
update, unxfail, fix bogus encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115163 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 0d5d7a019c8d76ba2df28fec56e9bb624002a8fc |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
update and unxfail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115162 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
|
| bf840a198ded52612173474df5f60aac34363a79 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
unxfail this by fixing syntactic differences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115161 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit.s
|
| 9ee4aed3b652ea4a4327af2cb1c614dd10cd8b47 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement support for finit, PR8258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115156 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 0bb83a84d4319030c0c9260dbfea461c40eea1b2 |
30-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add support for fstcw, PR8259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115154 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 186e7a0fb1b2028e4fa9c3efe29d9433c91b3f66 |
30-Sep-2010 |
Jan Wen Voung <jvoung@google.com> |
Move logic of determining ELF entsize from the .s printer to initialization
time. That way, the EntrySize field is initialized for other code paths,
namely, the .ll -> .o code path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115141 91177308-0d34-0410-b5e6-96231b3b80d8
LF/entsize.ll
|
| 1b6285cd72c480cd39048539d03b240e3c47d195 |
30-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add another test that now passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115137 91177308-0d34-0410-b5e6-96231b3b80d8
LF/undef2.s
|
| a8c02c3bdd68e65d14fb6b0d56989663754059b0 |
30-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly produce R_X86_64_32 or R_X86_64_32S.
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115134 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relocation.s
|
| 12ad94e03c46c3bba44756bc052e08d6c4341b3d |
30-Sep-2010 |
Jan Wen Voung <jvoung@google.com> |
Have ELFAsmParser.cpp use the already parsed "Size" (entry size) when
constructing a section. Test for a few cases also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115132 91177308-0d34-0410-b5e6-96231b3b80d8
LF/entsize.s
|
| 7070387f08f7dc797b554ed8013cba9f8b74121a |
30-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make it possible for the MCObjectWriter to decide if a given fixup is fully
resolved or not. Different object files have different restrictions and
different native assemblers have different idiosyncrasies we want to emulate
for now.
Move the existing MachO logic to the new place and implement an ELF one that
gets fixups to globals right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115131 91177308-0d34-0410-b5e6-96231b3b80d8
LF/relax.s
|
| a25f933396b8408ad89218bc60b0a93f130a3ea9 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115061 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 9e3922e94975b7b3d98da42f0d20a524f3deed53 |
29-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move "local commons" to the end of .bss to match the gnu as behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115037 91177308-0d34-0410-b5e6-96231b3b80d8
LF/common2.s
|
| 9804db13535d524ed88532d161cf265e72249036 |
29-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a test that I forgot to add with a previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115036 91177308-0d34-0410-b5e6-96231b3b80d8
LF/align-size.s
|
| 6f4202726339815c7167ef2f00858c766c9ffea9 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115029 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| f3654db4588884edbf52f139a2f713e45a8ed9b4 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 2baa2a8cc7d2b85c4220cd8d8f369a6bc088adc7 |
29-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Fix test. IMAGE_SYM_CLASS_LABEL should never have been emitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115024 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/symbol-fragment-offset.ll
|
| 78a194693bb9bbfa1080454cded0166265b803e5 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
order as cctools for diffability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115022 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 8a5072903e2037da1cfdaffa5a26be00f3d76a22 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement support for 32-bit address operands in 64-bit mode, which
are defined to emit the 0x67 prefix byte. rdar://8482675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115021 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| b2ef4c1235c846c2503d0796541f4255ef1e13f5 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add basic avx support to the disassembler, also teach it about ssmem/sdmem
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| bf6018ac5a4ce8db0f0719aa666cd81f0904431a |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115018 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 0c04e4f58f8d1ad4604de17324170fa1f4e43418 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 7c51a3172cf5104ebeaef22f1366fa634ca00d85 |
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://8456378 and PR7557 - support for the fstsw,
an instruction that requires a WHOLE NEW wonderful kind of alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 53725bc57a992e812d08f6ec62d824dfd21425bf |
28-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
On elf, undefined symbols can start with .L.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114958 91177308-0d34-0410-b5e6-96231b3b80d8
LF/undef.s
|
| c3c413f63117896f186fc4385bdaac0578d3613f |
28-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Write relocations in the end of the file. This matches what gas does and
makes files easier to diff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114898 91177308-0d34-0410-b5e6-96231b3b80d8
LF/basic-elf.ll
LF/local-reloc.s
LF/merge.s
|
| 0453dd9ca0165cccd7c68a0425bd6bcfd6c74924 |
27-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make sure .text doesn't produce extra alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114895 91177308-0d34-0410-b5e6-96231b3b80d8
LF/align-text.s
|
| 4f2afe3d399eb9485dc605f3cc3a6382dcae757a |
27-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Handle exponents in floating point literals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114861 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| a72d87899bc1bfdb17744aae2545a21b3630d3c1 |
27-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC-COFF: Drop empty sections, and label symbols. Convert relocations
targeted at symbols into relocations relative to the containing section.
Patch by Nathan Jeffords!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114823 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.ll
OFF/symbol-fragment-offset.ll
|
| 295646274276c6814d970bed86d3b4ff76ba3ee3 |
27-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
yet more aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114822 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| b1162fc05e09c7247be1896fd4aa4ca7e76c938c |
27-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add a couple more aliases, rdar://8456378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114821 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| df967d613704d4e4f01ecce85c1846dfab4d9a1b |
27-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8470918 - llvm-mc can't assemble smovl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114819 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| cb296ec0b689ccbcb08cedc5d3e090c0471eb393 |
27-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114818 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| fd8fddd830ad8322d04161f2f6bad6269a451ab2 |
27-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement support for 'clr' alias. This is part of rdar://8416805,
but balrog was wanting it on irc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114809 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 73ffea47d20bc9f559b4ce0c60166ee504073832 |
25-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
symbols defined in merge sections in independent atoms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114786 91177308-0d34-0410-b5e6-96231b3b80d8
LF/basic-elf.ll
LF/merge.s
|
| a648918eb772d46cd8e14a2ab3489a80500260af |
24-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reapply 114678 and 114667. Reverting them did not fix the bot:
http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/69
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114761 91177308-0d34-0410-b5e6-96231b3b80d8
LF/local-reloc.s
|
| cd4b20a25b6251fb4a2ca50813c10184accab24b |
24-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert 114678 and 114667 to see if
http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost
gets happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114742 91177308-0d34-0410-b5e6-96231b3b80d8
LF/local-reloc.s
|
| facb34b41cea284b5a0b4992ff619e5cfd5e6a22 |
24-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Handle a missed case of floating literals in the lexer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114733 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| b95a079cae7bd5232d17be8a095fa63fe84f4e44 |
24-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Support .single and .double for embedding floating point literals.
- I believe more modern 'gas' supports a more enhanced set of arithmetic on
them, but for now the only thing we can do is emit them as data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114719 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/floating-literals.s
|
| e15eb4e14cd543b925a837026cbdde9f94393e1c |
23-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly handle weak undefined symbols. Before we would get a invalid binding
(2 == STB_WEAK | STB_GLOBAL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114690 91177308-0d34-0410-b5e6-96231b3b80d8
LF/weak.s
|
| b142bef30b2e2ef0c978f5f3041f1d4a429eb9b2 |
23-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Represent relocations against local symbols as relocations against the section
they are in. Both ways should be equivalent, but gas produces relocations
against the section.
Roman wrote the patch, I added the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114667 91177308-0d34-0410-b5e6-96231b3b80d8
LF/local-reloc.s
|
| 59ff3c913449402ad5447bbe3ae6338402fb84b0 |
23-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Avoid some Mach-O specific alignment being done on ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114594 91177308-0d34-0410-b5e6-96231b3b80d8
LF/align.s
|
| 1963572f9de87cd1ac5f16e504e27c3c26267e6f |
22-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Correctly align bss.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114556 91177308-0d34-0410-b5e6-96231b3b80d8
LF/align-bss.s
|
| 2c5291b56358bf239bdfc675ed681c2da3eb4901 |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8456371 - Handle commutable instructions written backward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114536 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 1eb1b68e3a5241591bfa18d4beb0e0cf13a48ef2 |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_operands.s
|
| bc57c6db4a3a1f5df4450d8dbb100e1eb6944c28 |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
Teaching the code generator about CR8-15, how to rex them up, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| f7d4da0c1dcdac3941fe440982bce19706541629 |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8456417 - llvm-mc can't do basic math
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114532 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| c2b942acf6008ac822c21722ac7ec84264d10bef |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add the missing aliases for fp stack cmovs, rdar://8456391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114531 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 33d60d5e56bbf3e9ed02bc916735419091736ca3 |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
Fix rdar://8456364 - llvm-mc rejects '%CS'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114528 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 0c289c140ee7a68e3d06b9d8ae6060758345ad4e |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114527 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 61129252e44067ae112dc856c64c814344b7e7c9 |
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114526 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| f7c10a3cff61c70efe8e405d9bdc5386e8e3fc0a |
21-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement support for .local and its "interesting" interactions with .comm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114382 91177308-0d34-0410-b5e6-96231b3b80d8
LF/common.s
|
| 43779dcfef7f4e921c6fc12bb5394a1b2efcd81d |
20-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Produce a R_X86_64_32 when the value is >=0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114339 91177308-0d34-0410-b5e6-96231b3b80d8
LF/basic-elf.ll
LF/relocation.s
|
| ad49cf586624c400302d17ecc2c2e41ea4346f1a |
18-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make sure the STT_FILE symbol is the first one in the symbol table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114285 91177308-0d34-0410-b5e6-96231b3b80d8
LF/file.s
|
| d3dce16ffef83fbb30be7125d7a38ae2f1a2ab06 |
18-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add test that was missing in my previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114248 91177308-0d34-0410-b5e6-96231b3b80d8
LF/norelocation.s
|
| 92aa1f71230f086ddb3aaf67e18cea6f3d1f3afe |
18-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| 40cc3f8783a4e426a0d439bb2b070b5c072b5947 |
17-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8444631 - encoder crash on 'enter'
What a weird instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 23bea41ec68368f9186db2f819dde11efb1d3c83 |
17-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/i386: Fix a crash in relocation handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114176 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc.s
|
| cceba838935b5018fddf7118bb8b9e6f50bbbe45 |
17-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Add support for 'a + 4@GOTPCREL' and friends, by reconsing the
expression to include the modifier.
- Gross, but this a corner case we don't expect to see often in practice, but
it is worth accepting.
- Also improves diagnostics on invalid modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114154 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/expr_symbol_modifiers.s
|
| 35aa94b229d516b9eb775ad4e13a8e2d03221cf9 |
16-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8438816 - unrecognized 'fildq' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114116 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 71859c640f6a36251aca223fd503c58dc314e296 |
16-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print the address of sections as 0 and create the metadata sections in the
same order as gnu as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114109 91177308-0d34-0410-b5e6-96231b3b80d8
LF/empty.s
|
| 34e3d0cfe525b3067856c8978174fec75223b16a |
16-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make sure that names like .note.GNU-stack are accepted as valid section names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114091 91177308-0d34-0410-b5e6-96231b3b80d8
LF/section.s
|
| 2ea2ac798b07855bd950e848d73b8bea6bcdea4b |
16-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for the .zero directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114077 91177308-0d34-0410-b5e6-96231b3b80d8
LF/zero.s
|
| b9dadc90664237cde4c2ef8c61fe40ebb7ca28c1 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
add a test of an edge case value for the FP immediate (needs all digits of
precision)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114028 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| d80781b98b771d370730ab7c630018f23e202b57 |
15-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a InitSections method to the streamer interface.
The ELF implementation now creates text, data and bss to match the gnu as
behavior.
The text streamer still has the old MachO specific behavior since
the testsuite checks that it will error when a directive is given
before a setting the current section for example.
A nice benefit is that -n is not required anymore when producing
ELF files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114027 91177308-0d34-0410-b5e6-96231b3b80d8
LF/empty.s
LF/sleb.s
LF/uleb.s
|
| 60396975bea44c8d233eb11df2eb7599d2f5fa90 |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| d0bcc9a01590c60adb4d288691120c46a49a2288 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
lcall and ljmp always default to lcalll and ljmpl. This finally
wraps up r8418316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113949 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| cbb442640fdefae48edca2b4c60555a68352b553 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
for call. Add this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113948 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_instructions.s
|
| 250b948f21b2910c5bc61fb364c6817727a3a972 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
Disambiguate lcall/ljmp to the 32-bit version. This happens
even in 64-bit mode apparently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113945 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 6c1b3b1e32f960f44e47d8484510f5c5f8e5343f |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix the encoding of sldt GR16 to have the 0x66 prefix, and
add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113938 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| cfad564043021c7276ce19725f43bcde233fa549 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement aliases for shld/shrd, part of rdar://8418316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113937 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| e9e16a36d9ff355dab60e4b95673bf7a0cd27e86 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113936 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 84f362d8912657bb21250a65331f797d5381e9a3 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add various broken forms of fnstsw. I didn't add the %rax
version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113932 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 8f777a205e4523b773ba3af3bad007d93da56a9a |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add some aliases for f[u]comi, part of rdar://8431422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113930 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 2d592d10a57887ebe7c43a5e610f4278dd6c5d20 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add a bunch of aliases for fp operations with no operand,
rdar://8431422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113929 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 00002796bbb11f58435b9f43d63fd6d0657fc3a5 |
15-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
test: Fix coff-dump section array indicies to 1 based to match file format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113928 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.ll
OFF/symbol-fragment-offset.ll
|
| 05ae0c6026c15cc934ef2117a7a75ae57c55067d |
15-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Reapply r113875 with additional cleanups.
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| ef63c9a9b6f79fef91dc144db9d5f217d2b83a95 |
15-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add a terrible hack to allow out with dx is parens, a gas bug.
This fixes PR8114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113894 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 0989d29d093c281a0d8b4f1b1ea22436249c4087 |
11-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add a missed cmov alias, part of rdar://8416805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113693 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 697d37a43625b8862a6d6993c6c5ee614fdc0843 |
11-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add support for all the setCC aliases. Part of rdar://8416805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113692 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| b98ac2a71e55e685efa0fdbebdffb5228f7a512d |
11-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add support for leb128 of absolute expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113691 91177308-0d34-0410-b5e6-96231b3b80d8
LF/dg.exp
LF/sleb.s
LF/uleb.s
|
| dfa3c9d98260f899297c11cda2b15dc44fc4f91e |
11-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add support for pushfd/popfd which are aliases for pushfl/popfl.
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113690 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| ee211d0ed632d6329922ad4c5f7a25d3d66cf551 |
11-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement rdar://8407928 - support for in/out with a missing "a" register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113689 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 228290c0d181b663f33680aea03e10843da5f907 |
11-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change section_data dumping to print hex numbers instead of using
python's %r.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113685 91177308-0d34-0410-b5e6-96231b3b80d8
achO/absolutize.s
achO/darwin-x86_64-reloc-offsets.s
achO/darwin-x86_64-reloc.s
achO/direction_labels.s
achO/indirect-symbols.s
achO/jcc.s
achO/relax-jumps.s
achO/reloc-pcrel-offset.s
achO/reloc.s
achO/string-table.s
achO/tbss.s
achO/tdata.s
achO/thread_init_func.s
achO/tls.s
achO/tlv-reloc.s
achO/tlv.s
achO/x86_32-optimal_nop.s
achO/zerofill-5.s
|
| 1ab6f2fa7a38a12d8f20157d71e5280a253f2578 |
10-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Don't crash when using -n and we see a directive before the initial section.
- This is annoying, because we have to scatter this check everywhere that could emit real data, but I see no better solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113552 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/dash-n.s
|
| 93bd4d1e6b81b71ce56888e760ce0c9abe44023f |
10-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Make sure we exit != 0 if any errors are encountered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113551 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_abort.s
|
| a754be42da9449492a75d86dcb7a147ffd7b45d2 |
09-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add an elf-dumper utility.
- Output format and some of the code stolen from macho-dump.
- Somewhat incomplete and probably buggy.
- Comes with a very basic test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113488 91177308-0d34-0410-b5e6-96231b3b80d8
LF/basic-elf.ll
|
| 90b54547d9fcc381f8ec92c32756ad4da43ed9aa |
09-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113427 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 373c458850a963ab062046529337fe976e1f944d |
09-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix bugs in push/pop segment support, rdar://8407242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113422 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| c8ae35a8e8a6a39ae05b1c876afbf404e20961ff |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add support for the commuted form of the test instruction, rdar://8018260.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113352 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| ba8e81cca281a92fe30c25a10d8990521128be39 |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement proper support for sysret{,l,q}, rdar://8403907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113350 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| ba8cea450f330145cc7764e23e5d8b1aadd5e131 |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
implement the iret suite of instructions properly,
fixing rdar://8403974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113349 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| 2544f426927aa6dbac8d52bd9d5e12629099da82 |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add support for instruction prefixes on the same line as the instruction,
implementing rdar://8033482 and PR7254.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113348 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 9607c40601b345c21af9de97ec03e124179efd24 |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
Add this to the mc assembler, fixing PR8061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113346 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| a247685b3013b3dc675d4e83f9c98de6473af1d7 |
08-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix the encoding of the "jump on *cx" family of instructions,
rdar://8061602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113343 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
achO/jcc.s
|
| e9e0fc5eed9e177c3ee7299a34e640973102ac39 |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add missing cmov aliases, this resolves rdar://8208499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113189 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| c5cebeb3cb44a3fd0aaee956431159757ee47914 |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
"sldt <mem>" is ambiguous in 64-bit mode, but should
always be disambiguated as sldtw. sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact. Force it to sldtw, resolving rdar://8017530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113186 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| d68c474ec55a3dd43f9fa8ea4c89e5fae62909ab |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113184 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 9389b60a03890b70872e5ee2f078c4a4a00d123b |
07-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix the operand constraints of the immediate form of in/out,
allowing unsigned 8-bit operands. This fixes rdar://8208481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113182 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 1674b0b0e4972b844833f253286cbf99a6e99d6e |
02-Sep-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add AsmParser support for the ELF .previous directive. Patch by Roman Divacky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112849 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ELF/directive_previous.s
|
| 2ad12a0e2afa3cdffa35a4223bea775ad06ad468 |
01-Sep-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
COFF: Update tests to reflect changes in last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112704 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.ll
OFF/symbol-fragment-offset.ll
|
| a5729aae5d151f7b3a3805003ba076d7015cc9a7 |
28-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fixme accomplished
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112386 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_operands.s
|
| 3d6e4c31116c4f8fcc0737c5a626f81436c84532 |
25-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112089 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 82c84fdd23669d23c02a07498c83b83702979829 |
24-Aug-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Fix COFF x86-64 relocations. PR7960.
Multiple symbol reloc handling part of the patch by Cameron Esfahani.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111963 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.ll
OFF/switch-relocations.ll
OFF/symbol-fragment-offset.ll
|
| fba88d49e3fbb68bb84c295a9639fe94f9a8c6aa |
24-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
taking immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111950 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| ae528f65ba731e2e080822496ef36db950ffe1c1 |
24-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111947 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| e17edff28f684b5c59db395bdecb7b5330638398 |
24-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Change ParseExpression to use ParseIdentifier(), to support
dollars in identifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111946 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/dollars-in-identifiers.s
|
| ee9102587e7f6fc95de9fc5731b341eeb9bfc3ca |
24-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
for 'as' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111945 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 1f1b865c4062365712a1549191482bd6dd174f51 |
24-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Parser: Accept leading dollar signs in identifiers.
- Implemented by manually splicing the tokens. If this turns out to be
problematically platform specific, a more elegant solution would be to
implement some context dependent lexing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111934 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/dollars-in-identifiers.s
|
| a78c67e9bbf6ff0253945f3ba5bc178ece76d886 |
24-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://7997827 - Accept and ignore LL and ULL suffixes on integer literals.
Also fix 0b010 syntax to actually work while we're at it :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111876 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_values.s
|
| 59f8a6a66621f7c6f45b838e48fbf210af9d1fb5 |
19-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix PR7465, mishandling of lcall and ljmp: intersegment long
call and jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| c983b20661d574b7adb2675478210c03ad1d0a33 |
18-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ELF: Allow null values in virtual sections, ELF doesn't use special
directives for putting contents in .bss, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111376 91177308-0d34-0410-b5e6-96231b3b80d8
LF/bss.ll
LF/dg.exp
|
| f955f290c949ff0df7d23cec055efcc4ffeb35d1 |
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
isassembler/thumb-tests.txt
|
| 20d8e4e7aa5645450f3eaedd9f9dbb70423f8ccc |
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb2 t2RSBrr instruction for disassembly only.
This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/thumb-tests.txt
|
| 38aa2871fc7a37f7a6854744e71fc366ba12888a |
13-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the Thumb2 SSAT and USAT optional shift operator out of the
instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/thumb-tests.txt
|
| 1adc40cac314b0a77b790b094bca146a3a868452 |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 270159fcc21e06c67aa571d10d2b22d41d9a751a |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 09062b1672d33c40c38de3ff3163e0d53ebe165d |
12-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
because it could have an ambiguous suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instruction_errors.s
|
| 7def14f40f0b47551e2d66ec2f140a18b5bbbea4 |
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| eaf1c98a7c38444d41d1c6dc2074736eec7d452f |
12-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 345a9a6269318c96f333c0492b23733e29d952df |
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARM/arm_instructions.s
|
| e25c6b95cec7d8e774488c867998a94c3110250f |
10-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Fix a bug in macro argument parsing, which was dropping
parentheses from argument lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110692 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros.s
|
| a1d410d51265516584bf62c4e48874488dd2cba4 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM RSCrr instruction for disassembly only.
Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| cff71788446f17fa691a2768d8c11f46ae3206a2 |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add an ARM RSBrr instruction for disassembly only.
Partial fix for PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 079515f382fa7e95362ac1eeaadecbc7eb2f71db |
05-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
tests: Mark MC/AsmParser tests as requiring x86 for now -- almost all of them
rely on using a specific x86 triple to test what they want to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110337 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/dg.exp
|
| 1d9125a6ff192f1346d2b08bbf6ecc9c9e44103d |
05-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM "rrx" shift operands do not have an immediate. PR7790.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 237f8fe5df628065874b8590b364d04dfc2686fd |
03-Aug-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
MC: Fix symbol fragment offsets in COFF.
Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110104 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/symbol-fragment-offset.ll
|
| 98e1479575c87fcd16d2087c99b8e07e6722ac36 |
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add support for disassembling VMVN (immediate) instructions. PR7747.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| dfd30187c685c2c5200ee795c64885c0a39dc2d0 |
27-Jul-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Make MC use Windows COFF on Windows and add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109494 91177308-0d34-0410-b5e6-96231b3b80d8
OFF/basic-coff.ll
OFF/dg.exp
|
| 3c8e1bee6399e829eda801a32158c1f52d2733ad |
24-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-avx-encoding.s
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-avx-encoding.s
smParser/X86/x86_64-encoding.s
|
| 19d92fcae209cbd43d23a080a5166707600c0041 |
24-Jul-2010 |
Matt Fleming <matt@console-pimps.org> |
Consolidate the ELF section directive tests into a single file as
suggested by Chris Lattner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109290 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ELF/directive_section.s
smParser/ELF/directive_section_bss.s
smParser/ELF/directive_section_data_rel.s
smParser/ELF/directive_section_data_rel_ro.s
smParser/ELF/directive_section_eh_frame.s
smParser/ELF/directive_section_rodata.s
smParser/ELF/directive_section_tbss.s
smParser/ELF/directive_section_tdata.s
|
| 6d7019bcc43ab92ae87c8762b16264327e5c37a8 |
23-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Move AVX encoding tests to different files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109269 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-avx-encoding.s
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-avx-encoding.s
smParser/X86/x86_64-encoding.s
|
| f528d2b438b5c8fd3e2609be981e500576f5e5af |
23-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX version of CLMUL instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-avx-clmul-encoding.s
smParser/X86/x86_64-avx-clmul-encoding.s
|
| 6b7e9168a451a7c07ceda1c92470b3b691e35c20 |
23-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-fma3-encoding.s
smParser/X86/x86_64-fma3-encoding.s
|
| fb583a98427bb7191b27ad2ac5bf408201df07bb |
22-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109168 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-encoding.s
|
| 2b69143083a770fa883257340073ebb1f4787747 |
22-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add more 256-bit forms for a bunch of regular AVX instructions
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109063 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| e29f37f6a134502e39553c9f072eaad2568cbe18 |
21-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109039 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| cf6ca031288332c4fb43a314a3c30df8deeb2ffb |
21-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX only vzeroall and vzeroupper instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 7d7d15a159aaddeafe243a87ef3dbf9c9d220f49 |
21-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108984 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 4b13f3cf3d44219371ca8cdfe699ebdc5e12f7f8 |
21-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 1154f426d72ea7b2d9de93f9af5874d7d9b5a3d5 |
21-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add new AVX vextractf128 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108964 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| a7f9563c018d33eee1586da8aa26a1faa58a3cea |
20-Jul-2010 |
Matt Fleming <matt@console-pimps.org> |
Include some tests for the recently committed ELF section directive
handlers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108938 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ELF/dg.exp
smParser/ELF/directive_section_bss.s
smParser/ELF/directive_section_data_rel.s
smParser/ELF/directive_section_data_rel_ro.s
smParser/ELF/directive_section_eh_frame.s
smParser/ELF/directive_section_rodata.s
smParser/ELF/directive_section_tbss.s
smParser/ELF/directive_section_tdata.s
|
| e1c29be6f08d0e5657cfa3d430816147698c7479 |
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add new AVX instruction vinsertf128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 7a2b701ef6a294170fb92a535d52bc533778acff |
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
x86_32 tests for vbroadcast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108789 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 43945d99de0df592383e6e0a42694418c78dbdda |
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX vbroadcast new instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108788 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-encoding.s
|
| 94143ee6254944a26adba2200037328c2c8ef289 |
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 77e2dd7bb2bb5f28d389ba246d815cd9848ee53b |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| 926f2bb3d8dd6f8b0198aa478828ee02914050f9 |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
X86-64: Mark WINCALL and more tail call instructions as code gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108685 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 90b374cdedf0ff844b86b768b2d0832c64ab9173 |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
assembling; remove crufty custom cleanup code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108681 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 9ece46d172d89aa4ea6c04b8e55044bc9fdf9921 |
19-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
tests: Force another triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108666 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-def-in-instantiation.s
|
| 030794bd87d731d736da59681afdb7694131c9f2 |
18-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
tests: Force triples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108658 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros-parsing.s
smParser/macros.s
|
| 6a46d571b461246e36f82c146e17bf614d2114ea |
18-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token
sequences, not just strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108655 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_abort.s
|
| 7a570d09ac8630f782d394878baf6645cfd264e7 |
18-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Add macro argument substitution support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108654 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macro-def-in-instantiation.s
smParser/macros.s
|
| c64a0d7c3e55cf7d8bc8b49dcc447a3d809b11c8 |
18-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Add basic support for macro instantiation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108653 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros-parsing.s
|
| 6d8cf082f643a585b82e8dd136641ee4638b8c7a |
18-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Add basic parsing support for .macro definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108652 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros-parsing.s
|
| 3c802de01af19964c41cc17e9d788271d42dbcdb |
18-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't
support macros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108649 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/macros-parsing.s
|
| 879259faa3b24015949f3a3614ce348a7c20e422 |
17-Jul-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Test for ELF .size directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108607 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_elf_size.s
|
| 7dbf7d8b1cc60f869534b959025aa29b6e1018fb |
14-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX 256-bit compare instructions and a bunch of testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 87a85c7ef0d1a96c73473de90d3b2b28d24538a5 |
13-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
AVX 256-bit conversion instructions
Add the x86 VEX_L form to handle special cases where VEX_L must be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 37a746bc854d050ded5e280a13aad359852eb06a |
13-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
my work on adding segment registers to LEA missed the
disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| fd920fa59a7ac65fdd5f97da4e07e63b3922d30a |
13-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX 256-bit packed logical forms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 6991623dd7b8a096ccddbaedd9de3f515bacb1e2 |
13-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX 256-bit unop arithmetic instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| a0d09a85e27adb8545b37bfdaab9e2c6a01477fa |
13-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX 256 binary arithmetic instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| aa099be71f5e7b6a71930259edd3d25e60cb4fe2 |
12-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX 256-bit MOVMSK forms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| b6c3a607ac91dc4fdd0b195e9df2b04eaa53a1ef |
12-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108180 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_zerofill.s
smParser/exprs.s
|
| 492b7a21cb28adf8819ee369f42a8129de5227ae |
12-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Move .desc parsing to Darwin specific parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108179 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_desc.s
|
| 9ac66b008d74d0a981455a2220136c59cf363226 |
12-Jul-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108174 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_subsections_via_symbols.s
smParser/hello.s
|
| d52e78efac2da94f9967db343abd46a0fa9cb3b4 |
09-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX 256-bit packed MOVNT variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 2bfb8f6ef8ac6970acfd90f4b93f5e58b7d2e62c |
09-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX 256-bit unpack and interleave
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| e86b01c153ba52307ecb6e7513ec33f57caedfdd |
09-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 834df19452a551195ab012a8923b646b9a57a0d9 |
09-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Rework segment prefix emission code to handle segments
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-encoding.s
|
| 9fc05227a2596c545b845ed9a72673995e49d16b |
08-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-encoding.s
|
| cc69e13a36b2238d8e0a2fc01463d16943c08936 |
08-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add more assembly opcodes for SSE compare instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107823 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| ced9ec9baceb8fd89fc657cfeeb1697f27d2e6ec |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX AES instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 4f6bdf9042dee0d49b0537b73be93878d0b402b1 |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 09df2ae0d056f846850732b4ec1ab49dee9791cc |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 3c1482231290e4c180556e090475bd09e7a26480 |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.1 extractps and pinsr instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 4fd32db6a6a43296489ac65b3cc84660f0621694 |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.1 Extract Integer instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| ee94e8297e37775011b5ddebc55b729d694cfa84 |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 36869b69b0b42944e8e3add7db2299e19e94e53d |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 07de40629f73fb018a2a7f0a5bbd1ee4defe95fd |
07-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX vblendvpd, vblendvps and vpblendvb instructions
Update VEX encoding to support those new instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 68b559e5f34b787fac04eb617c451cc840a473b4 |
03-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.1 blend, mpsadbw and vdp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 4a544be3a8d27b0f4314e893397124c3c7ed1507 |
03-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| c607570563609b97f9bb0e3a367c9460c00976a7 |
03-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.1 Horizontal Minimum and Position instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 2c70d4ad35e6a7beddb0b65d9176ede77ea5683e |
03-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE4.1 round instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| f5cd8c51e3d09a2af32e03414e75d3b50f47d0aa |
03-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Add support for the rest of AVX SSE3 instructions
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| c6fcdeb8f94c0b1a4b203e341d978b36df58b1e3 |
01-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Move SSE3 Move patterns to a more appropriate section
Add AVX SSE3 packed horizontal and & sub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 7144821c61db5c12be2d24f2149ff63804f24d1a |
01-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE3 packed addsub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 79b634c244e178ff4ab38151c77d2307f4f6ffe1 |
01-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE3 replicate and convert instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 6596a6207627ed59f568883924a21e642934c083 |
01-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| e26f14d15024d27cc1416efb62432de54ee779d2 |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE2 mask creation and conditional store instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 1e4b723b20af962f1f235cc0c8929b36e8e6a9fb |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE2 packed integer extract/insert instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 876085dcfa0b16071b73d4b1bb2f531bf897417a |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE2 integer unpack instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| d252fec7ae69ec95e41589d8d5b4ea218f3e25ce |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE2 packed integer shuffle instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 6d5d2b5de2e48944a5fc28aff585333e6fa52f2a |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE2 pack with saturation integer instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| c0ea94a37c6ebf7a517fd7e78b1df6bcad2e2ac9 |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SSE2 integer packed compare instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 5a3a4767502341f304a8015580ab05ed74161ab0 |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Add AVX form of all SSE2 logical instructions
- Add VEX encoding bits to x86 MRM0r-MRM7r
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 6c9fa437167bf420e6cc4b0b577910d634b09ac5 |
30-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add *several* AVX integer packed binop instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 147b7cad2fefa3260e2da8f7cfe31ac07f352ceb |
29-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 721ef73d88414b7cfab1f1424db7101ff727ea81 |
29-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX non-temporal stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107178 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| ea86423cbd3cc71a2ee2d261c25ab6c0eea0c7e0 |
29-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add sqrt, rsqrt and rcp AVX instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107166 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 4548260ab57319273f24d25bf8d6a7eeda6fe0f6 |
29-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Described the missing AVX forms of SSE2 convert instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| bdffc16d65b92929c79f5651280ee3051a877289 |
26-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 161476ec343161c6c6ab16df775d853fcecd77c3 |
26-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r106896:
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 95325b08a33dbce40f4d1faa2dfada40cac6cec5 |
26-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
revert this now, it's using avx instead of sse :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 544a95d7161a0b333ec889d77941aff828e627ac |
26-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| a0ae87fd5d8dd7e1221114c80fdfd0bba6ddaf87 |
25-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add some AVX convert instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106815 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 788184365a4a949eb83b0036045e6793bc6c20f0 |
24-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106787 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 645b209c4af53c0d21292df3d506cf79d4e3ec11 |
24-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
Teach the x86 mc assembler that %dr6 = %db6, this implements
rdar://8013734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106725 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-operands.s
|
| 6539dc6e6cb247de6960b2b1b3b8b01badb90728 |
24-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| e93e300ad04ca93b1e3b07d0eaf632e361785954 |
23-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX MOVMSK{PS,PD}rr instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106683 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 428256b8186208e89995d447c5e4c9d8e5c099fa |
23-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106678 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 7dbfd07e321dfdc90501d71a144749c69263659f |
23-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX SHUF{PS,PD}{rr,rm} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 50b9efc2a852bab753948a35e6615ace3100c9da |
23-Jun-2010 |
Nico Weber <nicolasweber@gmx.de> |
Add support for the x86 instructions "pusha" and "popa".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 62a76c6401e050b741f9293d4476346f1d74230d |
23-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX compare packed instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106600 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 0caca3967b6547a9c97bd5e10ee3babb345a9979 |
23-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply support for AVX unpack and interleave instructions, with
testcases this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106593 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| c3d57b179c33ef010ebbff003ce8c5d908cf9c01 |
23-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add AVX MOV{SS,SD}{rr,rm} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106588 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 97994e02621dbb174463c348b7155978a1429b8b |
22-Jun-2010 |
Eric Christopher <echristo@apple.com> |
Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion
during test runs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106577 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| f4f4bad6965fc3b8df700ceb7fe4679bd386d9f9 |
19-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Refactor aliased packed logical instructions, also add
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| be4d595afd6e0d1a1c0a511dabf2c5a724bdf366 |
19-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 1cf44fc051e05c7cd96a4b071b654381338baae9 |
19-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://7873482 by teaching the instruction encoder to emit
segment prefixes. Daniel wrote most of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| d7f9cc4de72bbb4f6308d7d66386319feeb4d466 |
18-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| cf125d02a08b0bde90739425da7c4af9ea43b9d7 |
12-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105870 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 7be0d2c8e944d0f51db8abb0fb4c8fb7c1bfe8f8 |
12-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
Handle OpSize TSFlag for AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105869 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| c902a59f4c786a2a047f0b4c964a93108f248915 |
12-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 99405df044f2c584242e711cc9023ec90356da82 |
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 1087f54ddb70bd2a7ab62608161e4a3f0c345935 |
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 3eca98bb3ab1ec27ab8763298c416d282cdaa261 |
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
|
| 31cc9655b681c1b9b0a199131588377ce578ec0d |
28-May-2010 |
Kevin Enderby <enderby@apple.com> |
MC/X86: Add alias for movzx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105005 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 5e394429ab0a51af87056fbdaceeae879e651963 |
28-May-2010 |
Kevin Enderby <enderby@apple.com> |
MC/X86: Add alias for fwait.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105001 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 31b6c5b2f3118ba8ab9366ecf37085a26be6db97 |
28-May-2010 |
Kevin Enderby <enderby@apple.com> |
Fix the use of x86 control and debug registers so that the assertion failure in
getX86RegNum() does not happen. Patch by Shantonu Sen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104994 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| bd658918df63f43654ce3b1045c7b563df91a63f |
27-May-2010 |
Kevin Enderby <enderby@apple.com> |
MC/X86: Add aliases for Jcc variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
achO/jcc.s
|
| bd3ba537cdc257b7f2f7fb4ad2ea55ee1e4036f3 |
27-May-2010 |
Eric Christopher <echristo@apple.com> |
Add a quick test of relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104794 91177308-0d34-0410-b5e6-96231b3b80d8
achO/tlv-reloc.s
|
| b106543592abcaabdbe929dd05d914f613f00af2 |
26-May-2010 |
Kevin Enderby <enderby@apple.com> |
Fix the x86 move to/from segment register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 02b46bc9426925b90137d264216a54aa413335fd |
25-May-2010 |
Eric Christopher <echristo@apple.com> |
Add support for initialized global data for darwin tls. Update comments
and testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
achO/tls.s
|
| cf50a5390c09325a7fc41640449205eced4363f6 |
25-May-2010 |
Kevin Enderby <enderby@apple.com> |
Changed the encoding of X86 floating point stack operations where both operands
are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 39e2dd7bab1925e12d4a03ae7abca0eff87274d6 |
25-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 79373680ed7f2b92df4a5c45d0d9bbd47af77c58 |
25-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 04ac770be90f7e6c308fb0213caab2bed2c20e47 |
25-May-2010 |
Kevin Enderby <enderby@apple.com> |
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
for the 64-bit version of the Bit Test instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 7e2f5aaa6754542e869e4f506273e2df45dcda6a |
25-May-2010 |
Eric Christopher <echristo@apple.com> |
Make sure aeskeygenassist uses an unsigned immediate field.
Fixes rdar://8017638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| e350690e3b0b33255ad9b8f152da4dff43014f9b |
24-May-2010 |
Dan Gohman <gohman@apple.com> |
Fix an mmx movd encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-encoding.s
|
| ca956dc0f66a573735cdea16acab7159c0c254e5 |
24-May-2010 |
Kevin Enderby <enderby@apple.com> |
MC/X86: Add aliases for CMOVcc variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 62e4c671b6b0f13c04a20bb43c05bfe84984ef34 |
22-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-imm-widths.s
|
| 4c361972fd9110eff30145abdd17f195404a4e49 |
22-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add alias for setz, setnz, jz, jnz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 9d31d79493be05ab9cbf5b7fb16b52e79712eff3 |
22-May-2010 |
Kevin Enderby <enderby@apple.com> |
Added retl for 32-bit x86 and added retq for 64-bit x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| 4e7f8390c0aada41b820fe47f65b7bde570f53a7 |
20-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| e5e4ff974df52aa870085904b6670c4d22ada0ac |
20-May-2010 |
Dan Gohman <gohman@apple.com> |
Fix assembly parsing and encoding of the pushf and popf family of
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| 14aaeac5cf8dd96859c4e74423f17a3da1c094c4 |
20-May-2010 |
Dan Gohman <gohman@apple.com> |
Define the x86 pause instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-new-encoder.s
|
| ee5673b622de7684c20b265f15a7563c573f452a |
20-May-2010 |
Dan Gohman <gohman@apple.com> |
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| a7f1354eb5289b340220c9138befff89822119b2 |
20-May-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://7986634 - match instruction opcodes case insensitively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 591466baff32bd76aa3329e18092c0c09528f826 |
19-May-2010 |
Eric Christopher <echristo@apple.com> |
A more combo tls testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104163 91177308-0d34-0410-b5e6-96231b3b80d8
achO/tls.s
|
| aa6c72ec9579cf7a9e65cbc7a56c6a40e9c5ad47 |
19-May-2010 |
Eric Christopher <echristo@apple.com> |
Few more simple tls testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104148 91177308-0d34-0410-b5e6-96231b3b80d8
achO/tdata.s
achO/thread_init_func.s
achO/tlv.s
|
| b4e876e37e47d950034667c3bc420828d1c44457 |
18-May-2010 |
Eric Christopher <echristo@apple.com> |
Quick test to make sure we're emitting the tbss section correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104063 91177308-0d34-0410-b5e6-96231b3b80d8
achO/tbss.s
|
| d8ba292c9bc4e0927ea21304d735e27a43d296a6 |
18-May-2010 |
Kevin Enderby <enderby@apple.com> |
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104038 91177308-0d34-0410-b5e6-96231b3b80d8
achO/direction_labels.s
|
| 2ae4bfd76905fb6d5be2bf03eaca51da2f9a4d81 |
18-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104033 91177308-0d34-0410-b5e6-96231b3b80d8
achO/indirect-symbols.s
|
| ebe7fcd041e1e9c3a0c535b26d8cdb45805bbeb8 |
18-May-2010 |
Kevin Enderby <enderby@apple.com> |
Added support in MC for Directional Local Labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103989 91177308-0d34-0410-b5e6-96231b3b80d8
achO/direction_labels.s
|
| c6177a4531a5d7e2207a3184cc8a4f1792073a7d |
18-May-2010 |
Eric Christopher <echristo@apple.com> |
More data/parsing support for tls directives. Add a few more testcases
and cleanup comments as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103985 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_tbss.s
smParser/directive_tdata.s
smParser/directive_thread_init_func.s
smParser/directive_tlv.s
|
| 648ac5153e2317d8eb21c5b201f7c58e6a04e2d6 |
17-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103981 91177308-0d34-0410-b5e6-96231b3b80d8
achO/x86_32-optimal_nop.s
|
| db9014dd8b7b0b2581d10357b305f99f1b529316 |
17-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Reverse order of SymbolData scanning when emitting instructions.
- This fixes a string table mismatch with 'as' when two new symbols are defined
in a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103979 91177308-0d34-0410-b5e6-96231b3b80d8
achO/string-table.s
|
| b18d2dd115d8ff3fd75bbaa90849473266236dc3 |
17-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Fix some differences in symbol flag handling.
- Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't
actually succeeding.
- Clear the "lazy bound" bit when we mark something external. This corresponds
roughly to the lazy clearing of the bit that 'as' implements in
symbol_table_lookup.
- The exact meaning of these flags appears pretty loose, since 'as' isn't very
consistent. For now we just try to match 'as', we will clean this up one day
hopefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103964 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbol-flags.s
|
| 525a3a67c16c2d1d9ce9d75ed1b44296be6c2270 |
17-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Support reassignment of variables in one special case, when the
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103950 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/assignment.s
|
| d04d98d24fe5c82c7e69b711cd989ef96980fb8e |
17-May-2010 |
Eric Christopher <echristo@apple.com> |
Assume that we'll handle mangling the symbols earlier and just put the
symbol to the file as we have it. Simplifies out tbss handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103928 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_tbss.s
|
| c3ce05c594ded5c2ad20410719bd9e586aeff180 |
14-May-2010 |
Kevin Enderby <enderby@apple.com> |
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
argument, like "int $4", to not get an Assertion error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| f0f6cdb6b40bdf799a806efca05f44081bb154d3 |
14-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be
used to replace a normal relocation, not a reference to a GOT entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103789 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-reloc.s
|
| 482eba054ab3543ee0e1f453d3d6441092f4b76d |
14-May-2010 |
Eric Christopher <echristo@apple.com> |
Add AsmParser support for darwin tbss directive.
Nothing uses this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103757 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_tbss.s
|
| 2f93667f0bc08a9f092b941ba7d604367da3e377 |
13-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Add another zerofill test to improve coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103691 91177308-0d34-0410-b5e6-96231b3b80d8
achO/zerofill-5.s
|
| 7bb7c55a619c29f96518f4a0da57799cdef27167 |
13-May-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://7965971 and a fixme: use ParseIdentifier in
ParseDirectiveDarwinZerofill instead of hard coding the
check for identifier. This allows quoted symbol names to
be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103682 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_zerofill.s
|
| b5505d0ee34c22ca25189e035e29e07323311ec9 |
13-May-2010 |
Chris Lattner <sabre@nondot.org> |
reapply r103668 with a fix. Never make "minor syntax changes"
after testing before committing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103681 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| 3519f9d7d179ac1a77a4721b2e5f8123f95af418 |
13-May-2010 |
Chris Lattner <sabre@nondot.org> |
revert r103668 for now, it is apparently breaking things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103677 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| 0de8e3f10ac42abbd642fb2bdab5911374b14a75 |
13-May-2010 |
Chris Lattner <sabre@nondot.org> |
moffset forms of moves are x86-32 only, make the parser
lower them to the correct x86-64 instructions since we
don't have a clean way to handle this in td files yet.
rdar://7947184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103668 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| 2745f6e920dd8b562ded008e3e34acc873c5a36f |
13-May-2010 |
Chris Lattner <sabre@nondot.org> |
fix the encoding of the obscure "moffset" forms of moves, i386
part first. rdar://7947184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 0481449a0536311b5fefc9122ce679000540e013 |
12-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Extend suffix matching hack to match 'q' suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103535 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-suffix-matching.s
|
| a5f1d57f65ae601ec181c0f4e36cf0df5e8d79d8 |
12-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
be diced into atoms, and adjust getAtom() to take this into account.
- This fixes relocations to symbols in fixed size literal sections, for
example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103532 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-reloc.s
|
| db4c7e606f6bcc42ed8d853be5d67dfb9fa0edee |
12-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Fix PCrel adjustment for x86_64, which was using the fixup
offset instead of the fixup address as intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103527 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-reloc.s
|
| 651804c3d63a05f72221a6d133e5b344e6aaa093 |
11-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O x86_64: Switch to using fragment atom symbol.
- This eliminates getAtomForAddress() (which was a linear search) and
simplifies getAtom().
- This also fixes some correctness problems where local labels at the same
address as non-local labels could be assigned to the wrong atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103480 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-reloc.s
|
| a8251fac10e3ba7c4ad7035f1f039197ac3e09c7 |
11-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Fix another mismatch with .weak_definition, we shouldn't use a
scattered relocation entry with a .weak_definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103443 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc.s
|
| a6eeb6e226d7d86d04e34e3b6464f66e0a052f43 |
07-May-2010 |
Kevin Enderby <enderby@apple.com> |
Fix i386 relocations to Weak Definitions. The relocation entries should be
external and the item to be relocated should not have the address of the
symbol added in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103302 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc.s
|
| c26ae5ab7e2d65b67c97524e66f50ce86445dec7 |
07-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
- This fixes "leal 0, %eax", for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| e1611f26e332045272923d4e540b055c1c08be4d |
06-May-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://7947167 - llvm-mc doesn't match movsq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 1a8b789a4b8290d263c1c75411788ca45bae3230 |
06-May-2010 |
Sean Callanan <scallanan@apple.com> |
Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| 5fe03c023cd47a718759a3a4dc1d8e33297ae0fc |
06-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
Revert r103137, fix for $ in labels. It looks like we can't actually handle this
at the token level. Consider the following horrible test case:
a = 1
.globl $a
movl ($a), %eax
movl $a, %eax
movl $$a, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103178 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_operands.s
smParser/labels.s
|
| 851f87c6c98af936ba68c5ca8962df3832f8a5fc |
06-May-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://7946934 - in some limited cases, the assembler should
allow $ at the start of a symbol name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103137 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_operands.s
smParser/labels.s
|
| 2d7fd61e94e2db0586ad9d5d26c1e7c5510a006d |
05-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Mark absolute variable's appropriately, and add Mach-O support for
writing them.
- <rdar://problem/7885351> integrated assembler broken for i386 objc code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103112 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc.s
|
| ae7fb0b03ebc524e6c47f0262b8dc87810fee1a8 |
05-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Relocations in debug sections should use local relocations
when possible.
- <rdar://problem/7934873>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103092 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-reloc.s
|
| e9f0fb4179d57c631a72fa8020ca05a4d132e15b |
04-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103015 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-suffix-matching.s
|
| c918d6043b823173b106c163038b14c1e2f92765 |
04-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103012 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-suffix-matching.s
|
| 9d0838fba8bb79bd4f43244e91f199dd8f4ea1b6 |
03-May-2010 |
Kevin Enderby <enderby@apple.com> |
Changed llvm-mc to use the same suffixes with floating point compare
instructions as the Mac OS X darwin assembler. Some of which like 'fcoml'
assembled to different opcodes. While some of the suffixes were just different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102958 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| eb612347f4ec1c6a44daa6abf232e25232984ef8 |
03-May-2010 |
Kevin Enderby <enderby@apple.com> |
Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 3c979b06c041544b97b13c5adac1a91d6cde6582 |
03-May-2010 |
Kevin Enderby <enderby@apple.com> |
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value. Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte. Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102951 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 9ac7282117d57932933b539fc8b7b17b6693cf9f |
29-Apr-2010 |
Kevin Enderby <enderby@apple.com> |
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
Operand size override prefix to be part of their records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102556 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 52d2b0ed00d71c8ba0ff1a0b35cad4ffebc81dd5 |
21-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Thumb instructions which have reglist operands at the end and predicate operands
before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/thumb-tests.txt
|
| 56a1afb6b06b63efb85efcfd12f07aa80ca6ab3b |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/thumb-tests.txt
|
| ef37e3abb7fdcdb773163e4e48743b2f7b2141b3 |
20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/thumb-tests.txt
|
| 22e401f5d4d863e753bc8e5655bac481602d22e6 |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/thumb-tests.txt
|
| 4b7df442a8a3cc5eacd2a7bb93ef09b3d3bbe63b |
19-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
ARM disassembler did not react to recent changes to the NEON instruction table.
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| eef6d78be1c3a685f277be3e89ff17f67ed65f49 |
17-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
teach the x86 asm parser how to handle segment prefixes
in memory operands. rdar://7874844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_operands.s
|
| 0fb372a497705e65908ef4b733b9679e8ca07a99 |
17-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
testcase for r101538, patch by Nico Schmidt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101642 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| 65de1b9eb373e196681bfc32f49c40f0d0561522 |
17-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
a bunch of ssse3 instructions are misencoded to think they have an
i8 field when they really do not. This fixes rdar://7840289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| f7e2bc80d1c645c347532f0847b77ed72b348e5a |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Minor change to make the test case comply with Vd<0> == '0' when Q == '1'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101559 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| c7b65914e080b5236078e5f58ded5503226bcb71 |
17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.
Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/neon-tests.txt
|
| 16fda6982b8fa366db2632d3b1775d71f1fd4eaa |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 2fb10f17d8e4fc2142e97f4efe653a75177d2363 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| cd52932dce81d9578039565dd836a340b7bb2c63 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added another test case for am3offset operand, testing Rn, #+/-imm8.
Previous checkin tested Rn, #+/-Rm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101418 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 1cfa094562457aa0c36818b93b481e4ff454ec92 |
16-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
am2offset. Modified the instruction table entry and added a new test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 4c7276a4eb64199e1804818a7650e4a3c5c662dc |
15-Apr-2010 |
Daniel Dunbar <daniel@zuster.org> |
tests: MC/Disassembler tests depend on ARM support being compiler in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101337 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/dg.exp
|
| d305035155ef3d138e102434bf5a733ea2e32405 |
14-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
implement mc asmparser support for '.', which gets the
current PC. rdar://7834775
We now produce an identical .o file compared to the cctools
assembler for something like this:
_f0:
L0:
jmp L1
.long . - L0
L1:
jmp A
.long . - L1
.zerofill __DATA,_bss,A,0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101227 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| bb6e9d8cf7c5a51b2f66568accc489927f0d538e |
12-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).
[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done
(gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------
mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.
Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0 0x00007fff88c65886 in __kill ()
#1 0x00007fff88d05eae in abort ()
#2 0x00007fff88cf2ef0 in __assert_rtn ()
#3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running. Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101053 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
|
| 447b19543bb227423524e65636a4b0ccd2b81797 |
07-Apr-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
unXFAIL, arm disassembler was reenabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100692 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
isassembler/neon-tests.txt
isassembler/thumb-tests.txt
|
| 1b0194d646d67c341a162c580196bb25aee2e12a |
05-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
isassembler/neon-tests.txt
isassembler/thumb-tests.txt
|
| b68a3ee82a8a34f7bae1d68d76f574e76a5535ef |
03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/arm-tests.txt
isassembler/neon-tests.txt
isassembler/thumb-tests.txt
|
| 1de558b71f710a00e391fb9a88a6481b8918e207 |
30-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Support @GOTPCREL on symbols, even for non-PCrel relocations!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99853 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-reloc.s
|
| 86afec7730e719600952bc9019f25e85289032a9 |
25-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Reapply Kevin's change 94440, now that Chris has fixed the limitation on
opcode values fitting in one byte (svn r99494).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-encoding.s
|
| e9cfd685f5916a45e7cd36e51191cec16b02189d |
25-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC: Fix refacto in MCExpr evaluation, I mistakenly replaced a fragment address with a symbol address.
- This fixes the integrated-as nightly test regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99466 91177308-0d34-0410-b5e6-96231b3b80d8
achO/absolutize.s
|
| 014dc4e7202f88fdd9c255837bf125f891f2f6b6 |
25-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Speculatively revert this to see if it fixes buildbot failures.
--- Reverse-merging r99440 into '.':
U test/MC/AsmParser/X86/x86_32-bit_cat.s
U test/MC/AsmParser/X86/x86_32-encoding.s
U include/llvm/IntrinsicsX86.td
U include/llvm/CodeGen/SelectionDAGNodes.h
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-encoding.s
|
| 760c2f34d94d01ddce47634e69bd77a3625899bf |
24-Mar-2010 |
Kevin Enderby <enderby@apple.com> |
Added the Advanced Encryption Standard (AES) Instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99440 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-encoding.s
|
| 044be39090a702504c62fc0544fc977a6caa7112 |
24-Mar-2010 |
Kevin Enderby <enderby@apple.com> |
Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does
not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 78fcf53a187584dec0b8eb25a34c826c918600ce |
20-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Remove Darwin host specific tests, we don't need them anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99100 91177308-0d34-0410-b5e6-96231b3b80d8
achO/Darwin/dg.exp
achO/Darwin/optimal_nop.s
achO/Darwin/x86_32_diff_as.s
|
| 57a49a202f8613d99dcb2f75f2b5a9505898f1a1 |
20-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Tweak optimal_nop test to be host independent.
- This also avoids us running valgrind on /usr/bin/as, which has leaks. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99099 91177308-0d34-0410-b5e6-96231b3b80d8
achO/Darwin/optimal_nop.s
achO/x86_32-optimal_nop.s
|
| b46b03b36f50c11d5517024c1d0ef3763085eb90 |
19-Mar-2010 |
Kevin Enderby <enderby@apple.com> |
Fixed the encoding problems of the crc32 instructions. All had the Operand size
override prefix and only the r/m16 forms should have had that. Also for variant
one, the AT&T syntax, added suffixes to all forms. Also added the missing
64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-encoding.s
smParser/X86/x86_64-encoding.s
achO/Darwin/x86_32_diff_as.s
|
| 602b40f0d06d6275cbe73de2ac3b6b6a7dc1d46d |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Add relocation support.
- This is "extraordinarily" Darwin 'as' compatible. See the litany of FIXMEs littered about for more information.
- There are a few cases which seem to clearly be 'as' bugs which I have left unsupported, and there is one cases where we diverge but should fix if it blocks diffing .o files (Darwin 'as' ends up widening a jump unnecessarily).
- 403.gcc build, runs, and diffs equivalently to the 'as' built version now (using llvm-mc). However, it builds so slowly that I wouldn't recommend trying it quite yet. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98974 91177308-0d34-0410-b5e6-96231b3b80d8
achO/darwin-x86_64-diff-relocs.s
achO/darwin-x86_64-reloc-offsets.s
achO/darwin-x86_64-reloc.s
|
| 0180daee024b97c87c34ac8c2a7b88c9e643c9aa |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 939f8d7ca23b95acdd5d1e71a7579ee8d33e7fd6 |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Factor out isScatteredFixupFullyResolvedSimple predicate, and fix some corner cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98924 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc.s
|
| c28c7689fc555b8507d2b0b128f4e6b05dcf2027 |
19-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
X86: Fix encoding for TEST64rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98919 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 9fdac902d4300f2b0b8f4830ff276cc8199864b5 |
18-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we
were missing it on some movq instructions and were not including the appropriate
PCrel bias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98880 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| f98bc6320b61645897606ef332cff60521c1e8f3 |
18-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a
temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98858 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-incl_decl.s
|
| 618d0ed4bc0b68d87f86eace0cd6b9c05329dfc7 |
18-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix an x86-64 encoding bug Daniel found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98855 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 0f53cf22361d89690dcf58409decb43d2a3ad60f |
18-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
add a special relocation type for movq loads for object
files that produce special relocation types where the
linker changes movq's into lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98839 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| d6e59084d07500f68548652b8197325809a0c0c2 |
15-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O/x86_64: Temporary labels in cstring sections require symbols (and external relocations, but we don't have x86_64 relocations yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98583 91177308-0d34-0410-b5e6-96231b3b80d8
achO/x86_32-symbols.s
achO/x86_64-symbols.s
|
| 3b39f890069a37e67081b17f1e9c99a8654d11cf |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
xfail properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98479 91177308-0d34-0410-b5e6-96231b3b80d8
achO/Darwin/x86_32_diff_as.s
|
| 9e2dab7dbe518bbeb7e93d0f3459e3f1c5f61964 |
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
xfail these tests temporarily to get teh buildbots back to happy land.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98476 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit.s
smParser/X86/x86_32-bit_cat.s
smParser/X86/x86_32-encoding.s
achO/Darwin/x86_32_diff_as.s
|
| 859c9dc867960c88db326d8ee16870a518457ec0 |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
X86: Fix ADD64i32 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98457 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| 5691e74f97fc8cad671d50450ad986347875e1d1 |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86_64: Symbol support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98456 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbols-1.s
|
| ee0d89245eabf93d89b5fef7ac8707680796826d |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Initial x86_64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98454 91177308-0d34-0410-b5e6-96231b3b80d8
achO/sections.s
achO/x86_32-sections.s
achO/x86_64-sections.s
|
| 96e2cec9c743d1242be0e987f6873f74a15d2f80 |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86_64: Fix matching of leaq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98444 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-operands.s
|
| 989ac729811802a4b2a23dd2afd825df1b07f849 |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86_64: Fix matching of callq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98443 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-operands.s
|
| da3e9f760ce2328f6dfe69663c2b17da02ece2db |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: PCrel relocations weren't using the right base address, they are
relative to the fragment address, not its offset. This was masked by the text
section normally being at address 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98420 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc-pcrel-offset.s
|
| d5e7705a05947e60806b795880f09757e835f590 |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testing
other functionality on 403.gcc compiled at -O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98405 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 69c695ee472853fa1ee93a94f00ef2a14bf18a66 |
13-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add an XFAIL test where we aren't matching the correct instruction
because we don't understand how the specific instruction is doing sign
extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98404 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-mismatched-add.s
|
| f08fde41f34d739c157b1d75dadbb864e7957cab |
12-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Implement initial support for relaxation.
- The implementation is currently very brain dead and inefficient, but I have a
clear plan on how to fix it.
- The good news is, it works and correctly assembles 403.gcc (when built with
Clang, at '-Os', '-Os -g', and '-O3'). Even better, at '-Os' and '-Os -g',
the resulting binary is exactly equivalent to that when built with the system
assembler. So it probably works! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98396 91177308-0d34-0410-b5e6-96231b3b80d8
achO/relax-jumps.s
achO/relax-recompute-align.s
|
| 979ba5b3c7c818b826d06298ee7f79c4234faedb |
11-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Implement "absolutizing" semantics of .set, by evaluating the assembly time value of variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98241 91177308-0d34-0410-b5e6-96231b3b80d8
achO/absolutize.s
|
| a015c1c876bb74a83cbbae06449056e0c6f0e9c9 |
10-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Use the SECTDIFF relocation type for (A - B + constant) where A is external.
- I'm not sure why, but this is what 'as' does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98115 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc-diff.s
|
| f291be3159530fdca2fd5e726ec2bd3100f38e55 |
09-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98098 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 1e8ee89c213704c398d8a7ea2567a30b0f75eb5f |
09-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98097 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| f3a066f7c3ef4e729c92929acab352a93f8d7563 |
09-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: For PCrel relocations, we need to compensate for the PCrel adjustment when determining if we need a scattered relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98082 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc-pcrel.s
|
| 0e822407b283d4334bb4506255e52bc2887786b1 |
08-Mar-2010 |
Kevin Enderby <enderby@apple.com> |
Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes
for the encoding and is not the same as vmptrld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97992 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| b2b4acd757194b4b75e571ec7225811f94e753f3 |
08-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Macho-O: Align the zerofill section itself to the maximum alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97991 91177308-0d34-0410-b5e6-96231b3b80d8
achO/zerofill-4.s
achO/zerofill-sect-align.s
|
| 37fad5ce4d81fd459fafe1517d6cd17e7ab49958 |
08-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Fix address compution for zero fill sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97984 91177308-0d34-0410-b5e6-96231b3b80d8
achO/zerofill-4.s
|
| b93c72cda456c96224d25e1df11112bd9b69cf69 |
08-Mar-2010 |
Daniel Dunbar <daniel@zuster.org> |
X86: Fix encoding for TEST{8,16,32}rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97982 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| d74acb0c78c3b738ae8f313461433105fb18543b |
25-Feb-2010 |
Kevin Enderby <enderby@apple.com> |
This is a patch to the assembler frontend to detect when aligning a text
section with TextAlignFillValue and calls EmitCodeAlignment() instead of
calling EmitValueToAlignment(). This allows x86 assembly code to be aligned
with optimal nops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97158 91177308-0d34-0410-b5e6-96231b3b80d8
achO/Darwin/optimal_nop.s
|
| a08b587494a09a94a72245dd9d7088564e511f4e |
16-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
make pcrel immediate values relative to the start of the field,
not the end of the field, fixing rdar://7651978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96330 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| b779033a23c49c2e5e02b15a87bbae42973287b3 |
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add encoder support and tests for rdtscp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96076 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
isassembler/simple-tests.txt
|
| e9a60eb4987a096df10de0442af1e2929bc32547 |
13-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96064 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_operands.s
smParser/conditional_asm.s
|
| f068304b1f9205b49aa4bef75e669f750906b84f |
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
rip out the 'heinous' x86 MCCodeEmitter implementation.
We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96059 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
smParser/X86/x86_64-new-encoder.s
|
| a599de241041eebc84867ac8e4cb76668cabd236 |
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
fix swapgs to be spelled right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
isassembler/simple-tests.txt
|
| 9c60f534cbdec2ba58b269c4d624ae4d301ef73a |
13-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Push immediate operands as immediates not expressions when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
smParser/X86/x86_instructions.s
smParser/X86/x86_operands.s
|
| ca3eeb33a8d7816721bb8b94456677ddead06b4d |
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add some disassemble testcases for weird instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96045 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| 4a2e5edb94c5d6ceb2f8f99ec031963e4c3862f9 |
13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
implement the rest of correct x86-64 encoder support for
rip-relative addresses, and add a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96040 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_64-new-encoder.s
|
| c4d3f662fc2e907ea2c76aca8ec1971e43f89c98 |
12-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
fix the encodings of monitor and mwait, which were completely
busted in both encoders. I'm not bothering to fix it in the
old one at this point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-new-encoder.s
|
| 1c5bcac7d55efa4df0b6d67bb9cf4fa362244812 |
11-Feb-2010 |
Kevin Enderby <enderby@apple.com> |
Remove the few # TAILCALL comments that snuck in. As they may fail on linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95827 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
|
| ac175e251dbd6f55448677a7dae70f92c49a0286 |
11-Feb-2010 |
Kevin Enderby <enderby@apple.com> |
Update the X86 assembler matcher test case now that a few more things match
with some of the recent changes that have gone into llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95826 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
|
| 1b6c0605915a2f626b1d3aae6f8371924e0fffe7 |
10-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86 AsmMatcher: Fix a use after free spotted by d0k, and de-XFAIL
x86_32-encoding.s in on expectation of it passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95806 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| ac6dd79a5548c2e0a409cccd34ad056dd521a80f |
10-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
XFAIL this on linux until I figure out what is happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95804 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| d901690b822fd40adc5eb34f777ee15d689b8d50 |
10-Feb-2010 |
Kevin Enderby <enderby@apple.com> |
Replace this file containing 4 tests of x86 32-bit encodings with a file
containing the subset of the full auto generated test case that currently
encodes correctly. Again it is useful as we bring up the the new encoder
to make sure currently working stuff stays working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95791 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 40fe18f66e7c94bda22bb3ad5fbef336fffd0f9d |
10-Feb-2010 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the movntdqa X86 instruction. It was missing the 0x66
prefix which is part of the opcode encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95729 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 9e8528fc5cd7426884c1708d921d4608ac3878b7 |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
fix X86 encoder to output [disp] only addresses with no SIB byte
in X86-32 mode. This is still required in x86-64 mode to avoid
forming [disp+rip] encoding. Rewrite the SIB byte decision logic
to be actually understandable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95693 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| e16b0fc3cb607bd0b8240733e2fe829d78df3833 |
09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Implement x86 asm parsing support for %st and %st(4)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95634 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 8f60e4d679003235d6e4ac2f5f03eb757a84dde8 |
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
fix incorrect encoding of SBB8mi that Kevin noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95448 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| 3f1118310eddbbc0d5972e8564c7ac9b91464a33 |
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
fix a case where we'd mis-encode fisttp because of an incorrect (and
redundant with a correct one) pattern that was added for the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95446 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-encoding.s
|
| c8296a0d597a27e7070787d12c8fbe16830b1734 |
05-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove fixme
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95444 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 12ce0de4622df7bcc15ba6c8818b98c0b936876a |
03-Feb-2010 |
Kevin Enderby <enderby@apple.com> |
Added support for X86 instruction prefixes so llvm-mc can assemble them. The
Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| e7070e90066acc3460af1d6cac4036a80b0250b8 |
03-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
AsmParser/X86: Add temporary hack to allow parsing "sal". Eventually we need
some mechanism for specifying alternative syntaxes, but I'm not sure what form
that should take yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95158 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 41051552312c67d53f5571bf9451093e57d1b95a |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove the # TAILCALL markers, which was causing the to fail.
It's unclear if the matcher is nondeterminstic of what here,
but I'm getting matches without TAILCALL and some other hosts
are getting matches with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95149 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
|
| 197f1f024677641dc86760c56d5fcaff7e1b52ee |
02-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
MCAssembler/Darwin: Add a test (on Darwin) that we assemble a bunch of
instructions exactly like 'as', and produce equivalent .o files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95143 91177308-0d34-0410-b5e6-96231b3b80d8
achO/Darwin/dg.exp
achO/Darwin/x86_32_diff_as.s
|
| e1ec617c6abf0b9dc1eecbbfe483bda3bb2b7795 |
02-Feb-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/Mach-O: Set SOME_INSTRUCTIONS bit for sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95135 91177308-0d34-0410-b5e6-96231b3b80d8
achO/section-flags.s
|
| 1de46a4ab526243aa950e3f06ab40745d275527d |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
this apparently depends on the host somehow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95122 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
|
| d56f80358b113e918dc43d5b7659f4dd545872de |
02-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
disable this test for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95120 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
|
| 82a594693976edefa37160567e7f7495c2653c99 |
02-Feb-2010 |
Kevin Enderby <enderby@apple.com> |
Added another version of the X86 assembler matcher test case.
This test case is different subset of the full auto generated test case, and a
larger subset that is in x86_32-bit.s (that set will encode correctly). These
instructions can pass though llvm-mc as it were a logical cat(1) and then
reassemble to the same instruction. It is useful as we bring up the parser and
matcher so we don't break things that currently work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95107 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_32-bit_cat.s
|
| b834f5d13d824dc4da2ce0df2aa8dffb697b8974 |
30-Jan-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing
something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
movl $0, %eax
as
movl 0, %eax
Feel free to guess how well that worked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94869 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
smParser/labels.s
|
| 50459580e79348003fec7849b8e147e449c472b8 |
30-Jan-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/X86: Add a nice X86 assembler matcher test case from Kevin Enderby.
- This test case is auto generated, and has been verified to round-trip
correctly through llvm-mc by checking the assembled .o file before and after
piping through llvm-mc. It will be extended over time as the matcher grows
support for more instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94857 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/dg.exp
smParser/X86/x86_32-bit.s
|
| d32e80307395581eac25b4b081dc4e42860b62b9 |
25-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
wirte up .file and .file to the mc asmparser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94438 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_file.s
|
| 75f265fbbbb64ab060bf41c5a4677ce56014ce9f |
24-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
fix a parsing problem on instructions like:
movw $8, (_cost_table_-L97$pb)+66(%eax)
After the parens, we could still have a binop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94345 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 12e555c36ce11c39ce15cd0b27bf7b02a068beb2 |
23-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
teach MCAsmStreamer::EmitBytes to use .ascii and .asciz
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94259 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_ascii.s
|
| 8a3ee718cdaa153e29c079548e6755184d5426e4 |
22-Jan-2010 |
Daniel Dunbar <daniel@zuster.org> |
Mark EH_RETURN64 as CodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94205 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/X86/x86_instructions.s
|
| 6113b3d32396168f8f390343d426baa9f64e9009 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
add an MCAsmStreamer::EmitFill specialization of EmitFill that
emits one directive instead of N. Not doing this would be a
significant regression on the # bytes generated by .fill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93889 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_space.s
|
| f4d9a555ba99a9def419c57fd96d253961c05c84 |
19-Jan-2010 |
Chris Lattner <sabre@nondot.org> |
only darwin has zerofill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93866 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_lcomm.s
|
| 516088d4ae496e479ec5e3092436ea98a6d25e17 |
22-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
specify a triple to use, fixing the test on non-x86-64 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91900 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| 665e947740bb1909f9c3dc60927e8b9620d644e5 |
22-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
various cleanups, make the disassemble reject lines with too much
data on them, for example:
addb %al, (%rax)
simple-tests.txt:11:5: error: excess data detected in input
0 0 0 0 0
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91896 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/simple-tests.txt
|
| 2adbef06a637b367f724d0a46f7fa78d5827ec64 |
22-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
rewrite the file parser for the disassembler, implementing support for
comments. Also, check in a simple testcase for the disassembler,
including a test for r91864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91894 91177308-0d34-0410-b5e6-96231b3b80d8
isassembler/dg.exp
isassembler/simple-tests.txt
|
| db196e82a40020706a221c48cd99026b85fb27ab |
16-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
Force triple in tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84257 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/variables-invalid.s
smParser/variables.s
|
| 75773ff00da79ecf65e8578cf6f013295a2069cf |
16-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
MC: Tweak variable assignment diagnostics, and make reassignment of non-absolute
variables and symbols invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84232 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/variables-invalid.s
|
| fffff915d53361fc575621c5e04ae7df99dd3fab |
16-Oct-2009 |
Daniel Dunbar <daniel@zuster.org> |
MC: When parsing a variable reference, substitute absolute variables immediately
since they are allowed to be redefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84230 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
smParser/variables.s
|
| 5440f6309d6b714475a631b12307432c719cd066 |
07-Oct-2009 |
Kevin Enderby <enderby@apple.com> |
Fixed MCSectionMachO::ParseSectionSpecifier to allow an attribute of "none" so
that a symbol stub section with no attributes can be parsed as in:
.section __TEXT,__picsymbolstub4,symbol_stubs,none,16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83488 91177308-0d34-0410-b5e6-96231b3b80d8
achO/sections.s
|
| 06e483dae04b0ad714f9d8bb0a929b98720bf483 |
21-Sep-2009 |
Daniel Dunbar <daniel@zuster.org> |
Move ARM and X86 specific AsmParser tests into separate subdirectories, and only
run if appropriate target is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82419 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/ARM/arm_word_directive.s
smParser/ARM/dg.exp
smParser/X86/dg.exp
smParser/X86/x86_instructions.s
smParser/X86/x86_operands.s
smParser/X86/x86_word_directive.s
smParser/arm_word_directive.s
smParser/dg.exp
smParser/x86_instructions.s
smParser/x86_operands.s
smParser/x86_word_directive.s
|
| e895c6151589c1b7f6ac9ca992b76106fa197a37 |
20-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Add an intel syntax MCInstPrinter implementation. You can now
transcode from AT&T to intel syntax with "llvm-mc foo.s -output-asm-variant=1"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82385 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/hello.s
|
| ca9c42c4daa8f4ffd9411e11c05fb53ee1bfaf70 |
15-Sep-2009 |
Kevin Enderby <enderby@apple.com> |
Added the first bits of the ARM target assembler to llvm-mc. For now it only
parses the .word directive as 4 bytes and ARMAsmParser::ParseInstruction will
give an error is called. Broke out the test of the .word directive into two
different test cases, one for x86 and one for arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81817 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/arm_word_directive.s
smParser/directive_values.s
smParser/x86_word_directive.s
|
| b92c36331dd9c1102b99dc795f14513503ec3e29 |
14-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
unbreak this test by working around an asmparser bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81724 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/hello.s
|
| cd60c1fb742813df2aa9d85ed6bf219b44bb4b29 |
08-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Unbreak these tests. Chris, please verify that these changes are intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81217 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/conditional_asm.s
smParser/labels.s
smParser/x86_operands.s
|
| 0892a6d7a95fab61ff4e5640e601b363700d952f |
03-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
use a darwin triple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80900 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| 17b9abb799037d28382e5be16af1cd2be8d80a5f |
03-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
adjust expected lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80898 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| 2f0adae973010f659909b77041b6cd674953d9b1 |
03-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
update test for alignment value in hex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80876 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_align.s
|
| 821e3334ed3390d931f497300e6a5f1dc21bcfb3 |
31-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Pass values to MCStreamer as MCExprs, not MCValues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80578 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/conditional_asm.s
smParser/exprs-invalid.s
smParser/labels.s
|
| e2ace509fc1205bed97a5114b13534610d4dbf5e |
31-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Simplify EmitAssignment ('.set' is identical to '=').
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80577 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_include.s
smParser/directive_set.s
smParser/labels.s
|
| 8c2eebe4074ef218b30d94358f6b2e45c079605c |
31-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Switch MCInst to storing an MCExpr* instead of an MCValue.
Also, use MCInst::print instead of custom code in MCAsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80575 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
smParser/x86_operands.s
|
| 3a3cb6c59edb35184aad06c6d6f32ac2572b3866 |
30-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Update test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80490 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| 7092c7e1dcf9d05741b400dd54bbd7d3419773b2 |
30-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: MCStreamer cleanups. - Remove EmitLocalSymbol, this is unsupported for now.
- Switch Emit{CommonSymbol,Zerofill} to take alignment in bytes (for consistency).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80484 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_lsym.s
|
| 8f4d146c340c9423271ebd7bb3fd32b880000bc9 |
28-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Support .comm emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80351 91177308-0d34-0410-b5e6-96231b3b80d8
achO/comm-1.s
|
| d5a8e98ef627a35284c9b5989664514f8f163968 |
28-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Support .zerofill emission.
- I'm still trying to figure out the cleanest way to implement this and match the assembler, currently there are some substantial differences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80347 91177308-0d34-0410-b5e6-96231b3b80d8
achO/lcomm-attributes.s
achO/zerofill-1.s
achO/zerofill-2.s
achO/zerofill-3.s
|
| e6cdbf2f92a753ad547e3287e279bf47585b228d |
28-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Emit .lcomm as .zerofill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80343 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_lcomm.s
smParser/labels.s
|
| b1126e6f4a41ba8bcee155803a6572cf2e493924 |
27-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
For now, only run MC tests if X86 is configured.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80213 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/dg.exp
achO/dg.exp
|
| 7c0a3348fb5c8259a2b4e21b8c80b5459eaa9487 |
27-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Unique sections properly, so we don't get duplicate text
sections, etc.
- The quick and dirty way, just clone the TargetLoweringObjectFile
code. Eventually this should be shared... somehow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80168 91177308-0d34-0410-b5e6-96231b3b80d8
achO/sections.s
|
| 959fd883346384e742fff049327a6815e36017e0 |
27-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Don't put assembler temporary labels in the symbol table.
- I moved section creation back into AsmParser. I think policy decisions like
this should be pushed higher, not lower, when possible (in addition the
assembler has flags which change this behavior, for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80162 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbols-1.s
|
| 6009db486e7fba448ccb28dff676c012efade8f0 |
26-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Set .subsections_via_symbols flag properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80144 91177308-0d34-0410-b5e6-96231b3b80d8
achO/sections.s
|
| 3f6a960f9c9ad27f2ac573020df414e8b8cdda04 |
26-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Add support for relocations.
- I haven't really tried to find the "right" way to store the fixups or apply
them, yet. This works, but isn't particularly elegant or fast.
- Still no evaluation support, so we don't actually ever not turn a fixup into
a relocation entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80089 91177308-0d34-0410-b5e6-96231b3b80d8
achO/reloc.s
|
| 573e53627e3e44cce60e8c0443a34cd43c41e316 |
26-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Fix tests for python variations in int printing, sigh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80069 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbol-indirect.s
|
| 6742e34385bff89b897ef0fc930c4bca9e75ac4a |
26-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Add section padding where needed (to align the next section).
Also, simplify some of Mach-O writer code which can now use section addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80067 91177308-0d34-0410-b5e6-96231b3b80d8
achO/section-align-1.s
achO/section-align-2.s
|
| 5e835967dd5dda294d0ef3392f4c1d4a2260f532 |
26-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Set addresses for symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80065 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbol-indirect.s
achO/values.s
|
| ad7c3d55932f949e6bd428232999088a53f54a4f |
26-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Improve indirect symbol support (add the indirect index table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80059 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbol-indirect.s
|
| 6aff2fbd56d4bc2d6029f7c9bd49a97f6dc01213 |
24-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Support symbol attributes.
- This is mostly complete, the main thing missing is .indirect_symbol support
(which would be straight-forward, except that the way it is implemented in
'as' makes getting an exact .o match interesting).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79899 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbol-flags.s
|
| 3edd9bb7a3da8526eb2f4a5dae2962a987d3d566 |
22-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Improve symbol table support:
- Honor .globl.
- Set symbol type and section correctly ('nm' now works), and order symbols
appropriately.
- Take care to the string table so that the .o matches 'as' exactly (for ease
of testing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79740 91177308-0d34-0410-b5e6-96231b3b80d8
achO/symbols-1.s
|
| 605187e5968b500d6ea1d6a7e318ee608f08b774 |
22-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Force triple for these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79737 91177308-0d34-0410-b5e6-96231b3b80d8
achO/data.s
achO/sections.s
|
| 2330df6b66e6ca7cfad54be9088f0d931cc66441 |
22-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Improve handling of implicit alignment for magic section directives
(e.g., .objc_message_refs).
- Just emit a .align when we see the directive; this isn't exactly what 'as'
does but in practice it should be ok, at least for now. See FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79697 91177308-0d34-0410-b5e6-96231b3b80d8
achO/sections.s
|
| d6f761e0eb610936a6b8495360b62696dcd85164 |
22-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Support .o emission for .org and .align.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79684 91177308-0d34-0410-b5e6-96231b3b80d8
achO/data.s
|
| 0705fbf52fcaade0c6b9d5d33bec163ee4c2daf4 |
21-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/Mach-O: Support byte and fill value emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79652 91177308-0d34-0410-b5e6-96231b3b80d8
achO/data.s
|
| bc38ca7321b4ca32580e397a9b7df970688560c0 |
21-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Accept .fill size of 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79635 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_fill.s
|
| fb4a6b397665df011348ade24a8e38d2219f095a |
21-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Start MCAssembler and MCMachOStreamer.
- Together these form the (Mach-O) back end of the assembler.
- MCAssembler is the actual assembler backend, which is designed to have a
reasonable API. This will eventually grow to support multiple object file
implementations, but for now its Mach-O/i386 only.
- MCMachOStreamer adapts the MCStreamer "actions" API to the MCAssembler API,
e.g. converting the various directives into fragments, managing state like
the current section, and so on.
- llvm-mc will use the new backend via '-filetype=obj', which may eventually
be, but is not yet, since I hear that people like assemblers which actually
assemble.
- The only thing that works at the moment is changing sections. For the time
being I have a Python Mach-O dumping tool in test/scripts so this stuff can
be easily tested, eventually I expect to replace this with a real LLVM tool.
- More doxyments to come.
I assume that since this stuff doesn't touch any of the things which are part of
2.6 that it is ok to put this in not so long before the freeze, but if someone
objects let me know, I can pull it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79612 91177308-0d34-0410-b5e6-96231b3b80d8
achO/dg.exp
achO/sections.s
|
| c21d5883acb7635635bb449dd8e439fa15a91bf6 |
19-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79445 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_align.s
|
| 6e579c67272afdbca273ad6e6e93c5f6c0f10eeb |
19-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
fix asmstreaming of 2/4 byte elements with pow-2 alignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79408 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_align.s
|
| e44313e0ca7ca3504dd9dc906e2eff8b36bc4ee4 |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Fix bugs where bytes were unintentionally being printed as signed.
- We now print all of 403.gcc cleanly (llvm-mc -> 'as' as diffed to 'as'), minus two
'rep;movsl' instructions (which I missed before).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79031 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_ascii.s
|
| b2d0b6b8c70dadd4c7628d814c5caf7088defad3 |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: When handling a .set, make sure to print subsequent references to the
symbol as the symbol name itself, not the expression it was defined to. These
have different semantics due to the quirky .set behavior (which absolutizes an
expression that would otherwise be treated as a relocation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79025 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| 12de0df59fdab799d8d1432fcfd9190829d7f292 |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: zerofill shouldn't print quotes around the section,segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79017 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_zerofill.s
|
| 1ab75949460b92df31b911ea9f99a3e32d779e3f |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Support escaped characters in string literals (for .ascii and .asciz)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79010 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_ascii.s
|
| c22e0b2443afdedb6d9b225b938ad404d63cdbe6 |
14-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target
specific printer (this only works on x86, for now).
- This makes it possible to do some correctness checking of the parsing and
matching, since we can compare the results of 'as' on the original input, to
those of 'as' on the output from llvm-mc.
- In theory, we could now have an easy ATT -> Intel syntax converter. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
smParser/x86_instructions.s
smParser/x86_operands.s
|
| 1095f2ae261d231a63d329b0ebbf6eaf566ff429 |
12-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Match hard coded registers (e.g. 'shldl %cl, %eax, %eax')
We now match all of 403.gcc (as emitted by clang). :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78750 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| b27a41b44092c0a6e439203586cc944187de3388 |
11-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Fix a crash on invalid due to a typo in relocatable expression
evaluation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78692 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs-invalid.s
|
| 0db68f4e3a8be1641dbba72a41baa6ff1b5dd6af |
11-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/X86: Parse '*' correctly (in the way the matcher expects).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78642 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| 1e840b2c6150838815c1041562f9876560b0b465 |
11-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Accept .word as a synonym for .short
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78641 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_values.s
|
| d0c14d69134473f38b84205e9d556234b2d0c0ad |
11-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Sketch parsing for .file, .line, and .loc. No streamer hooks for these
yet (I'm not even sure what they do).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78639 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_file.s
smParser/directive_line.s
smParser/directive_loc.s
|
| ace63127bc7501d4d7707f744cdae09894342aa9 |
11-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Fix darwin .section parsing. It was skipping the section name and a ','
(and outputting a diagnostic pointing at the wrong place), all of which lead to
much confusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78637 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_darwin_section.s
|
| ea6408f8cd17b065e414611e01a7133d118429e9 |
11-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands.
- This drops us to 123 ambiguous instructions (previously ~500) on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| 44f63f9335bfb487a2e94cbe20d2950bbdef840e |
10-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Disambiguate i64i8imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78598 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| fdb1f493ab6bcfb5603b9f497195492d92aceacb |
10-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Check for matches with super classes when matching
instruction operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78565 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/hello.s
|
| a62b02a7ef93d1fd4e09842c43074b88f559819a |
09-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Disable this test for now, we don't check for super classes when matching yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78531 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/hello.s
|
| 5fe6338ac859707f797bf6db6d043bb5f4d944a1 |
09-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmParser: Implement user defined super classes.
- We can now discriminate SUB32ri8 from SUB32ri, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| 93b6db3de934a3cfca5586df25184fef4a54c500 |
09-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
sink the 'name' and 'isdirective' state out of MCSection into its derived classes.
This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78517 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| a3741fa28b1a397ebfd623ef9d14e978df94ce47 |
08-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmMatcher: Improve match code.
- This doesn't actually improve the algorithm (its still linear), but the
generated (match) code is now fairly compact and table driven. Still need a
generic string matcher.
- The table still needs to be compressed, this is quite simple to do and should
shrink it to under 16k.
- This also simplifies and restructures the code to make the match classes more
explicit, in anticipation of resolving ambiguities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78461 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
smParser/x86_instructions.s
|
| c114ed711eca29e735e10956883a1010c22d7942 |
08-Aug-2009 |
Kevin Enderby <enderby@apple.com> |
Added Mac OS X assembler style conditional assembly. I may come back and see if
I can clean this up a bit more and do way with the TheCondState and just use
the top element on the TheCondStack if not empty. Also may tweak the code
around ParseConditionalAssemblyDirectives() to simplify the AsmParser code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78423 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/conditional_asm.s
|
| 7ddca30f311423933ab27bd48727a7226ac3e159 |
07-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Disable X86 AsmMatcher for now, it is causing gcc-4.0 to run out of memory on
i386-apple-darwin9. This presumably will get fixed once the generated code
improves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78379 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
smParser/x86_instructions.s
|
| 20927f26fcd7d0394bc60c58c61d879a83adac0d |
07-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/AsmMatcher: Move to a slightly more sane matching design.
- Still not very sane, but a least its not 60k lines on X86. :)
- In terms of correctness, currently some things are hard wired for X86, and we
still don't properly resolve ambiguities (this is ignoring the instructions
we don't even match due to funny .td stuff or other corner cases).
The high level changes:
1. Represent tokens which are significant for matching explicitly as separate
operands. This uniformly handles not only the instruction mnemonic, but
also 'signficiant' syntax like the '*' in "call * ...".
2. Separate the matching of operands to an instruction from the construction of
the MCInst. In theory this can be done during matching, but since the number
of variations is small I think it makes sense to decompose the problems.
3. Improved a few of the mechanisms to at least successfully flatten / tokenize
the assembly strings for PowerPC and ARM.
4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
moving towards for handling ambiguous instructions. The high-bit is to infer
a partial ordering of the operand classes (and force the user to specify one
if we can't) and use that to resolve ambiguities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78378 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| a6b3c5db2e0736937e717a1c221e51aa60700271 |
01-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: More quoted identifier support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77761 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| 35ee93b7919a97b3cd8ba3cd41e5fb46bfdcc6ea |
01-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Add -triple, and fix some typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77750 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/hello.s
smParser/labels.s
|
| ad4555c549ed41aefb306cf9bd0c2e9f60cb3047 |
01-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Fix .s output to quote section & symbol names when necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77749 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_zerofill.s
smParser/labels.s
|
| c09e411102878c7f01ef707c2ac52eb3c76ab77b |
01-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: A few more parsing / match tweaks.
- Operands which are just a label should be parsed as immediates, not memory
operands (from the assembler perspective).
- Match a few more flavors of immediates.
- Distinguish match functions for memory operands which don't take a segment
register.
- We match the .s for "hello world" now!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77745 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/hello.s
|
| 76c4d7696c1eb566d53467a76024c5fdadd448e4 |
31-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Support quoted identifiers.
- Uses MCAsmToken::getIdentifier which returns the (sub)string representing the
meaningfull contents a string or identifier token.
- Directives aren't done yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77739 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/labels.s
|
| 022e2a84a867ba73fd0e6b89f61e56396f22620d |
31-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/X86: Sketch match functions for immediates and memory operands.
Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| b6804e91267381427866dfc1ae3d88abd02ddf14 |
31-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add this test back, the check pattern was too strict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77662 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| 527695dd66971086f1a67ad30762c47fc7bce5d1 |
31-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove this test while I figure out why it is failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77659 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
|
| a027d222e18ea9028e9e12ae2f5cd566889b599a |
31-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Match a few X86 instructions.
- This is "experimental" code, I am feeling my way around and working out the
best way to do things (and learning tblgen in the process). Comments welcome,
but keep in mind this stuff will change radically.
- This is enough to match "subb" and friends, but not much else. The next step is to
automatically generate the matchers for individual operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77657 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_instructions.s
smParser/x86_operands.s
|
| f9507ffa5b1c8697009e86bbedaacb51e4c6735d |
28-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Implement .abort fully in the front end
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77272 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_abort.s
|
| 5026ae4514caf5bb88d6c09fbf56a9db2753ed43 |
20-Jul-2009 |
Kevin Enderby <enderby@apple.com> |
Removed the DumpSymbolsandMacros and LoadSymbolsandMacros MCStreamer API as
the parsing of the .dump and .load should be done in the assembly parser and
not have any need for an MCStreamer API. Changed the code for now so these
just produce an error saying these specific directives are not yet implemented
since they are likely no longer used and may never need to be implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76462 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_dump_and_load.s
|
| b4b53e5c13167925d6315a6f57c7b863e4e2b704 |
18-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Add -triple, and start fetching the target asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76257 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/assignment.s
smParser/directive_abort.s
smParser/directive_align.s
smParser/directive_ascii.s
smParser/directive_comm.s
smParser/directive_desc.s
smParser/directive_dump_and_load.s
smParser/directive_fill.s
smParser/directive_include.s
smParser/directive_lcomm.s
smParser/directive_lsym.s
smParser/directive_org.s
smParser/directive_set.s
smParser/directive_space.s
smParser/directive_subsections_via_symbols.s
smParser/directive_symbol_attrs.s
smParser/directive_values.s
smParser/directive_zerofill.s
smParser/exprs.s
smParser/x86_operands.s
|
| 8e25e2d801bb1119cea080c7c860adcfbf85d65d |
16-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
implement .include in the lexer/parser instead of passing it into the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75896 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_include.s
|
| 6e68cd96b2c76c80bfff07e8121ba19691ec1276 |
15-Jul-2009 |
Kevin Enderby <enderby@apple.com> |
Added llvm-mc support for parsing the .dump and .load directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75786 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_dump_and_load.s
|
| 1f049b24c7e520ecfd2291b7d30eb5abc3aee852 |
15-Jul-2009 |
Kevin Enderby <enderby@apple.com> |
Added llvm-mc support for parsing the .include directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75711 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_include.s
|
| 711482476c55f99c34c516f9e035b7c59b00ef42 |
14-Jul-2009 |
Kevin Enderby <enderby@apple.com> |
Added llvm-mc support for parsing the .lsym directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75685 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_lsym.s
|
| 95cf30c444707634bbd950f13405b6c8bcfe496b |
14-Jul-2009 |
Kevin Enderby <enderby@apple.com> |
Added llvm-mc support for parsing the .desc directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75645 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_desc.s
|
| 5f1f0b8f7e7087d456ddc3efdb4bed21a4ae359c |
14-Jul-2009 |
Kevin Enderby <enderby@apple.com> |
Added llvm-mc support for parsing the .abort directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75545 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_abort.s
|
| a5c783280f83df5c60a8ed9e32c61b05a11048e3 |
13-Jul-2009 |
Kevin Enderby <enderby@apple.com> |
add llvm-mc support for parsing the .subsections_via_symbols directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75500 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_subsections_via_symbols.s
|
| 9be3fee2bdc3126fb87e4e1b31935905f4bcc4d0 |
11-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add support for .zerofill, patch by Kevin Enderby!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75301 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_zerofill.s
|
| 1fc3d7558139eb6081a7ee5a8f88506d44c8dd7f |
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add llvm-mc support for parsing the .lcomm directive, patch by Kevin Enderby!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75148 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_lcomm.s
|
| 096e7280c2abceb4dcc119677c31a2055bc8ccde |
08-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Switch all the MC tests to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75039 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/assignment.s
smParser/directive_align.s
smParser/directive_comm.s
smParser/directive_fill.s
smParser/directive_org.s
smParser/directive_set.s
smParser/directive_space.s
smParser/directive_symbol_attrs.s
smParser/directive_values.s
|
| 648f9970aeab8ba8ec2e149a4ed67145a80785ac |
08-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
convert to FileCheck style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75038 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_ascii.s
|
| 4e4db7adfc9858a8f77f841c7467bc6fcbb8110e |
07-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Implement parsing support for the .comm directive. Patch by
Kevin Enderby!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74944 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_comm.s
|
| 0a93771e4c7283bf7999c00b3282eab0431b463f |
02-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc/x86: Test case for x86 operand parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74688 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/x86_operands.s
|
| 374d8bddacbffce7c82ce81103d30b5ee42032df |
01-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Symbols in a relocatable expression of the (a - b + cst) form are
allowed to be undefined when the expression is seen, we cannot enforce the
same-section requirement until the entire assembly file has been seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74565 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| f4b830f03f4859d89b03cb56fb3e43ba08ba94c3 |
30-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Accept relocatable expressions for .org, assignments, .byte, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74498 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| d7b267bd908ee1a1792a6a917c036e764fc3ace0 |
30-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Parse symbol attribute directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74487 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_symbol_attrs.s
|
| c29dfa786a23c9ff0827ce4a56b5b178e4087aaa |
30-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Parse .{,b,p2}align{,w,l} directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74478 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_align.s
|
| 1ad7edc2125d57dcd6c54810d7a4a5f4f77da34b |
30-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
llvm-mc: Recognize C++ style comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74463 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| 475839e9a97a0c0282e107d14fd1dc6e5f223435 |
29-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
MC: Improve expression parsing and implement evaluation of absolute expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74448 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/exprs.s
|
| c238b584de26d7ee717dbd951a7656033fb6bc05 |
26-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
MC: Parse .org directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74218 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/directive_org.s
|
| 8f780cd7896407f743de7538166ff9d40d752086 |
25-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
MC: Parse .set and assignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74208 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/assignment.s
smParser/directive_set.s
|
| a0d1426af0bd05e1ae69481cdb75d2913e7e1ac1 |
25-Jun-2009 |
Daniel Dunbar <daniel@zuster.org> |
Basic .s parsing for .asci[iz], .fill, .space, {.byte, .short, ... }
- Includes some DG tests in test/MC/AsmParser, which are rather primitive since
we don't have a -verify mode yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74139 91177308-0d34-0410-b5e6-96231b3b80d8
smParser/dg.exp
smParser/directive_ascii.s
smParser/directive_fill.s
smParser/directive_space.s
smParser/directive_values.s
|