| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/test/MC/ARM/arm-thumb-cpus-default.s
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| 6c921a55f4d5fc51a127fcc673ac1c9b46273899 |
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11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-thumb-cpus-default.s
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| c139672407b6ad8d2929fd0c52591216fd32b4b6 |
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11-Jun-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
- For now, The tests are marked as XFAIL for win32 hosts.
FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-thumb-cpus-default.s
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| 9bdd78501484a1add2d8a757fd29960dd9fc9de7 |
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11-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.
rdar://14024354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/arm-thumb-cpus-default.s
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