| 589ddc9887406ddfd5a2661b567057faad7a22cc |
|
05-May-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add LDAPB instructions.
With the change the disassembler now supports the XCore ISA in its
entirety.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| c601bd69d5c7fcd3bf9946e8a8a1bd1f9ab6642b |
|
05-May-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add BLRB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| ef1762b6a1d3353790bdb415788e7d8963e70372 |
|
14-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| e50faa754b946d5240c1d4e84e64b7e84d4e27b1 |
|
04-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add bru instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| c6ff29713d69b4a41c225cbde9c82e4a350dbfac |
|
04-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] The RRegs register class is a superset of GRRegs.
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 6107bbbbdf1c801b80f28a4d20e2194087f13c62 |
|
03-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Check disassembly of the st8 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| ef6343347a9269f17c1c723d6afaa28a5e5a5714 |
|
03-Apr-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Update disassembler test to improve coverage of the instructions.
Previously some instructions were unintentionally covered twice and
others were not covered at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 8dc741e400213ea8183e09626f0d1f45f14e044f |
|
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 763c858edeb76173ee4ef5ab9bf7d750db5d8c4f |
|
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| a970dde9060d8994c242bd186bb3636d2caf22d2 |
|
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing u10 / lu10 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| cbe6c88b6811e4641629d111f941879982362fe8 |
|
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing u6 / lu6 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 970a479c02a418726950580e13136acd2a2dc13f |
|
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| b719d8b1007f6b31ae6d1a66258a26e6a91749bc |
|
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing l2r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 9d2b1aef1b5bc8926c66b38f03583a77d015e921 |
|
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 1r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| f5e7e793f196cfba4427321ee9f38ecc8bb8470f |
|
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 0r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| c47bd9899b639c3384268f871009259c2a94fba4 |
|
25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l4r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 3b6a5eefe0ab2199bc69094b390b736ae332b905 |
|
25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l5r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b |
|
23-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l6r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 0ec35ac4fcd5c83e2ec35d04fc20db9eb387d289 |
|
22-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for u10 / lu10 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 8da543434664986ac19f4753a691fb613ba80778 |
|
21-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for u6 / lu6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 9b709f8b3f3fa6e9bfb5007b70e096f6192f3ef8 |
|
21-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encoding / disassembly support for ru6 / lru6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| b853c415c663c752c669cb191cea95542c1d21f6 |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| c78ec6b6bc05572aed6af1eee4349d76a68ded18 |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l3r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| a68c64fbb2f1bee7f9313f3ee19c35677563f974 |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembler support for 2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 62b8786d12ceacafd665d4a1fbb6e90af0ec368c |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| c47793c62c434bd27fee1d243c2081a34d4f3817 |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| a839ffc323396326ebdcf8d065c60be0bf05420d |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings for PEEK and ENDIN.
Previously these were marked with the wrong format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 35150cbf4166ae8d69032d355f1e8d83b4a6eb3c |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| ff6114e872742e966c57202add83b84611e63e97 |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings for ZEXT and SEXT.
Previously these were marked with the wrong format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170327 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| 1ffe48a84b398e8cebbdc7a47bedb57e1e67e63f |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for 2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| dd78daa199f653b64b997fdee46db8964e5c50cc |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for 0r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|
| e4e0089e45350f99c80ece1781671028368708c1 |
|
16-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add tests for disassembly of 1r XCore instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Disassembler/XCore/xcore.txt
|