| 4433b0302d0aa9dc61002e8bb4fd1b752b0be338 |
|
20-Apr-2012 |
Brian Paul <brianp@vmware.com> |
intel: use _mesa_is_winsys/user_fbo() helpers
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 43af02ac731dac7d80f7e47feb0c80e4da156769 |
|
27-Feb-2012 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: handle gl_PointCoord for Gen4 and Gen5 platforms
This patch add the support of gl_PointCoord gl builtin variable for
platform gen4 and gen5(ILK).
Unlike gen6+, we don't have a hardware support of gl_PointCoord, means
hardware will not calculate the interpolation coefficient for you.
Instead, you should handle it yourself in sf shader stage.
But badly, gl_PointCoord is a FS instead of VS builtin variable, thus
it's not included in c.vue_map generated in VS stage. Thus the current
code doesn't aware of this attribute. And to handle it correctly, we
need add it to c.vue_map manually to let SF shader generate the needed
interpolation coefficient for FS shader. SF stage has it's own copy of
vue_map, thus I think it's safe to do it manually.
Since handling gl_PointCoord for gen4 and gen5 platforms is somehow a
little special, I added a lot of comments and hope I didn't overdo it ;)
v2: add a /* _NEW_BUFFERS */ comment to note the state flag dependency
and also add the _NEW_BUFFERS dirty mask (Eric).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45975
Piglit: glsl-fs-pointcoord and fbo-gl_pointcoord
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| f0cecd43d6b6d3f5def3fd43b9c95baaf3be9b16 |
|
13-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Move VUE map computation to once at VS compile time.
With this and the previous patch, 640x480 nexuiz is running 0.169118%
+/- 0.0863696% faster (n=121). On a VS state change microbenchmark,
performance is increased 8.28645% +/- 0.460478% (n=52).
v2: Fix CACHE_NEW_VS comment.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 9f3d3216cf25d8ffed4d72fbce6feacbc2990e4b |
|
13-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make the userclip flag for the VUE map come from VS prog data.
This reduces recomputation of state based on non-clipping-related
transform changes, and is a step toward removing VUE map
recomputation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| dc9a753f6687133d2d057597e5af86abcdc56781 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move program compile to emit() time.
Only 4 other prepare() functions are left, which don't rely on this.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 18e2e19b07b312c978dfbb6d336f69fa84b3ffe2 |
|
27-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Make brw_compute_vue_map's userclip dependency a boolean.
Previously, brw_compute_vue_map required an argument indicating the
number of clip planes in use, but all it did with it was check if it
was nonzero.
This patch changes brw_compute_vue_map to take a boolean instead.
This allows us to avoid some unnecessary recompilation of the Gen4/5
GS and SF threads.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| c163072197b56e76b656cc472bbe6df650cf11ba |
|
28-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
mesa: Create _mesa_bitcount_64() to replace i965's brw_count_bits()
The i965 driver already had a function to count bits in a 64-bit uint
(brw_count_bits()), but it was buggy (it only counted the bottom 32
bits) and it was clumsy (it had a strange and broken fallback for
non-GCC-like compilers, which fortunately was never used). Since Mesa
already has a _mesa_bitcount() function, it seems better to just
create a _mesa_bitcount_64() function rather than special-case this in
the i965 driver.
This patch creates the new _mesa_bitcount_64() function and rewrites
all of the old brw_count_bits() calls to refer to it.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| becd54eedb26ec9076e6f5f98f485861b3e13a90 |
|
03-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Remove two_side_color from brw_compute_vue_map().
Since we now lay out the VUE the same way regardless of whether
two-sided color is enabled, brw_compute_vue_map() no longer needs to
know whether two-sided color is enabled. This allows the two-sided
color flag to be removed from the clip, GS, and VS keys, so that fewer
GPU programs need to be recompiled when turning two-sided color on and
off.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| bbc53d6285efc664b9b9f326cdcd82a9414507c1 |
|
25-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: SF: Remove unnecessary variables.
This patch removes the variables nr_attrs and nr_setup_attrs, whose
purpose is now being served by the VUE map. nr_attr_regs and
nr_setup_regs are still needed, however they are now computed using
the VUE map rather than by counting the number of vertex shader
outputs (which caused subtle bugs when gl_PointSize was written).
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 08f030baec3d13805c5800183550d8ad88ed8881 |
|
25-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: SF: Remove attr_to_idx and idx_to_attr.
These data structures were serving the same purpose as the VUE map,
but were buggy. Now that the code has been transitioned to use the
VUE map, they are not needed.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 4a1fb81902a7863d5dfe304e5e4ca2c631159be1 |
|
24-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: SF: Modify calculate_point_sprite_mask to use the VUE map.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| f147599ef4b0d14c25a7e0d3f9f1c9b0229bb6fc |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.
From the GL 2.1 spec:
"Required perspective-correct interpolation for all fragment
attributes except depth in sections 3.4.1 and 3.5.1, effectively
making GL PERSPECTIVE CORRECT HINT a no-op."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 774fb90db3e83d5e7326b7a72e05ce805c306b24 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Get a ralloc context into brw_compile.
This would be so much easier if we were using C++; we could simply use
constructors and destructors. Instead, we have to update all the
callers.
While we're at it, ralloc various brw_wm_compile fields rather than
explicitly calloc/free'ing them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 3032582d032a28381dd4c2f4093d82c79e73129e |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead entrypoints to state cache, rename the one that's left.
As we expanded the usage of the state cache, it grew extra
functionality. However, with the recent state streaming rework, we're
back to the state cache being used only for shader kernels, which is
the piece of GPU state that's actually expensive to compute again from
scratch, since it involves compiling.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 64f5e9059b975e34885e63bc404b30b1b2c28de8 |
|
18-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix point coordinate replacement after airlied's ffvertex changes.
This basically restores the previous state, where a vertex result slot
is set up for the texcoord to be replaced with point coord. Fixes
piglit point-sprite test.
Bug #27625
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| b8b2670fef4790d650939fece8c7e6c7b76c3171 |
|
18-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add SF program disasm under INTEL_DEBUG=sf.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| bc632d04370566c1156cbd0345fe303834f0b910 |
|
08-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up the handling of point sprite coordinate replacement.
The code was walking over the regs of pairs of attributes and checking
whether the attribute with a given reg index had point sprite enabled.
So the point sprite setup code was rarely even getting executed.
Instead, we need to determine which channels of a reg need point
sprite coordinate replacement. In addition, it was multiplying the
attribute by 1/w, when it's supposed to cover (0, 1) in each direction
regardless of w, and it wasn't filling in the Z and W components of
the texcoord as specified.
Fixes piglit point-sprite and the spriteblast demo. Bug #24431, #22245.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 5606dfb572bf4b89b4882265924705bacc8c182b |
|
18-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'outputswritten64'
Add a GLbitfield64 type and several macros to operate on 64-bit
fields. The OutputsWritten field of gl_program is changed to use that
type. This results in a fair amount of fallout in drivers that use
programs.
No changes are strictly necessary at this point as all bits used are
below the 32-bit boundary. Fairly soon several bits will be added for
clip distances written by a vertex shader. This will cause several
bits used for varyings to be pushed above the 32-bit boundary. This
will affect any drivers that support GLSL.
At this point, only the i965 driver has been modified to support this
eventuality.
I did this as a "squash" merge. There were several places through the
outputswritten64 branch where things were broken. I foresee this
causing difficulties later for bisecting. The history is still
available in the branch.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 26d22b094bb7b2f37d4bc8edfeb1b2a9a1c96d88 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: make brw_sf_prog_key::sprite_origin_lower_left one bit
Shrinks size of key to 8 bytes from 12.
Note that progs/demos/spriteblast.c is still broken.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 18af7c384cf663533f210d95d074c244d4214f29 |
|
13-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: interpolate colors with perspective correction by default
...rather than with linear interpolation. Modern hardware should use
perspective-corrected interpolation for colors (as for texcoords).
glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get
linear interpolation if mode = GL_FASTEST.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 6dceeb2eb804d708639d68a13a924d65f366458a |
|
11-Mar-2009 |
Robert Ellison <papillo@vmware.com> |
i965: fix polygon face orientation when rendering to FBO
In the i965, the FBO coordinate system is inverted from the standard
OpenGL/Mesa coordinate system; that means that the viewport and the
polygon face orientation have to be inverted if rendering to a FBO.
The viewport was already being handled correctly; but polygon face
was not. This caused a conform failure when rendering to texture with
two-sided lighting enabled.
This fixes the problem in the i965 driver, and adds to the comment about
the gl_framebuffer "Name" field so that this isn't a surprise to other
driver writers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| d911e3e24fbfb5cd28cabb92f952775b7eb1d1d9 |
|
13-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix indentation
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 4813946d366a0d61e0be1dacec6d3077bc939b48 |
|
14-Feb-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: use setup attributes as inputs when allocating registers
for WM payload. fix #10767
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 4cca760a9b7fe120ed92257a6a6c4a3a6e929ba8 |
|
19-Dec-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: allocate GRF registers before building subroutines,
it ensures there are sufficient registers for all subroutines.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 125bd4cae51c6deaacd2e90f14931c2052f146ab |
|
06-Dec-2007 |
Eric Anholt <eric@anholt.net> |
Revert "[965] Add missing flagging of new stage programs for updating stage state."
I had forgotten part of brw_state_cache.c that made this fix not relevant for
master (last_addr comparison and flagging based on cache id).
This reverts commit a4642f3d18bdaebaba31e5dee72fe5de9d890ffb.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| a4642f3d18bdaebaba31e5dee72fe5de9d890ffb |
|
06-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Add missing flagging of new stage programs for updating stage state.
Otherwise, choosing a new program wouldn't necessarily update the state, and
and an old program could be executed, leading to various sorts of pretty
pictures or hangs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| ae078e1a0abae58e325ed3ebcb1884867847826b |
|
12-Sep-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: revert commit 1a15b2169ba6cb100627eb525a20a00537cfb6f0,
and keep the instruction state unchanged after calling
brw_emit_tri_setup/brw_emit_line_setup when building setup
thread for SF_UNFILLED_TRIS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 1a15b2169ba6cb100627eb525a20a00537cfb6f0 |
|
05-Sep-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: only take non-varying attribute into account when
compiling sf_prog. fix bug#11378 (which is introduced by
commit d619cceea47dc3070ebb7f7ea4f8b6b31a672d38)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
|
| 60179434d15989b81e2d4757f34033009184a678 |
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30-Jul-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
ARB sprite point support on i965
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
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09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf.c
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