| 2de8874ec37bfc548de2e16bbefa51341e25d340 |
|
02-Feb-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Compute the maximum SF source attribute.
The maximum SF source attribute is necessary to compute the Vertex URB
read length properly, which will be done in the next commit.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Tested-by: Martin Steigerwald <martin@lichtvoll.de>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 5e9bc7bd1290b0c34be90e9a0b8298ebe4b4b131)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 3ebfd3f7743e5c05661eab977b23441e45441b39 |
|
07-Sep-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Refactor texture swizzle generation into a helper.
It's going to be reused in a second place soon.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit b5a042a657fed45264406cbd0d67fa6217a410a1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| b922999a404322a1034c4f96c21acae860483bb0 |
|
25-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix primitive restart on Haswell.
Haswell moved the "Cut Index Enable" bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0xffffffff.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 815d9d405c69bb07d550ae9f79283dcdc7466e2c)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 993c52d0be5bdf0e30e64ab4c6e1347c5dcb8e3b |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Replace general sw fallback support with a manual check for rendermode.
There were no other cases that set it any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 2faa592e7f54ef21b799b61ffa50c6bc8039ddc1 |
|
24-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add a "sampler state index" parameter to update_sampler_state().
This represents the index into the sampler state table or sampler
default color table (the two are identical).
Right now, this is still the texture unit, but that will change shortly.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 25d2bf3845e9a6faaef8d808c1255ec57dc71dba |
|
20-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965: Bind UBOs as surfaces like we do for pull constants.
v2: Comment fix, drop extraneous parens (review by Kenneth)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 5bffbd7ba2ba2ff21469b2a69a0ed67f0802fec7 |
|
20-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add an offset argument to constant buffer setup.
We'll use this for UBO surfaces.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 989218b9801f0afd0cbadce19a5719b0aa0deb70 |
|
09-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Configure SURFACE_STATE correctly for IMS surfaces.
This patch modifies gen7_set_surface_num_multisamples() to set up the
SURFACE_STATE appropriately for texturing from IMS format MSAA
surfaces (which are only used on Gen7 for depth and stencil buffers).
Since the function now sets more than just the number of multisamples,
it's been renamed to gen7_set_surface_msaa().
This will make it possible to remove some kludginess from the blorp
engine.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 7b3263af696e504ec68b91b0ce128d46a0691dce |
|
03-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Set SURFACE_STATE properly when CMS MSAA is in use.
When a buffer using Gen7's CMS MSAA layout is bound to a texture or a
render target, the SURFACE_STATE structure needs to point to the MCS
buffer and to indicate its pitch. This patch updates the functions
that emit SURFACE_STATE to handle CMS layout properly.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 31f3dfd59b6687214402c395ee03e7498fd6c79a |
|
09-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Validate Gen7 surface state constraints.
When a Gen7 SURFACE_STATE is configured for MSAA, a number of
additional constaints come in to play. This patch adds a function
gen7_check_surface_setup() which verifies that all of those
constraints are met.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 36e34134184e72532f2e6a2b9438f72284ac3057 |
|
27-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Expose surface setup internals for use by blits.
This patch exposes the functions brw_get_surface_tiling_bits and
gen7_set_surface_tiling, so that they can be re-used when setting up
surface states in gen6_blorp.cpp and gen7_blorp.cpp.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 434fc8bde41f07687ad8941ceba03c4b3e0e75bb |
|
27-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add extern "C" declarations to headers
These declarations are necessary to allow C++ code to call C code
without causing unresolved symbols (which would make the driver fail
to load).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 5a7942c2f1e3af4daedd92c1ddf21fa6a0e4e752 |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Rename the original binding table to mention that it's the WM now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| f9c3ea32cd9b243050ee16f10d6eb9d9c8b3a8ea |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the gen6 GS binding table to a separate table.
Improves VS state change microbenchmark performance by 7.08729% +/-
1.22289% (n=10) on gen7, because we don't upload the 64 dwords of
unused binding table any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 07e00b3040d6da381595c65db5afe597f20d99fc |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the VS binding table to a separate table.
This is a step toward making the samplers/binding tables reflect
sampler uniform mappings instead of embedding those in the programs.
No significant performance difference on the microbenchmark (n=10).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 28cfa1fa213fe7ba6e5b57e61da663a6c3bf0c13 |
|
11-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't reallocate push constant URB space on new VS programs.
The gen7_urb atom depends on CACHE_NEW_VS_PROG and CACHE_NEW_GS_PROG,
causing gen7_upload_urb() to be called when switching to a new VS
program.
In addition to partitioning the URB space between the VS and GS,
gen7_upload_urb() also allocated space for VS and PS push constants.
Unfortunately, this meant that whenever CACHE_NEW_VS was flagged, we'd
reallocate the space for the PS push constants. According to the BSpec,
after sending 3DSTATE_PUSH_CONSTANT_ALLOC_PS, we must reprogram
3DSTATE_CONSTANT_PS prior to the next 3DPRIMITIVE.
Since our URB allocation for push constants is entirely static, it makes
sense to split it out into its own atom that only subscribes to
BRW_NEW_CONTEXT. This avoids reallocating the space and trashing
constants.
Fixes a rendering artifact in Extreme Tuxracer, where instead of a snow
trail, you'd get a bright red streak (affectionately known as the
"bloody penguin bug").
This also explains why adding VS-related dirty bits to gen7_ps_state
made the problem disappear: it made 3DSTATE_CONSTANT_PS be emitted after
every 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet.
NOTE: This is a candidate for the 7.11 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38868
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 6a26005c1e298ec205c339b1b53b3dff6e1fd03c |
|
08-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correct misspellings of "invariant".
$ dict invarient
No definitions found for "invarient", perhaps you mean:
gcide: Invariant
wn: invariant
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| f8328c998b4d68c62ba939165390c2c22c5b5740 |
|
19-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Ensure correct transform feedback indices on new batch.
We don't currently have kernel support for saving GPU registers on a
context switch, so if multiple processes are performing transform
feedback at the same time, their SVBI registers will interfere with
each other. To avoid this situation, we keep a software shadow of the
state of the SVBI 0 register (which is the only register we use), and
re-upload it on every new batch.
The function that updates the shadow state of SVBI 0 is called
brw_update_primitive_count, since it will also be used to update the
counters for the PRIMITIVES_GENERATED and
TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| d84a180417d1eabd680554970f1eaaa93abcd41e |
|
17-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
This will make handling new formats (like actually exposing Z32F)
easier and more reliable.
v2: Remove the check for hiz buffer -- the MESA_FORMAT should really
be giving us the value we want even for hiz.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 9ae10e9cbdfce6404a3d86188f2897d8f5d0dcb2 |
|
10-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make Gen6+ renderbuffer surface updates not depend on NEW_COLOR.
NEW_COLOR is only needed on Gen4-5 as brw_update_renderbuffer_surfaces
only uses ctx->Color when intel->gen < 6.
This should reduce unnecessary state updates.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 32dfa6e5ef3d1fb703ec34942c55408be22e7ec3 |
|
28-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move and rename "wm sampler" fields to just "sampler".
brw_wm_samplers actually enables any active samplers regardless of what
pipeline stage is using them, so it doesn't make much sense for it to be
WM-specific. So, rename it to "brw_samplers."
To properly generalize it, move sampler_count and sampler_offset from
brw_context::wm to a new brw_context::sampler that can be shared without
looking strange.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 91043c21f9b82054060311aabb617dd6e5058602 |
|
07-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Clean up code for VS pull constant surface creation.
Like for the WM pull constants, we can merge the former prepare/emit
stages into one tracked state atom. Furthermore, the code that used to
handle the binding table was removed in the last commit, leaving some
rather silly looking short functions that can easily be folded in.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| e7c29c5de82f6de3d30ed1143d9672dd2e25f0e7 |
|
31-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use a single binding table for all pipeline stages.
Although the hardware supports separate binding tables for each pipeline
stage, we don't see much advantage over a single shared table.
Consider the contents of the binding table:
- Textures (16)
- Draw buffers (8)
- Pull constant buffers (1 for VS, 1 for WM)
OpenGL's texture bindings are global: the same set of textures is
available to all shader targets. So our binding table entries for
textures would be exactly the same in every table.
There are only two pull constant buffers (not many), and although draw
buffers aren't interesting to the VS, it shouldn't hurt to have them in
the table. The hardware supports up to 254 binding table entries, and
we currently only use 26.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 4a42bd3931d6298ab9a84b76957ce5d83d289f69 |
|
02-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split brw_wm_surfaces state into renderbuffer and texture atoms.
First, the texturing setup code is relevant for all pipeline stages,
while renderbuffer surfaces are only used by the WM.
Secondly, renderbuffer and texture setup depends on a different set of
dirty bits. There's no reason to walk the array of textures when
changing draw buffers, or vice-versa.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| a7d0fa209b444e3c7ad9358f1d31e3f638c20e40 |
|
02-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine the two WM pull constant tracked state atoms.
These were only split for historical reasons: brw_wm_constants used to
be the "prepare" step, while brw_wm_constant_surface was "emit". Now
that both happen at emit time, it makes sense to combine them.
Call the newly combined state atom "brw_wm_pull_constants" to indicate
help distinguish it from the Gen6+ atoms that handle push constants.
Finally, remove the BRW_NEW_WM_CONSTBUF dirty bit entirely now that it's
never flagged nor used.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| f3e9ccb3bcd174a0b55cae6f9c56835145558e89 |
|
04-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename gen6_*_constants tracked state atoms to "push_constants".
When reading the "brw_wm_constants" and "gen6_wm_constants" atoms
side-by-side, I initially failed to notice the crucial difference:
the Gen6 atoms are for Push Constants, while brw_wm_constants handles
Pull Constants. (Gen4/5 Push Constants are handled by "brw_curbe.")
Renaming these should clarify the code and save me from constant
confusion over the fact that "gen6_wm_constants" isn't just a newer
version of "brw_wm_constants."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 5d448b42b7143a1a38911b23d94b5c5d5bfa79f0 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add new vtable entries for surface state updating functions.
Gen7+ SURFACE_STATE is different from Gen4-6, so we need separate
per-generation functions for creating and updating it. However, the
usage is the same, and callers just want to utilize the appropriate
functions with minimal pain. So, put them in the vtable.
Since these take a brw_context pointer and are only used on Gen4, just
add a forward declaration. This is the simplest (if not cleanest)
solution. It would be nicer to have a i965-specific vtable, but that's
a refactor for another day.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 35c7e8cebeaae67c80254224cda46ee17f6d5868 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Merge brw_validate_state() and brw_upload_state() together.
They were called back-to-back at this point.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| eaf4d3e6e2493a6e0b20d1205a5fb33ce500c9c2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the validated BO list, now that it's unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 018ea68d8780ab5baeef0b8122b8410e5e55ae6d |
|
27-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 Gen6+: De-compact clip planes.
Previously, if the user enabled a non-consecutive set of clip planes
(e.g. 0, 1, and 3), the driver would compact them down to a
consecutive set starting at 0. This optimization was of dubious
value, and complicated the implementation of gl_ClipDistance.
This patch changes the driver so that with Gen6 and later chipsets, we
no longer compact the clip planes. However, we still discard any clip
planes beyond the highest number that is in use, so performance should
not be affected for applications that use clip planes consecutively
from 0.
With chipsets previous to Gen6, we still compact the clip planes,
since the pre-Gen6 clipper thread relies on this behavior.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| a864b82a04efd0642f5b2a9489b3c20dac46551f |
|
21-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: allow for nonconsecutive elements of gl_ClipDistance to be enabled.
When using user-defined clipping planes, the i965 driver compacts the
array of clipping planes so that disabled clipping planes do not
appear in it--this saves precious push constant space and makes it
easier to generate the pre-GEN6 clip program. As a result, when
enabling clipping planes in GEN6+ hardware, we always enable clipping
planes 0 through n-1 (where n is the number of clipping planes
enabled), regardless of which clipping planes the user actually
requested.
However, we can't do this when using gl_ClipDistance, because it would
be prohibitively complex to compact the gl_ClipDistance array inside
the user-supplied vertex shader. So, when enabling clipping planes in
GEN6+ hardware, if gl_ClipDistance is in use, we need to pass the
user-supplied enable flags directly through to the hardware rather
than just enabling the first n planes.
Fixes Piglit test vs-clip-distance-enables.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 2d909f431c67d0c8c5075dc40f2901076c5bc48b |
|
30-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: SF: New implementation of get_attr_override using the VUE map.
This patch changes get_attr_override() (which computes the
relationship between vertex shader outputs and fragment shader inputs)
to use the VUE map.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| d375df220fae47f38944c4832bcbd5f5d568884c |
|
23-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a type argument to brw_state_batch().
I want to make brw_state_dump.c handle more than just the last
statechange, so I want to keep track of what's in the batch state. By
using AUB file numbering for most of these packets, this may be
reusable for aub dumping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 4ef8464068bc96ea9af71bbd18d121358db303b2 |
|
07-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Call gen7_create_constant_surface instead of brw_[...].
Fixes 17 piglit tests:
- glsl-vs-arrays-3
- glsl-vs-texturematrix-2
- glsl-vs-uniform-array-2
- arl
- nv-arl
- nv-init-zero-addr
- vp-address-01
- vp-arl-constant-array
- vp-arl-constant-array-huge
- vp-arl-constant-array-huge-offset
- vp-arl-constant-array-huge-offset-neg
- vp-arl-constant-array-huge-relative-offset
- vp-arl-constant-array-huge-varying
- vp-arl-env-array
- vp-arl-local-array
- vp-arl-neg-array
- vp-arl-neg-array-2
Fixes 4 glean tests:
- glsl1-constant array of vec4 with variable indexing, vertex shader
- glsl1-constant array with variable indexing, vertex shader
- glsl1-constant array with variable indexing, vertex shader (2)
- vp1-ARL test
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| b126a0c0cb30b1e2f2df1953fe14d8596d1cf4f7 |
|
02-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for correct GL_CLAMP behavior by clamping coordinates.
This removes the stupid strict-conformance fallback code I broke when
adding ARB_sampler_objects.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36572
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 3f44043da37bcd0c481ceddf4f878ddb3419b763 |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix SAMPLER_STATE on Ivybridge.
Most of this code copied from brw_wm_sampler_state.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 3984372104ec6ac5986dedb07b8ca99d53dede18 |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Mark some brw_wm_sampler_state.c helper functions as non-static.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| b2b6cc662271d611462532222ef2fcc30042bd0f |
|
28-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update SURFACE_STATE for Ivybridge.
I'm still not happy with the amount of code duplication here, but it
will have to do for now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| c12a93d5c452da16ff0c8955e55770b8eda28036 |
|
28-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Mark a few more brw_wm_surface_state functions as non-static.
I need to reuse them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 70c6cd39bd9396b0d3f9e84df41fd8bef1f26cc4 |
|
28-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Change brw_format_for_mesa_format to a non-static function.
This will make it easier to share between files.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 8c8985bdd714f43a96ce922a7c0284d50aec3d1a |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add depth buffer support on Ivybridge.
This also disables the HiZ and separate stencil buffers. We still need
to implement stencil.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| bc08d4ebb832769aacb4aecaaf1e490f97c53d65 |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Upload sampler state pointers on Ivybridge.
Since we currently only support sampling in the fragment shader, we only
bother to emit the PS variant. In the future we'll need to emit others.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| bac10b58de69108bdb2cc3358733e2648ab7c5d2 |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Explicitly disable unused pipeline stages on Ivybridge.
This may not be strictly necessary, but seems wise.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 6b2010df7d55ad9feacbbcf708a83a66cdf91aaf |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge VS state.
Copied from gen6_vs_state.c; reuses create_vs_constant_bo from there.
The 3DSTATE_VS command is identical but 3DSTATE_CONSTANT_VS is not.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 18402fbf79e96d7afb6b690906a7656f01a92b9d |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge Viewport state setup.
SF and CLIP viewport state has been combined into SF_CLIP_VIEWPORT;
SF_CLIP and CC state pointers can now be uploaded independently.
Some portions of the hardware documentation refer to separate upload
commands for SF and CLIP; these are outdated and incorrect.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 81fd03fe56372c5c702bf257e821cea71ee25448 |
|
28-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge Clip state setup.
Copied from gen6_clip_state.c.
This enables early culling and sets the necessary fields. Otherwise, it
is entirely the same, so I doubt this patch is strictly necessary for a
functional driver.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 24d0ed72c1817b624e3021b12a0987b2c5edd71b |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge CC state setup.
The state itself still seems to be the same; the only change is that
each part (CC, BLEND, DEPTH_STENCIL) can now be uploaded independently.
Thus, we still rely on the code in gen6_cc.c to set up the state.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| a924d69b57a82c02f2d4fba3fc0b31bf6a4f744e |
|
03-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge WM/PS state setup.
Copied from gen6_wm_state.c.
The main change from Sandybridge seems to be that 3DSTATE_WM was split
into two separate state packet commands: 3DSTATE_WM and 3DSTATE_PS.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 7d608d0c331c101088273655708965fb9f1be56e |
|
05-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge SF/SBE state setup.
Copied from gen6_sf_state.c.
The main change from Sandybridge seems to be that 3DSTATE_SF was split
into two separate state packet commands: 3DSTATE_SF and 3DSTATE_SBE
("setup backend"). The bit-offsets are even the same - only the DWords
numbers have shuffled around a bit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 3dc4bc1f78db876d2dcb76153ecf9992fcce73e4 |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make gen6_sf_state.c's get_attr_override non-static.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 8832920c298f4e13ffd5e53feeba509be69edb16 |
|
27-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge URB space partitioning, including push constants.
Currently this always reserves 16kB for push constants, regardless of
how much space is needed, and partitions it evenly betwen the VS and FS.
This is probably not ideal, but is straightforward.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 3032582d032a28381dd4c2f4093d82c79e73129e |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead entrypoints to state cache, rename the one that's left.
As we expanded the usage of the state cache, it grew extra
functionality. However, with the recent state streaming rework, we're
back to the state cache being used only for shader kernels, which is
the piece of GPU state that's actually expensive to compute again from
scratch, since it involves compiling.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| d6ba7b16039b3cf03903888df23732cbb358e810 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop the now unused brw_cache_data() function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 855f56ca13c1003396a81da1a110357d624a2101 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Move scissor state to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| d67c08319fda7d0f2df98d60b64c8cc2f3e06c44 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the CC VP to state streaming.
This is in a way a revert of f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f.
The tiny win that had will be overwhelmed by the win of using the gen6
dynamic state base address.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 32cc0c9d8de343f699e80e7e416ea0d7e3121a42 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Stream the VS push constants.
Improves 3DMMES taiji demo performance by 10.1% +/- 0.9% (n=15).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| aac120977d1ead319141d48d65c9bba626ec03b8 |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Move repeat-instruction-suppression to batchbuffer core
Move the tracking of the last emitted instructions into the core
batchbuffer routines and take advantage of the shadow batch copy to
avoid extra memory allocations and copies.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 3f55683927278e57f3ef8a151d15f4cffdc060dc |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: drop state_bo references to batch_bo
As we use state relocations and we know that all the state belongs to
the same bo, we can drop the multiple references to the same bo.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 59fa8600d8efa803a4f86a41beaca78f7be41d7c |
|
28-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
Revert "i965: upload multisample state for fragment program change"
This reverts commit de6fd527a545f8344e074312544517d05573fb72.
Revert this workaround as it seems the real trouble is caused by
lineloop, which doesn't require GS convert on sandybridge actually.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| de6fd527a545f8344e074312544517d05573fb72 |
|
23-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: upload multisample state for fragment program change
This makes conformance tests stable on sandybridge D0 to track
multisample state before SF/WM state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| c27285610c9f9b50d06bf0f2725da195937cb48d |
|
13-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for using the BLT ring on gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 4b6b0bf24a043035d7ada0c966e01df6327dc529 |
|
28-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix scissor state on sandybridge
Fix incorrect scissor rect struct and missed scissor state pointer
setting for sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 556f19415a5210aacd52d652b8aae6e58c44e4ed |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up WM push constant setup on gen6.
Fixes glsl-algebraic-add-add-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 32ea5394173ecbfb766c5c02eccb21642aec0483 |
|
29-Jul-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Declare the various tracked state variables using "extern"
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 0f59b9a95d21dc79e98bce4ece3eab19e32ca80a |
|
12-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Update gen6 paths for the streaming rework.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 108264e859b4f435e9608472dc2e388aa200183c |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove the surface key used to generate constant surfaces.
We had to fill out all that junk when using the cache, but no more.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 8ad3fdc9678866b40f3d9faaaf7c6333d388907f |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: GC the last two arguments to brw_cache_data.
Now that the binding table is streamed indirect state, they were
always NULL/0.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 309c011641c6189dc74bc2f78ba6d6602d8c96b7 |
|
08-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw_state_cache_bo_delete now that it's unused again.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 178414eba402f9087ea505e7ef19f1becdd7a36d |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove caching of surface state objects.
It turns out that computing a 56 byte key to look up a 20-byte object
out of a hash table was some sort of a bad idea. Whoops.
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
after:
[ 0] gl firefox-talos-gfx 34.761 34.784 0.17% 5/6
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 73de09f265cb1c66d70fd9eb92021882bfbbbef6 |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Convert the binding table to streamed indirect state.
This slightly reduces reduces cairo-gl firefox-talos-gfx runtime on my
Ironlake:
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 38.236 38.383 0.43% 5/6
after:
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
It turns out the cost of caching these objects and looking them up in
the cache again is greater than the cost of just computing the object
again, particularly when the overhead of having a separate BO to pin
is removed.
(Those that are paying close attention will note that this is a
reversal of the path I was moving the driver in a couple of years ago.
The major thing that has changed is that back then all state was
recomputed when we wrapped the streaming state buffer, including
recompiling our precious programs. Now, we're uncaching just the
objects that are cheap to compute, and retaining caching of expensive
objects)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 118a47623a11a374df371d52ed0294224e6a62dc |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Split constant buffer setup from its surface state/binding state.
This was bothering me when redoing the binding tables.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 321014156b3f7842a84d9b9915389c9f6f6486f5 |
|
11-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for streaming indirect state rather than caching objects.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the CC VP state immediately on state change.
The cache lookup of these two little floats was .12% of total CPU time
on firefox-talos-gfx because we did it any time commonly-changed state
changed. On the other hand, updating the CC VP bo immediately whenver
CC VP state changes is a .07% overhead due to putting a driver hoook
in glEnable().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| c791f8a1e532834ae7a517c042e9efe262b62233 |
|
01-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set up the SNB sampler state pointers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| ab8c37fe18e0367e8718774198a0d0086fde0cf9 |
|
21-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Untested Sandybridge WM packets.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 70be48dff6bb68c61285641e4d976bfd53e0f00c |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Untested Sandybridge SF setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 1ae0cb5f286bbba10e99c8e3bc1c55d2aeb38b59 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add Sandybridge viewport setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 64e0c586a74553b2941f18feb199d8cddb192102 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add Sandybridge scissor state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| c9dc6d425e645f2988118ff51cabe167a0cd3971 |
|
04-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set up the SNB URB.
even with vs disabled, still doesn't work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| f58fbcf7618bcc6ef9da8e8939100b14ea4d584b |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add untested REJECT_ALL clip state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 520b64ddfb4c2efa742bc2217fef96fdec5eea9b |
|
27-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add untested passthrough GS setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| ba882d7827e5526e99c9d5c453d56c5e029c7476 |
|
16-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add untested Sandybridge passthrough VS setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 7ee590424c974cb10882e9c4664a6024595fc9de |
|
29-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start adding support for the Sandybridge CC unit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 9dce60f35b25f4f5605b22d75447bac5d9f55515 |
|
03-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set up sandybridge binding table pointers but don't enable it yet.
It hangs the GPU at the clipper stage, presumably because we're lacking
other setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 5203b7227ccb6b618fa42f08434d4a3cf123dca2 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop batchbuffer cliprect_mode tracking
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| c67bb15d4e3da430d511444bd7d159ccb0c84b73 |
|
29-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
intel: Silence compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 8451b29d9628f09b65962385bfbd95cd7f26427f |
|
21-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix several memory leaks on exit.
Bug #25194.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 8395da2e8af40367714c70afe299568272f36cc8 |
|
05-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Always pass the size argument to brw_cache_data.
This keeps the individual state files from having to export their
structures for brw_state_cache initialization.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 49fbdd18ed738feaf73b7faba4d3577cd9cc3e59 |
|
12-Feb-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix massive memory allocation for streaming texture usage.
Once we've freed a miptree, we won't see any more state cache requests
that would hit the things that pointed at it until we've let the miptree
get released back into the BO cache to be reused. By leaving those
surface state and binding table pointers that pointed at it around, we
would end up with up to (500 * texture size) in memory uselessly consumed
by the state cache.
Bug #20057
Bug #23530
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 54107a097904129ff794534542acd09ed152ea2e |
|
24-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Clean up some mess with the batch cache.
Its flagging of extra state that's already flagged by the vtbl new_batch
when appropriate was confusing my tracking down of the OA clear bug.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 255e5be265133280293bbfd8b2f9b74b2dec50bb |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Avoid re-uploading the index buffer when we don't need to.
No performance difference proven at 95% confidence with my GLSL demo (n=10).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 71fb9d62ece0177183efd5bb955d1f3292cb4376 |
|
06-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Split WM constant buffer update from other WM surfaces.
This can avoid re-uploading constant data when it isn't necessary, and is
a step towards not updating other surfaces just because constants change.
It also brings the upload of the constant buffer next to the creation.
This brings openarena performance up another 4%, to 91% of the Mesa 7.4 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 9490d86808300e5819941a40784e272c290e05ee |
|
05-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Disentangle VS constant surface state from WM surface state.
Also, only create VS surface state if there's a VS constant buffer to be
uploaded, and set the contents of the buffer at the same time as creation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| f9af97c7a5d81226a87d79baf8fb00231c96398d |
|
22-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: use two state caches instead of one
The new, second cache will only be used for surface-related items.
Since we can create many surfaces the original, single cache could get
filled quickly. When we cleared it, we had to regenerate shaders, etc.
With two caches, we can avoid doing that.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| d0415a5a01c1a8c2c2a389d977401a7f6cee031b |
|
25-Feb-2009 |
Eric Anholt <eric@anholt.net> |
i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| b9b482bd8de366289158a916e16414c5a74819c9 |
|
07-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead brw_vs_tnl.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix check_aperture calls to cover everything needed for the prim at once.
Previously, since my check_aperture API change, we would check each piece of
state against the batchbuffer individually, but not all the state against the
batchbuffer at once. In addition to not being terribly useful in assuring
success, it probably also increased CPU load by calling check_aperture many
times per primitive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 0cade4de4f74f6b0e86fb6622e2fc370c73fd840 |
|
20-Oct-2008 |
Eric Anholt <eric@anholt.net> |
intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time. Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| b5d59222ccbec9db23b6847737765a4dc0d8c47b |
|
26-Sep-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Remove TNL-to-VP tracking from i965
The i965 driver previously had it's own set of code to convert
fixed-function TNL state to a vertex program. Core Mesa has code to
do this, so there is no reason to duplicate that effort in the driver.
In fact, this duplication leads to bugs when other aspects of the Mesa
infrastructure change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 1fd82451eb8a76f2df85720e8d9d607d9e37ab24 |
|
08-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove stale brw_state_cache.c comment and function export.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| a04b632350e5d0e9994fc667afc59407a39da0ba |
|
10-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:
- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
(copybuffers, clears).
All callers should now be fixed to use one of these states for any batchbuffer
emits. Thanks to Keith Whitwell for pointing out the failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| d9edd8e90588417e3d549f25132dab2f21445792 |
|
09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove drawing rect upload, which is handled (better) by the kernel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_state.h
|