| 1bd4d456cdecf7bea55f4e3dac574af54efad994 |
|
04-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:
There are three types of multisampled surface layouts designated
as follows:
- IMS Interleaved Multisampled Surface
- CMS Compressed Mulitsampled Surface
- UMS Uncompressed Multisampled Surface
Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved. To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}. It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM. CMS layout is not yet used.
The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 455ac562722f60ac9fb0c3d3c697fa339fa011ad |
|
08-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Properly handle sliced layout for Gen7.
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for depth and stencil
surfaces only.
- Sliced, in which the surface is stored as a 2D array, with array
slice n containing all pixel data for sample n. On Gen7 this layout
is used for color surfaces.
The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.
This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode. It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| f939776cb2372a3427784f88d34bf14c18a5a212 |
|
02-May-2012 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: fix wrong cube/3D texture layout
Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.
From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
All of the LOD=0 q-planes are stacked vertically, then below that,
the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
stacked four-wide below that, and so on.
Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.
This would fix the following webgl test case on all gen4 platforms:
conformance/textures/texture-size-cube-maps.html
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 8a472427559ea33186c71dfbab8254651fec3077 |
|
17-Jan-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Set depth to 6 for cubemaps
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41216
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43212
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43250
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jin Yang <jin.a.yang@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 79d981cd03f2e2e8f67ab21d52711de989bb9a44 |
|
15-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't minify depth when setting up cube map miptrees on Gen4.
Prior to Ironlake, cube maps were stored as 3D textures. In recent
refactoring, we removed a separate "layers" parameter in favor of using
depth. Unfortunately, depth was getting minified, which is only correct
for actual 3D textures.
Fixes piglit tests:
- bugs/crash-cubemap-order
- fbo/fbo-cubemap
- texturing/cubemap
Also changes texturing/cubemap npot from abort to fail.
This hasn't seen a full test run since Piglit on Mesa master hangs
GM45 a lot.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 017c13d55b5b086774d6afea2ca754482c624c6a |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Store miptree alignment units in the miptree
This allows us to replace all the calls to
intel_get_texture_alignment_unit() with a single call at miptree creation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| d7b33309fe160212f2eb73f471f3aedcb5d0b5c1 |
|
15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Kill intel_mipmap_level::nr_images [v4]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace "It's" with "Its".
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v4:
In intel_miptree_get_image_offset(), document the conditions under
which different if-branches are taken.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 669f1822d2a60865514faf37f9fde21e4567b3d2 |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_texture_array and GL_MESA_texture_array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 2e0aefc1b9023a3d4003c1974489252d29b1d65b |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Refactor out the cube map setup for general texture array setup.
This is just moving the code out with s/6/slices/.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| d7cdbc3c5415d2dd5eee58834b13714a89eacf2b |
|
24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Remove pointless boolean return value from *_miptree_layout.
i915_miptree_layout, i945_miptree_layout, and brw_miptree_layout always
just return GL_TRUE, so there's really no point to it. Change them to
void functions and remove the (dead) error checking code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 36a91e45f755af164232ef908419bc4cb64ba45b |
|
26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence several "warning: unused parameter"
The intel_context and tiling parameters were not used by any if the
i9[14]5_miptree_layout or the functions they call, and the tiling parameter was
not used by brw_miptree_layout. Remove the unnecessary parameters.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 477b74e85be8e468c63af9f2f3fe788e486764ce |
|
15-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use proper texture alignment units for cubemaps on Gen5+.
In particular, S3TC compressed textures need align_h == 4.
Fixes skybox errors in Quake 4 and FEAR.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34628
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 81b036b4d79423c194596461b098a525af0102c2 |
|
31-Jul-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen5+: Fix incorrect miptree layout for non-power-of-two cubemaps.
For power-of-two sizes, h0 == mt->height0 since it's already a multiple
of two. However, for NPOT, they're different; h1 should be computed
based on the original size.
Fixes piglit test "cubemap npot" and oglconform test "textureNPOT".
NOTE: This is a candidate for stable release branches.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 4a60b0c8d2e4890038e1c6a72a7dac3b4cdf996e |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add block alignment for RGTC textures.
We were using the default 4x2 alignment instead of the 4x4 required
for RGTC textures.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| d0c6d24a9ebe31b3a805e8f5845fc7e6fa552a98 |
|
22-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Fix miptree layout for cube surfaces.
Volume 1a section 8.20.4.7.3 gives new equations which multiply by 12
instead of 11.
Fixes 8 piglit tests:
- fbo-cubemap
- texCube
- glsl-fs-texturecube
- glsl-fs-texturecube-2
- glsl-fs-texturecube-2-bias
- glsl-fs-texturecube-bias
- arb_seamless_cubemap
- cubemap
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| b522eb0717986bc7d8ca46ac1dd93a865e211345 |
|
22-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove comments about pre-965 hardware.
They're irrelevant for this driver.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 5b3eb7538cd9ceb967b6e9e765896183e7c2c4d4 |
|
10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."
This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.
I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier. This meant that i915 would have
never used the mag filter when baselevel != 0. Not a severe bug, but
not an intentional regression. I think we can fix the performance
issue another way.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 7ce6517f3ac41bf770ab39aba4509d4f535ef663 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Always allocate miptrees from level 0, not tObj->BaseLevel.
BaseLevel/MaxLevel are mostly used for two things: clamping texture
access for FBO rendering, and limiting the used mipmap levels when
incrementally loading textures. By restricting our mipmap trees to
just the current BaseLevel/MaxLevel, we caused reallocation thrashing
in the common case, for a theoretical win if someone really did want
just levels 2..4 or whatever of their texture object.
Bug #30366
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 956f866030f7bea5fc4a2de28c72e60bdc3a5b3d |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Fix sampler on sandybridge
Sandybridge has not much change on texture sampler with Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 7d8f0fc28239c8023d2d44cbd4c979aa86c31873 |
|
29-Apr-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix cube map layouts on Ironlake.
We were doubling up the offsets for the mipmap levels for CPU access.
Instead of reimplementing i945_miptree_layout_2d with 6 cube images
separated by qpitch, share that function and provide the level offsets
later.
Fixes piglit cubemap and fbo-cubemap.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 362c1bf75eb74de5b4655c481b74f79718ed4a34 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Replace mt->pitch with mt->region->pitch.
The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 6e0f702b23ebdc9fbf6b20697624bc77be08383e |
|
31-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 2d17dbfb5346b6d75e87c839148cbe125bf5cd6d |
|
09-Jul-2009 |
Eric Anholt <eric@anholt.net> |
intel: Keep track of x,y offsets in miptrees and use them for blitting.
By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.
Fixes piglit fbo-clearmipmap.
Bug #23552. (automatic mipmap generation)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 29e51c3872531366570d032147abad50f8a3c1af |
|
19-Aug-2009 |
Eric Anholt <eric@anholt.net> |
intel: Fix failure to commit -a --amend before last push.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| a70e1315846cd5e8d6f2b622821ff8262fe7179d |
|
19-Aug-2009 |
Eric Anholt <eric@anholt.net> |
intel: Align cubemap texture height to its padding requirements.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 1f40ffca634b8d6699c9b5d153c231e79527317a |
|
13-Aug-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix cube map on IGDNG
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 6c3f6968911e0bb3256e91b070166d3da78a4775 |
|
18-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix up texture layout for small things with wide pitches (tiled)
We were packing according to the pitch, while the hardware appears to base
it on the base level width.
With this and the previous commit, fbo-cubemap now matches untiled behavior.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| bd0861e2742c22e4bce83bce40dfdbfd713835df |
|
21-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: fix whitespace in brw_tex_layout.c
The broken indentation was driving me crazy, so fix other stuff while
I'm here.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| dd1a868b74ac47ac26f600f2f1eb0dc3f535f31b |
|
18-Dec-2007 |
Keith Packard <keithp@keithp.com> |
[INTEL] Fix 965 to use new centralized mipmap pitch function
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 27674c41352dc78ad79f67cebca16d7896cd2093 |
|
20-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 77e0523fb7769df4bf43747e136b1653b2421b97 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 00b86ecf6f2f936bad6d628622ea5546c780ab8d |
|
17-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: align width/height for volume texture
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 3416ef303af633668cece0b199b4a8b2388c1e2f |
|
14-Dec-2006 |
Michel Dänzer <michel@tungstengraphics.com> |
Share code to lay out >= 945 style 2D mipmaps between i915tex and i965 drivers.
Use the i965 version as it has some fixes over the i915tex version.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| e38114a5e4492684333251eb22bc60ee1038de55 |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Support ARB_texture_rectangle.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_tex_layout.c
|