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16-Mar-2014 |
Simon Hosie <simon.hosie@arm.com> |
Optimisations to 3DLUT assembly.
Process more pixels at once to try to keep the register file fuller and more
tightly packed and allow more concurrency. Implementations in AArch32 and
AArch64 assembly.
Change-Id: I683078ff02155cc14bacce35bce3d3fe06857095
/frameworks/rs/cpu_ref/rsCpuIntrinsics_advsimd_3DLUT.S
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