Lines Matching refs:v4i32
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
121 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
142 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
147 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
152 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
157 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1353 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1525 EVT NewVT = MVT::v4i32;
1535 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,