Lines Matching refs:v4i32
793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
803 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
810 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
832 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
893 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
919 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
920 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
950 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
968 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
973 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
975 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1017 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1105 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1157 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1164 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1295 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1303 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1472 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1473 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1474 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1715 return MVT::v4i32;
1813 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
3953 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4161 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4165 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4559 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4835 //of a v4i32 / v4f32. It's probably worth generalizing.
5506 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5626 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5633 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5636 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5688 EVT VecVT = MVT::v4i32;
5733 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5739 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6257 case MVT::v4i32:
6269 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6759 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6760 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6765 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6766 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6980 ExtVT = MVT::v4i32;
7423 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7424 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7430 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7712 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7713 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7714 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7722 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7731 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7747 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7753 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7758 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7766 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7771 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7776 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7778 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7780 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7782 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7788 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7794 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7799 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7807 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8729 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8817 case MVT::v4i32:
10374 MVT::v4i32,
10400 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10518 MVT::v4i32, Vec),
10744 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11528 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11531 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11532 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11546 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11547 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11567 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11622 bool Is128 = VecIntVT == MVT::v4i32;
11630 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11729 case MVT::v4i32:
11928 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11929 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11932 // v4i32 -> v4i64
11933 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11934 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11940 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12066 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12067 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12081 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12082 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12117 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12120 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12134 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12135 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12139 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13208 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13209 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13216 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13220 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13223 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13224 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13227 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13228 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13233 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13234 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13235 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13237 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13238 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13241 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13252 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13253 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13256 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13260 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13261 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13264 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13461 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13720 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13730 // v4i32 to v4i64
13733 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13734 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14633 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15895 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15896 if (VT == MVT::v4i32) {
15937 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16013 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16036 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16095 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16215 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16270 case MVT::v4i32:
16282 case MVT::v4i32:
16294 case MVT::v4i32:
16361 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16365 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16368 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16387 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16417 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16429 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16432 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16438 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16445 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16450 if (VT == MVT::v4i32) {
16482 EVT CastVT = MVT::v4i32;
16894 // Example: from MVT::v2i32 to MVT::v4i32.
16944 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
16946 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
20529 if (InputVector.getValueType() != MVT::v4i32)
20664 case MVT::v4i32:
21899 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23219 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23220 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23231 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23232 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23459 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23649 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23652 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23752 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23785 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24556 case MVT::v4i32: