| /external/llvm/lib/Target/X86/InstPrinter/ |
| H A D | X86ATTInstPrinter.cpp | 188 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); local
202 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
209 if (IndexReg.getReg() || BaseReg.getReg()) {
214 if (IndexReg.getReg()) {
|
| H A D | X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
179 if (IndexReg.getReg()) {
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 49 unsigned IndexReg; member in struct:llvm::X86AddressMode
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
|
| H A D | X86AsmPrinter.cpp | 239 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
249 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
269 assert(IndexReg.getReg() != X86::ESP &&
276 if (IndexReg.getReg()) {
305 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); local
323 if (IndexReg.getReg()) {
336 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| H A D | X86MCInstLower.cpp | 762 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; local
763 Opc = IndexReg = Displacement = SegmentReg = 0;
772 IndexReg = X86::RAX; break;
774 IndexReg = X86::RAX; break;
777 IndexReg = X86::RAX; break;
779 IndexReg = X86::RAX; break;
781 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
800 .addImm(ScaleVal).addReg(IndexReg)
|
| H A D | X86FastISel.cpp | 549 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
568 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
630 if (AM.IndexReg == 0) {
632 AM.IndexReg = getRegForValue(V);
633 return AM.IndexReg != 0;
716 unsigned IndexReg = AM.IndexReg; local
748 if (IndexReg == 0 &&
753 IndexReg = getRegForGEPIndex(Op).first;
754 if (IndexReg
[all...] |
| H A D | X86ISelDAGToDAG.cpp | 63 SDValue IndexReg; member in struct:__anon10925::X86ISelAddressMode
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
115 << "IndexReg ";
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
244 Index = AM.IndexReg;
751 AM.Base_Reg = AM.IndexReg;
763 AM.IndexReg.getNode() == nullptr &&
823 AM.IndexReg
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 53 unsigned IndexReg; member in struct:llvm::X86Operand::MemOp
118 return Mem.IndexReg;
484 Res->Mem.IndexReg = 0;
497 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
502 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
511 Res->Mem.IndexReg = IndexReg;
496 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(), void *OpDecl = nullptr) argument
|
| H A D | X86AsmParser.cpp | 255 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon10899::X86AsmParser::IntelExprStateMachine
264 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
269 unsigned getIndexReg() { return IndexReg; }
357 // If we already have a BaseReg, then assume this is the IndexReg with
362 assert (!IndexReg && "BaseReg/IndexReg already set!");
363 IndexReg = TmpReg;
394 // If we already have a BaseReg, then assume this is the IndexReg with
399 assert (!IndexReg && "BaseReg/IndexReg alread
799 CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, StringRef &ErrMsg) argument
1012 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1288 int IndexReg = SM.getIndexReg(); local
1886 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); local
69 (IndexReg.getReg() != 0 &&
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
227 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
231 (IndexReg.getReg() != 0 &&
232 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
242 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
246 (IndexReg.getReg() != 0 &&
247 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
371 const MCOperand &IndexReg local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 158 unsigned &IndexReg);
402 unsigned &IndexReg) {
424 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
425 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
489 unsigned IndexReg = 0; local
490 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
550 .addReg(Addr.Base.Reg).addReg(IndexReg);
622 unsigned IndexReg = 0; local
623 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
686 if (IndexReg)
401 PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, unsigned &IndexReg) argument
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2971 unsigned IndexReg = MI->getOperand(3).getReg(); local
2981 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
3013 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
|