Searched defs:NewOpcode (Results 1 - 17 of 17) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp73 int NewOpcode = 0; local
76 NewOpcode = Hexagon::J2_jumpf;
80 NewOpcode = Hexagon::J2_jumpt;
84 NewOpcode = Hexagon::J2_jumpfnewpt;
88 NewOpcode = Hexagon::J2_jumptnewpt;
95 MI->setDesc(TII->get(NewOpcode));
H A DHexagonVLIWPacketizer.cpp435 int NewOpcode; local
437 NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
439 NewOpcode = QII->GetDotNewOp(MI);
440 MI->setDesc(QII->get(NewOpcode));
447 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); local
448 MI->setDesc(QII->get(NewOpcode));
762 int NewOpcode = QII->GetDotNewOp(MI); local
763 const MCInstrDesc &desc = QII->get(NewOpcode);
H A DHexagonInstrInfo.cpp1655 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); local
1656 if (NewOpcode >= 0) // Valid predicate new instruction
1657 return NewOpcode;
/external/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp429 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); local
433 if (!NewOpcode) {
438 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
439 assert(NewOpcode && "No restore instruction available");
442 MBBI->setDesc(ZII->get(NewOpcode));
H A DSystemZInstrInfo.cpp49 // each having the opcode given by NewOpcode.
51 unsigned NewOpcode) const {
73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); local
92 assert(NewOpcode && "No support for huge argument lists yet");
93 MI->setDesc(get(NewOpcode));
725 unsigned NewOpcode; local
727 NewOpcode = SystemZ::RISBG;
730 NewOpcode
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp138 int NewOpcode; local
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
147 BuildMI(MBB, II, dl, TII.get(NewOpcode))
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp506 unsigned NewOpcode = local
510 const MCInstrDesc &NewDesc = TII->get(NewOpcode);
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp851 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; local
852 MI.setDesc(TII.get(NewOpcode));
H A DPPCAsmPrinter.cpp937 unsigned NewOpcode = local
941 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode)
951 unsigned NewOpcode = local
957 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode)
H A DPPCISelDAGToDAG.cpp4014 unsigned NewOpcode; local
4018 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
4019 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
4020 case PPC::SLW: NewOpcode = PPC::SLW8; break;
4021 case PPC::SRW: NewOpcode = PPC::SRW8; break;
4022 case PPC::LI: NewOpcode = PPC::LI8; break;
4023 case PPC::LIS: NewOpcode = PPC::LIS8; break;
4024 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
4025 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
4026 case PPC::CNTLZW: NewOpcode
[all...]
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp316 unsigned NewOpcode = 0; local
323 NewOpcode = X86::CBW;
327 NewOpcode = X86::CWDE;
331 NewOpcode = X86::CDQE;
335 if (NewOpcode != 0) {
337 Inst.setOpcode(NewOpcode);
H A DX86InstrInfo.cpp4279 unsigned NewOpcode = 0; local
4302 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4303 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4304 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4305 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4306 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4307 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4308 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4309 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4310 case X86::SUB64ri32: NewOpcode
[all...]
/external/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1559 std::string NewOpcode; local
1562 NewOpcode = Name;
1563 NewOpcode += '+';
1564 Name = NewOpcode;
1568 NewOpcode = Name;
1569 NewOpcode += '-';
1570 Name = NewOpcode;
1576 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1584 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
/external/llvm/lib/Target/R600/
H A DAMDILCFGStructurizer.cpp231 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
233 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
235 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
236 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
239 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
241 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
472 int NewOpcode, DebugLoc DL) {
474 ->CreateMachineInstr(TII->get(NewOpcode), DL);
481 int NewOpcode, DebugLoc DL) {
483 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), D
471 insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument
480 insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument
492 insertInstrBefore( MachineBasicBlock::iterator I, int NewOpcode) argument
504 insertCondBranchBefore( MachineBasicBlock::iterator I, int NewOpcode, DebugLoc DL) argument
517 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, DebugLoc DL) argument
528 insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum) argument
[all...]
H A DSIISelLowering.cpp1966 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet); local
1967 MI->setDesc(TII->get(NewOpcode));
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2116 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; local
2127 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
2129 Inst.setOpcode(NewOpcode);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3943 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local
3947 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3955 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local
3959 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);

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