| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 424 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
445 Op0IsKill, Imm, VT.getSimpleVT());
457 ISDOpcode, Op0, Op0IsKill, CF);
472 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
1282 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1299 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1613 bool /*Op0IsKill*/) {
1618 bool /*Op0IsKill*/, unsigned /*Op1*/,
1633 bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1638 bool /*Op0IsKill*/,
1653 fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument
1719 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
1740 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
1764 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
1792 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1814 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument
1839 fastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument
1861 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1887 fastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument
1951 fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument
1965 fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 161 unsigned Op0, bool Op0IsKill, uint64_t imm1,
160 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 116 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill);
123 unsigned Op0, bool Op0IsKill,
2275 unsigned Op0, bool Op0IsKill,
2287 Op0, Op0IsKill, Imm);
2295 unsigned Op0, bool Op0IsKill) {
2300 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2308 unsigned Op0, bool Op0IsKill,
2314 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2273 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
2293 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill) argument
2306 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 110 unsigned Op0, bool Op0IsKill);
113 unsigned Op0, bool Op0IsKill,
117 unsigned Op0, bool Op0IsKill,
122 unsigned Op0, bool Op0IsKill,
126 unsigned Op0, bool Op0IsKill,
288 unsigned Op0, bool Op0IsKill) {
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
300 .addReg(Op0, Op0IsKill * RegState::Kill));
310 unsigned Op0, bool Op0IsKill,
323 .addReg(Op0, Op0IsKill * RegStat
286 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
308 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
336 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
368 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
394 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 193 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
211 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
213 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
215 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
217 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
221 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
225 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1467 emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm) argument
3849 emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3869 emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3879 emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
3889 emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
3915 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
3995 emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4022 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4116 emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4143 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
[all...] |