Searched defs:SchedModel (Results 1 - 15 of 15) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h35 MCSchedModel SchedModel; member in class:llvm::TargetSchedModel
44 TargetSchedModel(): SchedModel(MCSchedModel::GetDefaultSchedModel()), STI(nullptr), TII(nullptr) {}
67 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
82 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
93 return SchedModel.getNumProcResourceKinds();
98 return SchedModel.getProcResource(PIdx);
105 return SchedModel.getProcResource(PIdx)->Name;
140 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
145 return SchedModel
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H A DScheduleDAGInstrs.h85 TargetSchedModel SchedModel; member in class:llvm::ScheduleDAGInstrs
169 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
173 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
174 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
H A DMachineTraceMetrics.h73 TargetSchedModel SchedModel; member in class:llvm::MachineTraceMetrics
111 /// This is an array with SchedModel.getNumProcResourceKinds() entries.
114 /// These numbers have already been scaled by SchedModel.getResourceFactor().
371 // where Kinds = SchedModel.getNumProcResourceKinds().
380 unsigned Factor = SchedModel.getLatencyFactor();
H A DMachineScheduler.h547 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
563 const TargetSchedModel *SchedModel; member in class:llvm::SchedBoundary
633 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
682 return RetiredMOps * SchedModel->getMicroOpFactor();
690 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
821 const TargetSchedModel *SchedModel);
826 const TargetSchedModel *SchedModel; member in class:llvm::GenericSchedulerBase
832 Context(C), SchedModel(nullptr), TRI(nullptr) {}
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp102 assert(Found->Value && "Missing processor SchedModel value");
108 const MCSchedModel SchedModel = getSchedModelForCPU(CPU); local
109 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
/external/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp33 TargetSchedModel SchedModel; member in class:__anon10642::AArch64StorePairSuppress
83 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
122 SchedModel.init(ST.getSchedModel(), &ST, TII);
128 if (!SchedModel.hasInstrSchedModel()) {
H A DAArch64ConditionalCompares.cpp726 MCSchedModel SchedModel; member in class:__anon10627::AArch64ConditionalCompares
848 unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4;
896 SchedModel = MF.getSubtarget().getSchedModel();
/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h111 MCSchedModel SchedModel; ///< Basic machine properties. member in class:llvm::InstrItineraryData
119 InstrItineraryData() : SchedModel(MCSchedModel::GetDefaultSchedModel()),
125 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
126 Itineraries(SchedModel.InstrItineraries) {}
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h47 const TargetSchedModel *SchedModel; member in class:llvm::VLIWResourceModel
58 : SchedModel(SM), TotalPackets(0) {
65 Packet.resize(SchedModel->getIssueWidth());
135 const TargetSchedModel *SchedModel; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary
156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
169 SchedModel = smodel;
192 const TargetSchedModel *SchedModel; member in class:llvm::ConvergingVLIWScheduler
207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
/external/llvm/lib/CodeGen/
H A DMachineCombiner.cpp41 MCSchedModel SchedModel; member in class:__anon10431::MachineCombiner
262 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx);
410 SchedModel = STI.getSchedModel();
411 TSchedModel.init(SchedModel, &STI, TII);
H A DEarlyIfConversion.cpp583 MCSchedModel SchedModel; member in class:__anon10410::EarlyIfConverter
691 unsigned CritLimit = SchedModel.MispredictPenalty/2;
786 SchedModel = STI.getSchedModel();
H A DTargetInstrInfo.cpp769 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel, argument
774 return SchedModel.LoadLatency;
776 return SchedModel.HighLatency;
829 return defaultDefLatency(ItinData->SchedModel, DefMI);
872 defaultDefLatency(ItinData->SchedModel, DefMI));
H A DIfConversion.cpp159 TargetSchedModel SchedModel; member in class:__anon10418::IfConverter
281 SchedModel.init(ST.getSchedModel(), &ST, TII);
686 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
1591 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
H A DMachineScheduler.cpp1619 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { argument
1621 if (!SchedModel->hasInstrSchedModel())
1623 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1627 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1628 * SchedModel->getMicroOpFactor();
1630 PI = SchedModel->getWriteProcResBegin(SC),
1631 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1633 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1643 SchedModel = smodel;
1645 if (SchedModel
2130 initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument
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/external/llvm/lib/Target/ARM/
H A DARMSubtarget.h225 /// SchedModel - Processor specific instruction costs.
226 MCSchedModel SchedModel; member in class:llvm::ARMSubtarget

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