H A D | assembler_mips.cc | 42 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument 44 CHECK_NE(rt, kNoRegister); 48 static_cast<int32_t>(rt) << kRtShift | 55 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument 57 CHECK_NE(rt, kNoRegister); 60 static_cast<int32_t>(rt) << kRtShift | 84 void MipsAssembler::EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm) { argument 85 CHECK_NE(rt, kNoFRegister); 88 static_cast<int32_t>(rt) << kRtShift | 93 void MipsAssembler::EmitBranch(Register rt, Registe argument 163 Add(Register rd, Register rs, Register rt) argument 167 Addu(Register rd, Register rs, Register rt) argument 171 Addi(Register rt, Register rs, uint16_t imm16) argument 175 Addiu(Register rt, Register rs, uint16_t imm16) argument 179 Sub(Register rd, Register rs, Register rt) argument 183 Subu(Register rd, Register rs, Register rt) argument 187 Mult(Register rs, Register rt) argument 191 Multu(Register rs, Register rt) argument 195 Div(Register rs, Register rt) argument 199 Divu(Register rs, Register rt) argument 203 And(Register rd, Register rs, Register rt) argument 207 Andi(Register rt, Register rs, uint16_t imm16) argument 211 Or(Register rd, Register rs, Register rt) argument 215 Ori(Register rt, Register rs, uint16_t imm16) argument 219 Xor(Register rd, Register rs, Register rt) argument 223 Xori(Register rt, Register rs, uint16_t imm16) argument 227 Nor(Register rd, Register rs, Register rt) argument 243 Sllv(Register rd, Register rs, Register rt) argument 247 Srlv(Register rd, Register rs, Register rt) argument 251 Srav(Register rd, Register rs, Register rt) argument 255 Lb(Register rt, Register rs, uint16_t imm16) argument 259 Lh(Register rt, Register rs, uint16_t imm16) argument 263 Lw(Register rt, Register rs, uint16_t imm16) argument 267 Lbu(Register rt, Register rs, uint16_t imm16) argument 271 Lhu(Register rt, Register rs, uint16_t imm16) argument 275 Lui(Register rt, uint16_t imm16) argument 287 Sb(Register rt, Register rs, uint16_t imm16) argument 291 Sh(Register rt, Register rs, uint16_t imm16) argument 295 Sw(Register rt, Register rs, uint16_t imm16) argument 299 Slt(Register rd, Register rs, Register rt) argument 303 Sltu(Register rd, Register rs, Register rt) argument 307 Slti(Register rt, Register rs, uint16_t imm16) argument 311 Sltiu(Register rt, Register rs, uint16_t imm16) argument 315 Beq(Register rt, Register rs, uint16_t imm16) argument 320 Bne(Register rt, Register rs, uint16_t imm16) argument 390 Mfc1(Register rt, FRegister fs) argument 423 Move(Register rt, Register rs) argument 427 Clear(Register rt) argument 431 Not(Register rt, Register rs) argument 435 Mul(Register rd, Register rs, Register rt) argument 440 Div(Register rd, Register rs, Register rt) argument 445 Rem(Register rd, Register rs, Register rt) argument 450 AddConstant(Register rt, Register rs, int32_t value) argument 454 LoadImmediate(Register rt, int32_t value) argument [all...] |
H A D | assembler_mips64.cc | 33 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, argument 36 CHECK_NE(rt, kNoGpuRegister); 40 static_cast<uint32_t>(rt) << kRtShift | 47 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { argument 49 CHECK_NE(rt, kNoGpuRegister); 52 static_cast<uint32_t>(rt) << kRtShift | 94 void Mips64Assembler::Add(GpuRegister rd, GpuRegister rs, GpuRegister rt) { argument 95 EmitR(0, rs, rt, rd, 0, 0x20); 98 void Mips64Assembler::Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { argument 99 EmitI(0x8, rs, rt, imm1 102 Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 106 Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 110 Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 114 Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 118 Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 122 Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 126 Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 130 MultR2(GpuRegister rs, GpuRegister rt) argument 134 MultuR2(GpuRegister rs, GpuRegister rt) argument 138 DivR2(GpuRegister rs, GpuRegister rt) argument 142 DivuR2(GpuRegister rs, GpuRegister rt) argument 146 MulR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 150 DivR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 155 ModR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 160 DivuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 165 ModuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 170 MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 174 DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 178 ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 182 DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 186 ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 190 Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 194 Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 198 Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 202 Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 206 Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 210 And(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 214 Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 218 Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 222 Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 226 Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 230 Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 234 Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 238 Seb(GpuRegister rd, GpuRegister rt) argument 242 Seh(GpuRegister rd, GpuRegister rt) argument 246 Dext(GpuRegister rt, GpuRegister rs, int pos, int size_less_one) argument 252 Sll(GpuRegister rd, GpuRegister rt, int shamt) argument 256 Srl(GpuRegister rd, GpuRegister rt, int shamt) argument 260 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument 264 Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 268 Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 272 Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 276 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument 280 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument 284 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument 288 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument 292 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument 296 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument 300 Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 304 Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 308 Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument 312 Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 316 Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 320 Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 324 Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 328 Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 332 Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 336 Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 340 Lui(GpuRegister rt, uint16_t imm16) argument 365 Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 369 Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 373 Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 377 Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 381 Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 385 Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument 389 Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 393 Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument 397 Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 402 Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 434 Jic(GpuRegister rt, uint16_t imm16) argument 438 Jialc(GpuRegister rt, uint16_t imm16) argument 442 Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 449 Bltzc(GpuRegister rt, uint16_t imm16) argument 454 Bgtzc(GpuRegister rt, uint16_t imm16) argument 459 Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 466 Bgezc(GpuRegister rt, uint16_t imm16) argument 471 Blezc(GpuRegister rt, uint16_t imm16) argument 476 Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 483 Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 490 Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 497 Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument 578 Mfc1(GpuRegister rt, FpuRegister fs) argument 582 Mtc1(GpuRegister rt, FpuRegister fs) argument 586 Dmfc1(GpuRegister rt, FpuRegister fs) argument 590 Dmtc1(GpuRegister rt, FpuRegister fs) argument 744 Addiu32(GpuRegister rt, GpuRegister rs, int32_t value, GpuRegister rtmp) argument 753 Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) argument 875 Bltc(GpuRegister rs, GpuRegister rt, Label* label) argument 880 Bltzc(GpuRegister rt, Label* label) argument 885 Bgtzc(GpuRegister rt, Label* label) argument 890 Bgec(GpuRegister rs, GpuRegister rt, Label* label) argument 895 Bgezc(GpuRegister rt, Label* label) argument 900 Blezc(GpuRegister rt, Label* label) argument 905 Bltuc(GpuRegister rs, GpuRegister rt, Label* label) argument 910 Bgeuc(GpuRegister rs, GpuRegister rt, Label* label) argument 915 Beqc(GpuRegister rs, GpuRegister rt, Label* label) argument 920 Bnec(GpuRegister rs, GpuRegister rt, Label* label) argument [all...] |