Searched defs:wide (Results 1 - 18 of 18) sorted by relevance

/art/compiler/dex/
H A Dreg_location.h45 unsigned wide:1; member in struct:art::RegLocation
H A Dgvn_dead_code_elimination.cc90 void GvnDeadCodeElimination::VRegChains::AddMIRWithDef(MIR* mir, int v_reg, bool wide, argument
96 data->wide_def = wide;
109 if (wide) {
210 void GvnDeadCodeElimination::VRegChains::UpdateInitialVRegValue(int v_reg, bool wide, argument
213 if (!wide) {
217 // Maybe there was a wide value in v_reg before. Do not check for wide value in v_reg-1,
236 // Maybe there was a narrow value before. Do not check for wide value in v_reg-1,
246 // Maybe there was a wide value before.
391 int old_s_reg, int new_s_reg, bool wide) {
390 RenameSRegUses(uint16_t first_change, uint16_t last_change, int old_s_reg, int new_s_reg, bool wide) argument
556 bool wide = (mir_to_kill->ssa_rep->num_defs != 1); local
692 bool wide = data->wide_def; local
845 bool wide = last_data->wide_def; local
1049 bool wide = raw_dest.wide; local
1442 bool wide = (mir->ssa_rep->num_defs == 2); local
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H A Dgvn_dead_code_elimination_test.cc238 int SRegToVReg(int32_t s_reg, bool wide) { argument
241 if (wide) {
247 int SRegToVReg(int32_t* uses, size_t* use, bool wide) { argument
248 int v_reg = SRegToVReg(uses[*use], wide);
249 if (wide) {
414 cu_.mir_graph->reg_location_[sreg].wide = true;
415 cu_.mir_graph->reg_location_[sreg + 1].wide = true;
H A Dtype_inference.h84 static Type ArtMethodType(bool wide) { argument
85 return Type(kFlagLowWord | kFlagRef | (wide ? kFlagWide : kFlagNarrow));
H A Dlocal_value_numbering.cc1157 // Determine if this Phi is merging wide regs.
1160 // This is the high part of a wide reg. Ignore the Phi.
1163 bool wide = raw_dest.wide; local
1179 value_name = wide ? lvn->GetOperandValueWide(s_reg) : lvn->GetOperandValue(s_reg);
1193 if (!wide && gvn_->NullCheckedInAllPredecessors(merge_names_)) {
1201 if (wide) {
1664 // 1 wide result, treat as unique each time, use result s_reg - will be unique.
1743 // res = op + 1 wide operand
1755 // wide re
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H A Dmir_optimization.cc277 CompilerTemp* MIRGraph::GetNewCompilerTemp(CompilerTempType ct_type, bool wide) { argument
302 << (wide ? "wide is being requested." : "not wide is being requested.");
313 // and thus even for 64-bit, we allow only a non-wide temp to be requested.
314 DCHECK_EQ(wide, false);
327 size_t needed_temps = wide ? 2u : 1u;
353 if (available_temps <= 0 || (available_temps <= 1 && wide)) {
378 if (wide) {
379 // Only non-special temps are handled as wide fo
415 RemoveLastCompilerTemp(CompilerTempType ct_type, bool wide, CompilerTemp* temp) argument
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H A Dmir_graph.cc410 bool wide = false; local
413 wide = true;
421 wide = true;
429 wide = true;
446 if (dest == monitor_reg || (wide && dest + 1 == monitor_reg)) {
1540 // For invokes-style formats, treat wide regs as a pair of singles.
1557 if (!show_singles && (reg_location_ != nullptr) && reg_location_[i].wide) {
1573 case Instruction::k51l: // Add one wide immediate.
1655 if (!singles_only && reg_location_[ssa_reg].wide &&
1736 * high-word loc for wide argument
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/art/compiler/dex/quick/mips/
H A Dfp_mips.cc108 DCHECK(rl_src1.wide);
110 DCHECK(rl_src2.wide);
112 DCHECK(rl_dest.wide);
113 DCHECK(rl_result.wide);
170 if (rl_src.wide) {
177 if (rl_dest.wide) {
184 // Get the reg storage for a wide FP. Is either a solo or a pair. Base is Mips-counted, e.g., even
210 bool wide = true; local
216 wide = false;
220 wide
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/art/compiler/dex/quick/arm64/
H A Dfp_arm64.cc111 DCHECK(rl_src1.wide);
113 DCHECK(rl_src2.wide);
115 DCHECK(rl_dest.wide);
116 DCHECK(rl_result.wide);
139 DCHECK(rl_src1.wide);
141 DCHECK(rl_dest.wide);
142 DCHECK(rl_result.wide);
213 if (rl_src.wide) {
222 if (rl_dest.wide) {
452 A64Opcode wide local
470 A64Opcode wide = (is_double) ? WIDE(0) : UNWIDE(0); local
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H A Dutility_arm64.cc228 // 2. If the value is two bits wide, it can be encoded.
565 A64Opcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); local
591 return NewLIR2(kA64Rev2rr | wide, r_dest_src1.GetReg(), r_src2.GetReg());
594 NewLIR2(kA64Rev162rr | wide, r_dest_src1.GetReg(), r_src2.GetReg());
596 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_dest_src1.GetReg(), 0, 15);
601 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 7);
605 return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15);
610 return NewLIR4(kA64Ubfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15);
618 return NewLIR2(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg());
622 return NewLIR3(opcode | wide, r_dest_src
632 A64Opcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); local
817 A64Opcode wide = (is_wide) ? WIDE(0) : UNWIDE(0); local
940 A64Opcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); local
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H A Dint_arm64.cc215 bool is_wide = rl_dest.ref || rl_dest.wide;
275 A64Opcode wide = reg.Is64Bit() ? WIDE(0) : UNWIDE(0); local
276 branch = NewLIR2(opcode | wide, reg.GetReg(), 0);
281 A64Opcode wide = reg.Is64Bit() ? WIDE(0) : UNWIDE(0); local
282 branch = NewLIR2(opcode | wide, reg.GetReg(), 0);
285 A64Opcode wide = reg.Is64Bit() ? WIDE(0) : UNWIDE(0); local
287 branch = NewLIR3(opcode | wide, reg.GetReg(), value, 0);
538 const bool is_64bit = rl_dest.wide;
647 A64Opcode wide; local
650 wide
787 A64Opcode wide = UNWIDE(0); local
950 OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest, bool wide) argument
1784 A64Opcode wide = IsWide(size) ? WIDE(0) : UNWIDE(0); local
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/art/compiler/dex/quick/
H A Dmir_to_lir-inl.h274 inline void Mir2Lir::CheckRegStorage(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp) argument
277 CheckRegStorageImpl(rs, wide, ref, fp, kFailOnSizeError, kReportSizeError);
H A Dmir_to_lir.cc115 RegStorage Mir2Lir::LoadArg(size_t in_position, RegisterClass reg_class, bool wide) { argument
138 if (reg_arg.Valid() && wide && (reg_arg.GetWideKind() == kNotWide)) {
139 // For wide register we've got only half of it.
146 reg_arg = wide ? AllocTypedTempWide(false, reg_class) : AllocTypedTemp(false, reg_class);
147 LoadBaseDisp(TargetPtrReg(kSp), offset, reg_arg, wide ? k64 : k32, kNotVolatile);
151 if (wide) {
188 if (reg_arg.Valid() && rl_dest.wide && (reg_arg.GetWideKind() == kNotWide)) {
189 // For wide register we've got only half of it.
196 OpSize op_size = rl_dest.wide ? k64 : (rl_dest.ref ? kReference : k32);
199 if (rl_dest.wide) {
376 bool wide = (data.is_wide != 0u); local
1364 CheckRegStorageImpl(RegStorage rs, WidenessCheck wide, RefCheck ref, FPCheck fp, bool fail, bool report) const argument
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H A Dralloc_util.cc133 // Existence of core64 registers implies wide references.
347 // If it's wide, split it up.
349 // If the pair was associated with a wide value, unmark the partner as well.
471 RegStorage Mir2Lir::AllocLiveReg(int s_reg, int reg_class, bool wide) { argument
478 reg = FindLiveReg(wide ? reg_pool_->dp_regs_ : reg_pool_->sp_regs_, s_reg);
482 reg = FindLiveReg(wide || reg_class == kRefReg ? reg_pool_->core64_regs_ :
489 if (wide && !reg.IsFloat() && !cu_->target64) {
500 if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) {
524 if (wide) {
549 DCHECK(rl_keep.wide);
1412 bool wide = fp_regs[i].s_reg & STARTING_WIDE_SREG; local
1451 bool wide = curr->wide || (cu_->target64 && curr->ref); local
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/art/compiler/linker/arm64/
H A Drelative_patcher_arm64.cc161 bool wide = (insn & 0x40000000) != 0; local
162 uint32_t shift = wide ? 3u : 2u;
/art/compiler/dex/quick/arm/
H A Dint_arm.cc1116 bool wide) {
1117 DCHECK(!wide) << "Unsupported";
1387 if (rl_dest.wide) {
1411 if (rl_dest.wide || rl_dest.fp || constant_index) {
1435 if (rl_dest.wide) {
1511 if (rl_src.wide || rl_src.fp || constant_index) {
1512 if (rl_src.wide) {
1115 OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest, bool wide) argument
/art/compiler/dex/quick/x86/
H A Dint_x86.cc1429 bool wide) {
1431 LIR* mov = NewLIR3(wide ? kX86Mov64RM : kX86Mov32RM, r_dest.GetReg(), kRIPReg,
1439 CHECK(!wide) << "Unsupported";
2336 DCHECK(rl_src2.wide);
1428 OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest, bool wide) argument
/art/compiler/utils/x86_64/
H A Dassembler_x86_64.cc2177 void X86_64Assembler::EmitGenericShift(bool wide, argument
2183 if (wide) {
2199 void X86_64Assembler::EmitGenericShift(bool wide, argument
2205 if (wide) {

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