Searched refs:reg (Results 251 - 275 of 1023) sorted by relevance

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/external/v8/src/mips/
H A Dregexp-macro-assembler-mips.h24 virtual void AdvanceRegister(int reg, int by);
65 virtual void IfRegisterGE(int reg, int comparand, Label* if_ge);
66 virtual void IfRegisterLT(int reg, int comparand, Label* if_lt);
67 virtual void IfRegisterEqPos(int reg, Label* if_eq);
79 virtual void ReadCurrentPositionFromRegister(int reg);
80 virtual void ReadStackPointerFromRegister(int reg);
84 virtual void WriteCurrentPositionToRegister(int reg, int cp_offset);
86 virtual void WriteStackPointerToRegister(int reg);
/external/v8/src/mips64/
H A Dregexp-macro-assembler-mips64.h24 virtual void AdvanceRegister(int reg, int by);
65 virtual void IfRegisterGE(int reg, int comparand, Label* if_ge);
66 virtual void IfRegisterLT(int reg, int comparand, Label* if_lt);
67 virtual void IfRegisterEqPos(int reg, Label* if_eq);
79 virtual void ReadCurrentPositionFromRegister(int reg);
80 virtual void ReadStackPointerFromRegister(int reg);
84 virtual void WriteCurrentPositionToRegister(int reg, int cp_offset);
86 virtual void WriteStackPointerToRegister(int reg);
H A Ddebug-mips64.cc129 Register reg = { r }; local
131 __ push(reg);
134 __ PushRegisterAsTwoSmis(reg);
150 Register reg = { r }; local
152 __ PopRegisterAsTwoSmis(reg, at);
155 __ pop(reg);
159 __ li(reg, kDebugZapValue);
/external/v8/src/
H A Dregexp-macro-assembler.h53 virtual void AdvanceRegister(int reg, int by) = 0; // r[reg] += by.
117 virtual void IfRegisterGE(int reg, int comparand, Label* if_ge) = 0;
120 virtual void IfRegisterLT(int reg, int comparand, Label* if_lt) = 0;
123 virtual void IfRegisterEqPos(int reg, Label* if_eq) = 0;
137 virtual void ReadCurrentPositionFromRegister(int reg) = 0;
138 virtual void ReadStackPointerFromRegister(int reg) = 0;
143 virtual void WriteCurrentPositionToRegister(int reg, int cp_offset) = 0;
145 virtual void WriteStackPointerToRegister(int reg) = 0;
H A Dregexp-macro-assembler-irregexp.h47 virtual void AdvanceRegister(int reg, int by); // r[reg] += by.
50 virtual void WriteCurrentPositionToRegister(int reg, int cp_offset);
52 virtual void ReadCurrentPositionFromRegister(int reg);
53 virtual void WriteStackPointerToRegister(int reg);
54 virtual void ReadStackPointerFromRegister(int reg);
/external/v8/src/x64/
H A Ddebug-x64.cc94 Register reg = { r }; local
95 DCHECK(!reg.is(kScratchRegister));
97 __ Push(reg);
100 __ PushRegisterAsTwoSmis(reg);
116 Register reg = { r }; local
118 __ Set(reg, kDebugZapValue);
121 __ Pop(reg);
125 __ PopRegisterAsTwoSmis(reg);
/external/v8/src/x87/
H A Dregexp-macro-assembler-x87.h22 virtual void AdvanceRegister(int reg, int by);
62 virtual void IfRegisterGE(int reg, int comparand, Label* if_ge);
63 virtual void IfRegisterLT(int reg, int comparand, Label* if_lt);
64 virtual void IfRegisterEqPos(int reg, Label* if_eq);
76 virtual void ReadCurrentPositionFromRegister(int reg);
77 virtual void ReadStackPointerFromRegister(int reg);
81 virtual void WriteCurrentPositionToRegister(int reg, int cp_offset);
83 virtual void WriteStackPointerToRegister(int reg);
/external/valgrind/VEX/priv/
H A Dguest_generic_x87.h82 UChar reg[80]; member in struct:__anon14973
102 UChar reg[80]; member in struct:__anon14974
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dr500_fragprog.c183 static int r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) argument
194 if (reg.Abs)
197 if (opcode == RC_OPCODE_KIL && (reg.Swizzle != RC_SWIZZLE_XYZW || reg.Negate != RC_MASK_NONE))
201 unsigned int swz = GET_SWZ(reg.Swizzle, i);
203 reg.Negate &= ~(1 << i);
210 if (reg.Negate)
217 if (reg.Swizzle == RC_SWIZZLE_XYZW && !reg.Abs && !reg
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H A Dradeon_pair_regalloc.c165 struct register_info * reg; local
172 reg = &s->Input[index];
178 reg->Live[i].Used = 1;
179 reg->Live[i].Start = 0;
180 reg->Live[i].End =
189 const struct register_info * reg; local
192 reg = &s->Temporary[*index];
194 reg = &s->Input[*index];
198 if (reg->Allocated) {
199 *index = reg
408 reg_get_index(int reg) argument
413 reg_get_writemask(int reg) argument
428 print_reg(int reg) argument
691 int reg = ra_get_node_reg(graph, node_index); local
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/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DSCCP.java111 * @param reg SSA register
112 * @param latticeValue new lattice value for @param reg.
114 private void addUsersToWorklist(int reg, int latticeValue) { argument
116 for (SsaInsn insn : ssaMeth.getUseListForRegister(reg)) {
120 for (SsaInsn insn : ssaMeth.getUseListForRegister(reg)) {
128 * @param reg SSA register
133 private boolean setLatticeValueTo(int reg, int value, Constant cst) { argument
135 if (latticeValues[reg] != value) {
136 latticeValues[reg] = value;
141 if (latticeValues[reg] !
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H A DSsaMethod.java405 * @param reg register in question
406 * @return insn (actual instance from code) that defined this reg or null
407 * if reg is not defined.
409 public SsaInsn getDefinitionForRegister(int reg) { argument
415 return definitionList[reg];
435 return definitionList[reg];
499 int reg = oldSource.getReg();
500 useList[reg].remove(insn);
503 int reg = newSource.getReg();
504 if (useList.length <= reg) {
638 getUseListForRegister(int reg) argument
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/external/llvm/lib/Target/R600/
H A DAMDGPUAsmPrinter.cpp262 unsigned reg = MO.getReg(); local
263 if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
264 reg == AMDGPU::VCC_HI) {
267 } else if (reg == AMDGPU::FLAT_SCR ||
268 reg == AMDGPU::FLAT_SCR_LO ||
269 reg == AMDGPU::FLAT_SCR_HI) {
274 switch (reg) {
282 if (AMDGPU::SReg_32RegClass.contains(reg)) {
285 } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
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/external/mesa3d/src/mesa/drivers/dri/i915/
H A Di915_debug_fp.c165 print_reg_neg_swizzle(GLuint reg) argument
169 if ((reg & REG_SWIZZLE_MASK) == REG_SWIZZLE_XYZW &&
170 (reg & REG_NEGATE_MASK) == 0)
176 if (reg & (1 << ((i * 4) + 3)))
179 switch ((reg >> (i * 4)) & 0x7) {
/external/chromium-trace/trace-viewer/third_party/Paste/paste/
H A Dregistry.py373 reg = environ.setdefault('paste.registry', Registry())
374 reg.prepare()
376 return self.streaming_iter(reg, environ, start_response)
394 reg.cleanup()
400 reg.cleanup()
403 reg.cleanup()
407 def streaming_iter(self, reg, environ, start_response):
425 reg.cleanup()
431 reg.cleanup()
434 reg
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/external/libunwind/src/x86/
H A DGos-freebsd.c142 x86_get_scratch_loc (struct cursor *c, unw_regnum_t reg) argument
151 return DWARF_REG_LOC (&c->dwarf, reg);
178 switch (reg)
243 off = FREEBSD_UC_MCONTEXT_ST0_OFF + 10*(reg - UNW_X86_ST0);
244 xmm_off = FREEBSD_UC_MCONTEXT_ST0_XMM_OFF + 10*(reg - UNW_X86_ST0);
258 xmm_off = FREEBSD_UC_MCONTEXT_XMM0_OFF + 8*(reg - UNW_X86_XMM0_lo);
270 xmm_off = FREEBSD_UC_MCONTEXT_XMM0_OFF + 16*(reg - UNW_X86_XMM0);
277 return DWARF_REG_LOC (&c->dwarf, reg);
304 x86_r_uc_addr (ucontext_t *uc, int reg) argument
308 switch (reg)
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H A DGos-linux.c141 x86_get_scratch_loc (struct cursor *c, unw_regnum_t reg) argument
149 return DWARF_REG_LOC (&c->dwarf, reg);
162 switch (reg)
199 off = LINUX_FPSTATE_ST0_OFF + 10*(reg - UNW_X86_ST0);
212 off = LINUX_FPSTATE_XMM0_OFF + 8*(reg - UNW_X86_XMM0_lo);
223 off = LINUX_FPSTATE_XMM0_OFF + 16*(reg - UNW_X86_XMM0);
230 return DWARF_REG_LOC (&c->dwarf, reg);
252 x86_r_uc_addr (ucontext_t *uc, int reg) argument
256 switch (reg)
/external/v8/src/compiler/
H A Dinstruction-selector-impl.h33 InstructionOperand* DefineAsFixed(Node* node, Register reg) { argument
36 Register::ToAllocationIndex(reg)));
39 InstructionOperand* DefineAsFixed(Node* node, DoubleRegister reg) { argument
42 DoubleRegister::ToAllocationIndex(reg)));
81 InstructionOperand* UseFixed(Node* node, Register reg) { argument
84 Register::ToAllocationIndex(reg)));
87 InstructionOperand* UseFixed(Node* node, DoubleRegister reg) { argument
90 DoubleRegister::ToAllocationIndex(reg)));
120 InstructionOperand* TempRegister(Register reg) { argument
122 Register::ToAllocationIndex(reg));
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/external/v8/src/ia32/
H A Dassembler-ia32.h76 static inline int ToAllocationIndex(Register reg);
87 bool is(Register reg) const { return code_ == reg.code_; }
132 inline int Register::ToAllocationIndex(Register reg) {
133 DCHECK(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg
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/external/mesa3d/src/gallium/auxiliary/rtasm/
H A Drtasm_x86sse.c43 void x86_print_reg( struct x86_reg reg )
45 if (reg.mod != mod_REG)
48 switch( reg.file ) {
50 switch( reg.idx ) {
62 debug_printf( "MMX%u", reg.idx );
65 debug_printf( "XMM%u", reg.idx );
68 debug_printf( "fp%u", reg.idx );
72 if (reg.mod == mod_DISP8 ||
73 reg.mod == mod_DISP32)
74 debug_printf("+%d", reg
227 emit_modrm( struct x86_function *p, struct x86_reg reg, struct x86_reg regmem ) argument
319 struct x86_reg reg; local
329 x86_make_disp( struct x86_reg reg, int disp ) argument
446 x86_call( struct x86_function *p, struct x86_reg reg) argument
841 x86_shr_imm( struct x86_function *p, struct x86_reg reg, unsigned imm ) argument
857 x86_sar_imm( struct x86_function *p, struct x86_reg reg, unsigned imm ) argument
873 x86_shl_imm( struct x86_function *p, struct x86_reg reg, unsigned imm ) argument
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/external/valgrind/none/tests/arm64/
H A Dmemory.stdout.exp23 LDR (literal, int reg)
128 0 x5 (sub, base reg)
129 0 x6 (sub, index reg)
158 0 x5 (sub, base reg)
159 0 x6 (sub, index reg)
188 0 x5 (sub, base reg)
189 0 x6 (sub, index reg)
218 0 x5 (sub, base reg)
219 0 x6 (sub, index reg)
248 0 x5 (sub, base reg)
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_vec4_emit.cpp63 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
65 struct brw_reg reg = brw_vec8_grf(grf, 0); local
66 reg.dw1.bits.writemask = inst->dst.writemask;
69 inst->dst.fixed_hw_reg = reg;
76 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
78 struct brw_reg reg = brw_vec8_grf(grf, 0); local
79 reg.dw1.bits.swizzle = inst->src[i].swizzle;
80 reg.type = inst->src[i].type;
82 reg = brw_abs(reg);
110 setup_uniforms(int reg) argument
141 int reg = 0; local
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H A Dbrw_curbe.c103 GLuint reg = 0; local
107 reg = 0;
108 brw->curbe.wm_start = reg;
109 brw->curbe.wm_size = nr_fp_regs; reg += nr_fp_regs;
110 brw->curbe.clip_start = reg;
111 brw->curbe.clip_size = nr_clip_regs; reg += nr_clip_regs;
112 brw->curbe.vs_start = reg;
113 brw->curbe.vs_size = nr_vp_regs; reg += nr_vp_regs;
114 brw->curbe.total_size = reg;
/external/mesa3d/src/mesa/program/
H A Dregister_allocate.c129 unsigned int reg; member in struct:ra_node
160 * mem_ctx is a ralloc context for the allocator. The reg set may be freed
210 * Adds a conflict between base_reg and reg, and also between reg and
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
321 g->nodes[i].reg = NO_REG;
381 if (g->nodes[i].in_stack || g->nodes[i].reg != NO_REG)
418 /* Find the lowest-numbered reg whic
218 ra_add_transitive_reg_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg) argument
497 ra_set_node_reg(struct ra_graph *g, unsigned int n, unsigned int reg) argument
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/external/lldb/source/Plugins/Process/Utility/
H A DRegisterContextDarwin_arm.cpp196 #define DBG_OFFSET(reg) ((LLVM_EXTENSION offsetof (RegisterContextDarwin_arm::DBG, reg) + sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU) + sizeof (RegisterContextDarwin_arm::EXC)))
198 #define DEFINE_DBG(reg, i) #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *)NULL)->reg[i]), DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, dbg_##reg##i }, NULL, NULL
419 RegisterContextDarwin_arm::GetRegisterInfoAtIndex (size_t reg) argument
422 if (reg < k_num_registers)
423 return &g_register_infos[reg];
479 GetSetForNativeRegNum(int reg) argument
639 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local
732 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; local
867 ConvertRegisterKindToRegisterNumber(uint32_t kind, uint32_t reg) argument
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