| /art/runtime/arch/arm64/ |
| H A D | registers_arm64.cc | 57 if (rhs >= D0 && rhs < kNumberOfDRegisters) {
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| H A D | registers_arm64.h | 115 D0 = 0, enumerator in enum:art::arm64::DRegister
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| H A D | context_arm64.cc | 96 fprs_[D0] = nullptr;
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| H A D | quick_method_frame_info_arm64.h | 52 (1 << art::arm64::D0) | (1 << art::arm64::D1) | (1 << art::arm64::D2) |
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| /art/compiler/utils/arm/ |
| H A D | managed_register_arm_test.cc | 126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0);
133 EXPECT_EQ(D0, reg.AsDRegister());
295 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromDRegister(D0)));
303 EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromDRegister(D0)));
311 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromDRegister(D0)));
321 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromDRegister(D0)));
332 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromDRegister(D0)));
342 EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::FromDRegister(D0)));
352 EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::FromDRegister(D0)));
356 ArmManagedRegister reg_D0 = ArmManagedRegister::FromDRegister(D0);
[all...] |
| H A D | constants_arm.h | 61 D0 = 0, enumerator in enum:art::arm::DRegister
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| H A D | assembler_arm32.cc | 354 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
381 dd, D0, D0);
466 EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
476 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
485 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
545 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
555 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
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| H A D | assembler_thumb2.cc | 469 dd, D0, D0);
482 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
564 EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
574 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
583 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
643 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
653 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
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| H A D | assembler_arm.cc | 59 if (rhs >= D0 && rhs < kNumberOfDRegisters) {
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| /art/compiler/utils/mips/ |
| H A D | constants_mips.h | 32 D0 = 0, enumerator in enum:art::mips::DRegister
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| H A D | assembler_mips.cc | 29 if (rhs >= D0 && rhs < kNumberOfDRegisters) {
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| /art/compiler/utils/arm64/ |
| H A D | managed_register_arm64_test.cc | 168 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0);
176 EXPECT_EQ(D0, reg.AsDRegister());
178 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D0)));
220 Arm64ManagedRegister dreg = Arm64ManagedRegister::FromDRegister(D0);
228 EXPECT_EQ(D0, reg.AsOverlappingDRegister());
275 EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromDRegister(D0)));
284 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromDRegister(D0)));
291 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromDRegister(D0)));
300 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromDRegister(D0)));
307 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromDRegister(D0)));
[all...] |
| /art/compiler/jni/quick/arm/ |
| H A D | calling_convention_arm.cc | 39 D0, D1, D2, D3, D4, D5, D6, D7
71 return ArmManagedRegister::FromDRegister(D0);
146 uint32_t fpr_double_index = 0; // D0 ~ D7.
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| /art/compiler/jni/quick/arm64/ |
| H A D | calling_convention_arm64.cc | 34 D0, D1, D2, D3, D4, D5, D6, D7
58 return Arm64ManagedRegister::FromDRegister(D0);
113 int fp_reg_index = 0; // D0/S0.
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| /art/compiler/jni/quick/mips/ |
| H A D | calling_convention_mips.cc | 39 return MipsManagedRegister::FromDRegister(D0);
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| /art/compiler/utils/ |
| H A D | assembler_thumb_test.cc | 952 __ vaddd(D0, D1, D2);
953 __ vsubd(D0, D1, D2);
954 __ vmuld(D0, D1, D2);
955 __ vmlad(D0, D1, D2);
956 __ vmlsd(D0, D1, D2);
957 __ vdivd(D0, D1, D2);
958 __ vabsd(D0, D1);
959 __ vnegd(D0, D1);
960 __ vsqrtd(D0, D1);
1000 __ vcmpd(D0, D
[all...] |
| /art/compiler/optimizing/ |
| H A D | code_generator_arm.h | 66 return DCHECK_CONSTEXPR(reg % 2 == 0, , D0)
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