| /art/compiler/trampolines/ |
| H A D | trampoline_compiler.cc | 38 __ LoadFromOffset(kLoadWord, PC, R0, offset.Int32Value());
41 __ LoadFromOffset(kLoadWord, IP, R0, JNIEnvExt::SelfOffset().Int32Value());
42 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value());
45 __ LoadFromOffset(kLoadWord, PC, R9, offset.Int32Value());
102 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value());
105 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset().Int32Value());
106 __ LoadFromOffset(kLoadWord, T9, T9, offset.Int32Value());
109 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value());
131 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value());
134 __ LoadFromOffset(kLoadDoublewor
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| /art/compiler/utils/arm/ |
| H A D | assembler_arm.cc | 520 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
527 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value());
535 LoadFromOffset(kLoadWord, dst.AsCoreRegister(),
545 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), SP, src.Int32Value());
552 LoadFromOffset(kLoadWord, dst.AsCoreRegister(),
579 assembler->LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset);
582 assembler->LoadFromOffset(kLoadWord, dst.AsRegisterPairLow(), src_register, src_offset);
583 assembler->LoadFromOffset(kLoadWord, dst.AsRegisterPairHigh(), src_register, src_offset + 4);
603 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value());
611 LoadFromOffset(kLoadWor
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| H A D | assembler_arm32.h | 250 void LoadFromOffset(LoadOperandType type,
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| H A D | assembler_thumb2.h | 289 void LoadFromOffset(LoadOperandType type,
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| H A D | assembler_arm.h | 585 virtual void LoadFromOffset(LoadOperandType type,
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| H A D | assembler_arm32.cc | 1435 void Arm32Assembler::LoadFromOffset(LoadOperandType type, function in class:art::arm::Arm32Assembler
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| H A D | assembler_thumb2.cc | 2541 void Thumb2Assembler::LoadFromOffset(LoadOperandType type, function in class:art::arm::Thumb2Assembler
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 465 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset);
468 LoadFromOffset(kLoadWord, dst.AsRegisterPairLow(), src_register, src_offset);
469 LoadFromOffset(kLoadWord, dst.AsRegisterPairHigh(), src_register, src_offset + 4);
478 void MipsAssembler::LoadFromOffset(LoadOperandType type, Register reg, Register base, function in class:art::mips::MipsAssembler
584 LoadFromOffset(kLoadWord, reg, SP, stack_offset);
588 LoadFromOffset(kLoadWord, RA, SP, stack_offset);
681 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value());
696 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value());
703 LoadFromOffset(kLoadWord, dest.AsCoreRegister(),
714 LoadFromOffset(kLoadWor
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| H A D | assembler_mips.h | 140 void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset);
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips64.cc | 459 __ LoadFromOffset(load_type,
463 __ LoadFromOffset(load_type,
486 __ LoadFromOffset(kLoadWord,
634 __ LoadFromOffset(load_type,
709 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
712 __ LoadFromOffset(kLoadDoubleword, TMP, SP, source.GetStackIndex());
758 __ LoadFromOffset(load_type, TMP, SP, mem_loc.GetStackIndex());
863 __ LoadFromOffset(kLoadDoubleword,
928 __ LoadFromOffset(kLoadDoubleword, GpuRegister(reg_id), SP, stack_index);
960 __ LoadFromOffset(kLoadDoublewor
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| H A D | code_generator_arm.cc | 363 __ LoadFromOffset(kLoadWord, static_cast<Register>(reg_id), SP, stack_index);
537 __ LoadFromOffset(kLoadWord, IP, IP, 0);
721 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), SP, source.GetStackIndex());
739 __ LoadFromOffset(kLoadWord, IP, SP, source.GetStackIndex());
763 __ LoadFromOffset(kLoadWordPair, destination.AsRegisterPairLow<Register>(),
891 __ LoadFromOffset(kLoadWord, LR, TR, entry_point_offset);
1258 __ LoadFromOffset(kLoadWord, reg, SP, kCurrentMethodStackOffset);
1322 __ LoadFromOffset(kLoadWord, temp, SP, receiver.GetStackIndex());
1323 __ LoadFromOffset(kLoadWord, temp, temp, class_offset);
1325 __ LoadFromOffset(kLoadWor
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| H A D | intrinsics_arm.cc | 475 __ LoadFromOffset(kLoadWord,
847 __ LoadFromOffset(
893 __ LoadFromOffset(kLoadWord, LR, TR,
963 __ LoadFromOffset(
984 __ LoadFromOffset(
1009 __ LoadFromOffset(kLoadWord,
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 935 void Mips64Assembler::LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, function in class:art::mips64::Mips64Assembler
997 LoadFromOffset(kLoadWord, dst.AsGpuRegister(), src_register, src_offset);
1000 LoadFromOffset(kLoadDoubleword, dst.AsGpuRegister(), src_register, src_offset);
1123 LoadFromOffset(kLoadDoubleword, reg, SP, stack_offset);
1127 LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset);
1226 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value());
1241 LoadFromOffset(kLoadUnsignedWord, dest.AsGpuRegister(), SP, src.Int32Value());
1248 LoadFromOffset(kLoadUnsignedWord, dest.AsGpuRegister(),
1263 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(),
1271 LoadFromOffset(kLoadDoublewor
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| H A D | assembler_mips64.h | 218 void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
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| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 194 LoadFromOffset(scratch.AsXRegister(), SP, in_off.Int32Value());
243 void Arm64Assembler::LoadFromOffset(XRegister dest, XRegister base, function in class:art::arm64::Arm64Assembler
322 LoadFromOffset(dst.AsXRegister(), ETR, offs.Int32Value());
360 LoadFromOffset(scratch.AsXRegister(), ETR, tr_offs.Int32Value());
369 LoadFromOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
392 LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value());
411 LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), src_offset.Int32Value());
430 LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value());
465 LoadFromOffset(scratch.AsXRegister(), src.AsXRegister(), src_offset.Int32Value());
518 LoadFromOffset(scratc
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| H A D | assembler_arm64.h | 226 void LoadFromOffset(XRegister dest, XRegister base, int32_t offset);
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| /art/compiler/linker/arm/ |
| H A D | relative_patcher_thumb2.cc | 81 assembler.LoadFromOffset(
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