Searched refs:PC (Results 1 - 13 of 13) sorted by relevance

/art/runtime/arch/arm/
H A Dregisters_arm.cc29 if (rhs >= R0 && rhs <= PC) {
H A Dregisters_arm.h48 PC = 15, enumerator in enum:art::arm::Register
H A Dcontext_arm.cc32 gprs_[PC] = &pc_;
35 pc_ = ArmContext::kBadGprBase + PC;
H A Dcontext_arm.h45 SetGPR(PC, new_pc);
H A Dquick_entrypoints_arm.S447 ldr r2, [r0, #60] @ r2 = r15 (PC from gprs_ 60=4*15)
/art/compiler/trampolines/
H A Dtrampoline_compiler.cc38 __ LoadFromOffset(kLoadWord, PC, R0, offset.Int32Value());
42 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value());
45 __ LoadFromOffset(kLoadWord, PC, R9, offset.Int32Value());
/art/compiler/utils/arm/
H A Dassembler_arm32.cc124 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker.
130 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker.
569 EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0));
622 if (!ad.IsImmediate() && ad.GetRegisterOffset() == PC) {
623 // PC relative LDR(literal)
735 CHECK_NE(rd, PC);
736 CHECK_NE(rm, PC);
877 CHECK_NE(rt, PC);
892 CHECK_NE(rt, PC);
909 CHECK_NE(rt, PC);
1002 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local
1029 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local
[all...]
H A Dassembler_thumb2.cc121 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker.
127 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker.
673 EmitDataProcessing(AL, TST, 1, PC, R0, ShifterOperand(0));
816 case TST: thumb_opcode = 0U /* 0b0000 */; set_cc = true; rd = PC; break;
817 case TEQ: thumb_opcode = 4U /* 0b0100 */; set_cc = true; rd = PC; break;
818 case CMP: thumb_opcode = 13U /* 0b1101 */; set_cc = true; rd = PC; break;
819 case CMN: thumb_opcode = 8U /* 0b1000 */; set_cc = true; rd = PC; break;
821 case MOV: thumb_opcode = 2U /* 0b0010 */; rn = PC; break;
823 case MVN: thumb_opcode = 3U /* 0b0011 */; rn = PC; break;
1331 offset -= 4; // Account for PC offse
1934 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local
1961 CHECK_NE(static_cast<Register>(addr.encodingArm() & (0xf << kRnShift)), PC); local
[all...]
H A Dassembler_arm.h192 CHECK_NE(rm, PC);
198 CHECK_NE(rm, PC);
203 rn_(PC), rm_(R0), offset_(offset),
H A Dassembler_arm.cc39 if (rhs >= R0 && rhs <= PC) {
443 // Compute callee saves to pop and PC.
444 RegList core_spill_mask = 1 << PC;
465 // Pop callee saves and PC.
/art/compiler/linker/arm/
H A Drelative_patcher_thumb2.cc38 displacement -= kPcDisplacement; // The base PC is at the end of the 4-byte patch.
63 uint32_t pc_base = patch_offset + (pc_literal_offset - literal_offset) + 4u /* PC adjustment */;
82 arm::kLoadWord, arm::PC, arm::R0,
/art/disassembler/
H A Ddisassembler_arm.cc1355 if (Rt.r == PC && is_load && !is_word) {
1361 } else if (Rn.r == PC || U != 0u) {
1364 if (Rn.r == PC && is_half) {
1382 bool unpred = (Rt.r == SP && !is_word) || (Rt.r == PC && !is_load);
1383 if (Rn.r == PC && !is_load) {
1386 } else if (Rn.r == PC || U != 0u) {
1387 // Load/store with imm12 (load literal if Rn.r == PC; there's no store literal).
1393 } else if (Rn.r == PC) {
1408 unpred = unpred || (Rm.rm.r == SP) || (Rm.rm.r == PC);
/art/compiler/optimizing/
H A Dcode_generator_arm.cc48 { R5, R6, R7, R8, R10, R11, PC };
206 // The dex PC of `at_`.
395 // Save the PC register to mimic Quick.
396 AddAllocatedRegister(Location::RegisterLocation(PC));
454 // Stack register, LR and PC are always reserved.
457 blocked_core_registers_[PC] = true;
499 // instruction to restore just the PC, so this actually helps both baseline
541 // PC is in the list of callee-save to mimic Quick, but we need to push
543 uint32_t push_mask = (core_spill_mask_ & (~(1 << PC))) | 1 << LR;

Completed in 904 milliseconds