/art/test/065-mismatched-implements/src/ |
H A D | Indirect.java | 25 Base base = new Base();
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/art/test/066-mismatched-super/src/ |
H A D | Indirect.java | 25 Base base = new Base();
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/art/runtime/arch/mips/ |
H A D | asm_support_mips.S | 74 from unaligned (mod-4-aligned) mem location disp(base) */ 75 .macro LDu feven,fodd,disp,base,temp 76 l.s \feven, \disp(\base) 77 lw \temp, \disp+4(\base) 82 to unaligned (mod-4-aligned) mem location disp(base) */ 83 .macro SDu feven,fodd,disp,base,temp 85 s.s \feven, \disp(\base) 86 sw \temp, \disp+4(\base) 101 .macro LDu feven,fodd,disp,base,temp 102 l.s \feven, \disp(\base) [all...] |
/art/compiler/utils/ |
H A D | assembler_test.h | 186 std::string base = fmt; local 188 size_t imm_index = base.find(IMM_TOKEN); 193 base.replace(imm_index, ConstexprStrLen(IMM_TOKEN), imm_string); 199 str += base; 353 std::string base = fmt; local 357 if ((reg_index = base.find(REG_TOKEN)) != std::string::npos) { 358 base.replace(reg_index, ConstexprStrLen(REG_TOKEN), reg_string); 364 str += base; 384 std::string base = fmt; local 388 while ((reg1_index = base 426 std::string base = fmt; local 519 std::string base = fmt; local [all...] |
/art/compiler/utils/arm64/ |
H A D | assembler_arm64.cc | 18 #include "base/logging.h" 96 XRegister base, int32_t offset) { 99 ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset)); 102 ___ Strh(reg_w(source), MEM_OP(reg_x(base), offset)); 105 ___ Str(reg_w(source), MEM_OP(reg_x(base), offset)); 112 void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { argument 114 ___ Str(reg_x(source), MEM_OP(reg_x(base), offset)); 117 void Arm64Assembler::StoreSToOffset(SRegister source, XRegister base, int32_t offset) { argument 118 ___ Str(reg_s(source), MEM_OP(reg_x(base), offset)); 121 void Arm64Assembler::StoreDToOffset(DRegister source, XRegister base, int32_ argument 95 StoreWToOffset(StoreOperandType type, WRegister source, XRegister base, int32_t offset) argument 218 LoadWFromOffset(LoadOperandType type, WRegister dest, XRegister base, int32_t offset) argument 243 LoadFromOffset(XRegister dest, XRegister base, int32_t offset) argument 249 LoadSFromOffset(SRegister dest, XRegister base, int32_t offset) argument 254 LoadDFromOffset(DRegister dest, XRegister base, int32_t offset) argument 259 Load(Arm64ManagedRegister dest, XRegister base, int32_t offset, size_t size) argument 299 Arm64ManagedRegister base = m_base.AsArm64(); local 311 Arm64ManagedRegister base = m_base.AsArm64(); local 402 Arm64ManagedRegister base = src_base.AsArm64(); local 421 Arm64ManagedRegister base = m_dest_base.AsArm64(); local 514 Arm64ManagedRegister base = m_base.AsArm64(); local 523 Arm64ManagedRegister base = m_base.AsArm64(); local 534 Call(FrameOffset base, Offset offs, ManagedRegister m_scratch) argument [all...] |
H A D | assembler_arm64.h | 24 #include "base/logging.h" 117 void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs, 119 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE; 172 // Call to address held at [base+offset]. 173 void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE; 174 void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE; 217 XRegister base, int32_t offset); 218 void StoreToOffset(XRegister source, XRegister base, int32_t offset); 219 void StoreSToOffset(SRegister source, XRegister base, int32_t offset); 220 void StoreDToOffset(DRegister source, XRegister base, int32_ [all...] |
/art/test/106-exceptions2/src/ |
H A D | Main.java | 134 Main base = new Main(); 138 base.ifoo = x; 139 return base.noThrow(a,b,c); 143 Main base = new Main(); 150 base.ifoo = x; 151 return base.checkThrow(a,b,c,d,e,f);
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/art/compiler/dex/ |
H A D | local_value_numbering.h | 22 #include "base/arena_object.h" 23 #include "base/logging.h" 172 // Maps instance field "location" (derived from base, field_id and type) to value name. 179 uint16_t base; // Or array. member in struct:art::LocalValueNumbering::EscapedIFieldClobberKey 185 return base == other.base && type == other.type && field_id == other.field_id; 191 // Compare base first. This makes sequential iteration respect the order of base. 192 if (lhs.base != rhs.base) { 209 uint16_t base; member in struct:art::LocalValueNumbering::EscapedArrayClobberKey [all...] |
H A D | global_value_numbering.h | 20 #include "base/arena_object.h" 21 #include "base/logging.h" 22 #include "base/macros.h" 147 uint16_t base; member in struct:art::GlobalValueNumbering::ArrayLocation 153 if (lhs.base != rhs.base) { 154 return lhs.base < rhs.base; 163 uint16_t GetArrayLocation(uint16_t base, uint16_t index); 165 // Get the array base fro [all...] |
/art/test/003-omnibus-opcodes/src/ |
H A D | MethodCall.java | 56 MethodCallBase base = inst; 57 base.tryThing();
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/art/runtime/arch/x86/ |
H A D | thread_x86.cc | 23 #include "base/macros.h" 47 const uintptr_t base = reinterpret_cast<uintptr_t>(this); local 64 entry.base0 = (base & 0x0000ffff); 65 entry.base1 = (base & 0x00ff0000) >> 16; 66 entry.base2 = (base & 0xff000000) >> 24; 100 ldt_entry.base_addr = base;
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/art/runtime/ |
H A D | Android.mk | 26 base/allocator.cc \ 27 base/arena_allocator.cc \ 28 base/bit_vector.cc \ 29 base/hex_dump.cc \ 30 base/logging.cc \ 31 base/mutex.cc \ 32 base/scoped_arena_allocator.cc \ 33 base/scoped_flock.cc \ 34 base/stringpiece.cc \ 35 base/stringprint [all...] |
H A D | monitor_pool.h | 22 #include "base/allocator.h" 28 #include "base/stl_util.h" // STLDeleteElements 126 uintptr_t base = *(monitor_chunks_.LoadRelaxed()+index); local 127 return reinterpret_cast<Monitor*>(base + offset_in_chunk);
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/art/test/072-precise-gc/src/ |
H A D | Main.java | 61 static String generateString(String base, int num) { argument 62 return base + num;
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/art/compiler/utils/mips/ |
H A D | assembler_mips.cc | 19 #include "base/bit_utils.h" 20 #include "base/casts.h" 478 void MipsAssembler::LoadFromOffset(LoadOperandType type, Register reg, Register base, argument 482 Lb(reg, base, offset); 485 Lbu(reg, base, offset); 488 Lh(reg, base, offset); 491 Lhu(reg, base, offset); 494 Lw(reg, base, offset); 504 void MipsAssembler::LoadSFromOffset(FRegister reg, Register base, int32_t offset) { argument 505 Lwc1(reg, base, offse 508 LoadDFromOffset(DRegister reg, Register base, int32_t offset) argument 512 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset) argument 532 StoreFToOffset(FRegister reg, Register base, int32_t offset) argument 536 StoreDToOffset(DRegister reg, Register base, int32_t offset) argument 699 LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, bool poison_reference) argument 710 LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) argument 922 MipsManagedRegister base = mbase.AsMips(); local 932 Call(FrameOffset base, Offset offset, ManagedRegister mscratch) argument [all...] |
H A D | assembler_mips.h | 22 #include "base/macros.h" 140 void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset); 141 void LoadSFromOffset(FRegister reg, Register base, int32_t offset); 142 void LoadDFromOffset(DRegister reg, Register base, int32_t offset); 143 void StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset); 144 void StoreFToOffset(FRegister reg, Register base, int32_t offset); 145 void StoreDToOffset(DRegister reg, Register base, int32_t offset); 194 void LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, 197 void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) OVERRIDE; 261 // Call to address held at [base [all...] |
/art/compiler/optimizing/ |
H A D | common_arm64.h | 148 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, size_t offset = 0) { argument 150 DCHECK(base.IsW()); 151 return vixl::MemOperand(base.X(), offset); 154 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, Offset offset) { argument 155 return HeapOperand(base, offset.SizeValue());
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/art/compiler/ |
H A D | cfi_test.h | 61 const uint8_t* base = actual_asm.data() + (isa == kThumb2 ? 1 : 0); local 62 disasm->Dump(stream, base, base + actual_asm.size());
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/art/runtime/gc/space/ |
H A D | dlmalloc_space.h | 43 // base address is not guaranteed to be granted, if it is required, 152 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size, 154 return CreateMspace(base, morecore_start, initial_size); 156 static void* CreateMspace(void* base, size_t morecore_start, size_t initial_size);
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H A D | rosalloc_space.h | 38 // base address is not guaranteed to be granted, if it is required, 158 void* CreateAllocator(void* base, size_t morecore_start, size_t initial_size, 160 return CreateRosAlloc(base, morecore_start, initial_size, maximum_size, low_memory_mode, 163 static allocator::RosAlloc* CreateRosAlloc(void* base, size_t morecore_start, size_t initial_size,
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/art/compiler/utils/arm/ |
H A D | assembler_arm32.cc | 19 #include "base/bit_utils.h" 20 #include "base/logging.h" 333 Register base, 336 EmitMultiMemOp(cond, am, true, base, regs); 341 Register base, 344 EmitMultiMemOp(cond, am, false, base, regs); 670 Register base, 672 CHECK_NE(base, kNoRegister); 678 (static_cast<int32_t>(base) << kRnShift) | 1437 Register base, 332 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 340 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 667 EmitMultiMemOp(Condition cond, BlockAddressMode am, bool load, Register base, RegList regs) argument 1435 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 1476 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 1494 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument 1512 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 1548 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 1566 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument [all...] |
H A D | assembler_thumb2.cc | 19 #include "base/bit_utils.h" 20 #include "base/logging.h" 410 Register base, 420 ldr(static_cast<Register>(reg), Address(base, kRegisterSize, Address::PostIndex), cond); 422 EmitMultiMemOp(cond, am, true, base, regs); 428 Register base, 439 str(static_cast<Register>(reg), Address(base, -kRegisterSize, strmode), cond); 441 EmitMultiMemOp(cond, am, false, base, regs); 1525 Register base, 1527 CHECK_NE(base, kNoRegiste 409 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 427 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument 1522 EmitMultiMemOp(Condition cond, BlockAddressMode bam, bool load, Register base, RegList regs) argument 2541 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 2582 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 2600 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument 2618 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument 2674 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument 2692 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument [all...] |
/art/compiler/utils/mips64/ |
H A D | assembler_mips64.cc | 19 #include "base/bit_utils.h" 20 #include "base/casts.h" 935 void Mips64Assembler::LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, argument 939 Daddu(AT, AT, base); 940 base = AT; 946 Lb(reg, base, offset); 949 Lbu(reg, base, offset); 952 Lh(reg, base, offset); 955 Lhu(reg, base, offset); 958 Lw(reg, base, offse 969 LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset) argument 1017 StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset) argument 1044 StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset) argument 1244 LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, bool poison_reference) argument 1259 LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) argument 1491 Mips64ManagedRegister base = mbase.AsMips64(); local 1501 Call(FrameOffset base, Offset offset, ManagedRegister mscratch) argument [all...] |
/art/build/ |
H A D | Android.gtest.mk | 97 # For the host, also add the installed tool (in the base size, that should suffice). For the 137 runtime/base/bit_field_test.cc \ 138 runtime/base/bit_utils_test.cc \ 139 runtime/base/bit_vector_test.cc \ 140 runtime/base/hash_set_test.cc \ 141 runtime/base/hex_dump_test.cc \ 142 runtime/base/histogram_test.cc \ 143 runtime/base/mutex_test.cc \ 144 runtime/base/scoped_flock_test.cc \ 145 runtime/base/stringprintf_tes [all...] |
/art/compiler/dex/quick/mips/ |
H A D | fp_mips.cc | 19 #include "base/logging.h" 186 static RegStorage GetWideArgFP(bool fpuIs32Bit, size_t base) { argument 187 // Think about how to make this be able to be computed. E.g., rMIPS_FARG0 + base. Right now 190 switch (base) { 197 switch (base) { 204 LOG(FATAL) << "Unsupported Mips.GetWideFP: " << fpuIs32Bit << " " << base; local
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