Searched refs:reg (Results 1 - 25 of 148) sorted by relevance

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/art/compiler/utils/arm/
H A Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCoreRegister());
34 EXPECT_TRUE(!reg.IsSRegister());
35 EXPECT_TRUE(!reg.IsDRegister());
36 EXPECT_TRUE(!reg
69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); local
126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); local
227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); local
459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local
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/art/compiler/utils/x86/
H A Dmanaged_register_x86_test.cc25 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCpuRegister());
34 EXPECT_TRUE(!reg.IsXmmRegister());
35 EXPECT_TRUE(!reg.IsX87Register());
36 EXPECT_TRUE(!reg
65 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); local
91 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); local
117 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); local
255 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local
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/art/compiler/utils/x86_64/
H A Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_TRUE(!reg.Overlaps(reg));
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local
32 EXPECT_TRUE(!reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsCpuRegister());
34 EXPECT_TRUE(!reg.IsXmmRegister());
35 EXPECT_TRUE(!reg.IsX87Register());
36 EXPECT_TRUE(!reg
65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); local
91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); local
117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); local
255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local
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/art/runtime/arch/arm/
H A Dcontext_arm.h48 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
49 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
50 return gprs_[reg] != nullptr;
53 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
55 return gprs_[reg];
58 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
59 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
60 DCHECK(IsAccessibleGPR(reg));
61 return *gprs_[reg];
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/art/runtime/arch/arm64/
H A Dcontext_arm64.h48 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
49 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters));
50 return gprs_[reg] != nullptr;
53 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters));
55 return gprs_[reg];
58 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
59 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters));
60 DCHECK(IsAccessibleGPR(reg));
61 return *gprs_[reg];
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/art/runtime/arch/mips/
H A Dcontext_mips.h47 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
48 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
49 return gprs_[reg] != nullptr;
52 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
54 return gprs_[reg];
57 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
58 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
59 DCHECK(IsAccessibleGPR(reg));
60 return *gprs_[reg];
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H A Dcontext_mips.cc58 void MipsContext::SetGPR(uint32_t reg, uintptr_t value) { argument
59 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
60 DCHECK(IsAccessibleGPR(reg));
61 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
62 *gprs_[reg] = value;
65 void MipsContext::SetFPR(uint32_t reg, uintptr_t value) { argument
66 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFRegisters));
67 DCHECK(IsAccessibleFPR(reg));
68 CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
69 *fprs_[reg]
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/art/runtime/arch/mips64/
H A Dcontext_mips64.h47 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
48 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
49 return gprs_[reg] != nullptr;
52 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
54 return gprs_[reg];
57 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
58 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
59 DCHECK(IsAccessibleGPR(reg));
60 return *gprs_[reg];
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/art/runtime/arch/x86/
H A Dcontext_x86.h47 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
48 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
49 return gprs_[reg] != nullptr;
52 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
54 return gprs_[reg];
57 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
59 DCHECK(IsAccessibleGPR(reg));
60 return *gprs_[reg];
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/art/runtime/arch/x86_64/
H A Dcontext_x86_64.h47 bool IsAccessibleGPR(uint32_t reg) OVERRIDE {
48 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
49 return gprs_[reg] != nullptr;
52 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE {
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
54 return gprs_[reg];
57 uintptr_t GetGPR(uint32_t reg) OVERRIDE {
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
59 DCHECK(IsAccessibleGPR(reg));
60 return *gprs_[reg];
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H A Dasm_support_x86_64.S80 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size
81 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg
82 #define CFI_RESTORE(reg) .cfi_restore reg
83 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size
89 #define CFI_DEF_CFA(reg,size)
90 #define CFI_DEF_CFA_REGISTER(reg)
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/art/compiler/utils/arm64/
H A Dmanaged_register_arm64_test.cc26 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); local
27 EXPECT_TRUE(reg.IsNoRegister());
28 EXPECT_TRUE(!reg.Overlaps(reg));
33 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); local
35 EXPECT_TRUE(!reg.IsNoRegister());
36 EXPECT_TRUE(reg.IsXRegister());
37 EXPECT_TRUE(!reg.IsWRegister());
38 EXPECT_TRUE(!reg.IsDRegister());
39 EXPECT_TRUE(!reg
106 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); local
168 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); local
219 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); local
375 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); local
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/art/runtime/arch/
H A Dcontext.h54 virtual bool IsAccessibleGPR(uint32_t reg) = 0;
57 virtual uintptr_t* GetGPRAddress(uint32_t reg) = 0;
61 virtual uintptr_t GetGPR(uint32_t reg) = 0;
65 virtual void SetGPR(uint32_t reg, uintptr_t value) = 0;
68 virtual bool IsAccessibleFPR(uint32_t reg) = 0;
72 virtual uintptr_t GetFPR(uint32_t reg) = 0;
76 virtual void SetFPR(uint32_t reg, uintptr_t value) = 0;
/art/compiler/dex/quick/
H A Dgen_loadstore.cc47 OpRegCopy(r_dest, rl_src.reg);
87 OpRegCopyWide(r_dest, rl_src.reg);
113 if (!RegClassMatches(op_kind, rl_src.reg)) {
116 OpRegCopy(new_reg, rl_src.reg);
118 Clobber(rl_src.reg);
119 FreeTemp(rl_src.reg);
121 rl_src.reg = new_reg;
128 rl_src.reg = AllocTypedTemp(rl_src.fp, op_kind);
129 LoadValueDirect(rl_src, rl_src.reg);
153 if (IsLive(rl_src.reg) ||
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H A Dralloc_util.cc83 for (const RegStorage& reg : core_regs) {
84 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
85 m2l_->reginfo_map_[reg.GetReg()] = info;
89 for (const RegStorage& reg : core64_regs) {
90 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
91 m2l_->reginfo_map_[reg.GetReg()] = info;
95 for (const RegStorage& reg : sp_regs) {
96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l
172 Clobber(RegStorage reg) argument
258 RecordCorePromotion(RegStorage reg, int s_reg) argument
290 RecordFpPromotion(RegStorage reg, int s_reg) argument
472 RegStorage reg; local
534 FreeTemp(RegStorage reg) argument
562 IsLive(RegStorage reg) argument
576 IsTemp(RegStorage reg) argument
589 IsPromoted(RegStorage reg) argument
602 IsDirty(RegStorage reg) argument
620 LockTemp(RegStorage reg) argument
636 ResetDef(RegStorage reg) argument
645 NullifyRange(RegStorage reg, int s_reg) argument
726 FlushRegWide(RegStorage reg) argument
746 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); local
754 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); local
759 FlushReg(RegStorage reg) argument
766 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, kWord, kNotVolatile); local
789 RegClassMatches(int reg_class, RegStorage reg) argument
804 RegStorage reg = loc.reg; local
848 MarkTemp(RegStorage reg) argument
855 UnmarkTemp(RegStorage reg) argument
864 MarkWide(RegStorage reg) argument
886 MarkNarrow(RegStorage reg) argument
922 MarkInUse(RegStorage reg) argument
997 RegStorage reg = AllocLiveReg(loc.s_reg_low, loc.ref ? kRefReg : kAnyReg, false); local
1022 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true); local
1408 RegStorage reg = RegStorage::InvalidReg(); local
1438 RegStorage reg = AllocPreservedCoreReg(low_sreg); local
1452 RegStorage reg = RegStorage::InvalidReg(); local
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/art/test/404-optimizing-allocator/src/
H A DMain.java17 // Note that $opt$reg$ is a marker for the optimizing compiler to ensure
23 expectEquals(4, $opt$reg$TestLostCopy());
24 expectEquals(-10, $opt$reg$TestTwoLive());
25 expectEquals(-20, $opt$reg$TestThreeLive());
26 expectEquals(5, $opt$reg$TestFourLive());
27 expectEquals(10, $opt$reg$TestMultipleLive());
28 expectEquals(1, $opt$reg$TestWithBreakAndContinue());
29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7));
30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7));
31 expectEquals(-77, $opt$reg
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/art/compiler/
H A Delf_writer_debug.cc46 for (int reg = 0; reg < 13; reg++) {
47 if (reg < 4 || reg == 12) {
48 opcodes.Undefined(Reg::ArmCore(reg));
50 opcodes.SameValue(Reg::ArmCore(reg));
54 for (int reg = 0; reg < 32; reg
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/art/compiler/dex/quick/x86/
H A Dfp_x86.cc65 RegStorage r_dest = rl_result.reg;
66 RegStorage r_src1 = rl_src1.reg;
67 RegStorage r_src2 = rl_src2.reg;
118 if (rl_result.reg == rl_src2.reg) {
119 rl_src2.reg = AllocTempDouble();
120 OpRegCopy(rl_src2.reg, rl_result.reg);
122 OpRegCopy(rl_result.reg, rl_src1.reg);
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H A Dint_x86.cc44 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
45 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0
47 NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg());
48 NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg());
108 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, argument
111 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
112 NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg
1105 IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) argument
1374 OpPcRelLoad(RegStorage reg, LIR* target) argument
1477 GenDivZeroCheckWide(RegStorage reg) argument
1593 OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) argument
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/art/compiler/dex/quick/arm/
H A Dint_arm.cc140 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh());
143 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow());
157 rl_temp.reg.SetReg(t_reg.GetReg());
175 RegStorage low_reg = rl_src1.reg.GetLow();
176 RegStorage high_reg = rl_src1.reg.GetHigh();
264 OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val);
267 LoadConstant(rl_result.reg, false_va
380 OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) argument
1089 OpPcRelLoad(RegStorage reg, LIR* target) argument
1157 GenDivZeroCheckWide(RegStorage reg) argument
1182 OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) argument
[all...]
H A Dfp_arm.cc68 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
115 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
126 NewLIR3(kThumb2Vmuls, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), r_tmp.GetReg());
141 NewLIR3(kThumb2Vmuld, rl_result.reg.GetReg(), rl_src1.reg
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/art/compiler/utils/mips64/
H A Dmanaged_register_mips64.h104 Mips64ManagedRegister reg(reg_id);
105 CHECK(reg.IsValidManagedRegister());
106 return reg;
110 std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg);
115 mips64::Mips64ManagedRegister reg(id_);
116 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
117 return reg;
/art/compiler/dex/quick/mips/
H A Dint_mips.cc59 NewLIR3(kMipsSlt, temp.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
60 NewLIR3(kMipsSlt, rl_result.reg.GetReg(), rl_src2.reg.GetReg(), rl_src1.reg.GetReg());
61 NewLIR3(kMipsSubu, rl_result.reg.GetReg(), rl_result.reg.GetReg(), temp.GetReg());
68 NewLIR3(kMipsSlt, t0.GetReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg());
69 NewLIR3(kMipsSlt, t1.GetReg(), rl_src2.reg
149 OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) argument
411 OpPcRelLoad(RegStorage reg, LIR* target) argument
441 GenDivZeroCheckWide(RegStorage reg) argument
460 OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) argument
[all...]
/art/compiler/dwarf/
H A Ddebug_frame_opcode_writer.h71 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { argument
72 Offset(reg, offset - current_cfa_offset_);
115 void ALWAYS_INLINE Offset(Reg reg, int offset) { argument
120 if (0 <= reg.num() && reg.num() <= 0x3F) {
121 this->PushUint8(DW_CFA_offset | reg.num());
125 this->PushUleb128(reg.num());
131 this->PushUleb128(reg.num());
137 void ALWAYS_INLINE Restore(Reg reg) { argument
140 if (0 <= reg
149 Undefined(Reg reg) argument
157 SameValue(Reg reg) argument
166 Register(Reg reg, Reg new_reg) argument
189 DefCFA(Reg reg, int offset) argument
206 DefCFARegister(Reg reg) argument
232 ValOffset(Reg reg, int offset) argument
259 Expression(Reg reg, void * expr, int expr_size) argument
270 ValExpression(Reg reg, void * expr, int expr_size) argument
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/art/compiler/dex/quick/arm64/
H A Dfp_arm64.cc64 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
117 NewLIR3(WIDE(op), rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
128 NewLIR3(kA64Fmul3fff, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), r_tmp.GetReg());
143 NewLIR3(WIDE(kA64Fmul3fff), rl_result.reg.GetReg(), rl_src1.reg
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