| /art/runtime/arch/arm/ |
| H A D | memcmp16_arm.S | 60 subs r0, r0, ip
62 subs r2, r2, #1
80 subs r0, r0, ip
102 subs r2, r2, #(16 + 2)
133 subs r2, r2, #16
145 subs r2, r2, #2
162 subs r0, r0, ip
176 subs r0, r0, ip
178 subs r2, r2, #1
220 subs r
[all...] |
| H A D | quick_entrypoints_arm.S | 1146 subs ip, r2, #32 @ ip<- r2 - 32
1168 subs ip, r2, #32 @ ip<- r2 - 32
1190 subs ip, r2, #32 @ ip<- r2 - 32
1241 subs r2, #4
1257 subs r2, #4
1268 subs r2, #1
1341 subs r11, r7, r10
1349 subs r2, #2 @ offset to contents[-1]
1350 subs r1, #2 @ offset to contents[-1]
1362 subs r1
[all...] |
| /art/runtime/arch/arm64/ |
| H A D | memcmp16_arm64.S | 65 subs limit_wd, limit_wd, #1
136 subs limit, limit, #2
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| H A D | quick_entrypoints_arm64.S | 1766 subs w2, w2, #4
1782 subs w2, w2, #4
1793 subs w2, w2, #1
1851 subs x0, x4, x3
1872 subs w3, w3, #2
1881 subs w4, w4, w5
1884 subs w6, w6, w7
1897 subs w4, w4, w5
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| /art/compiler/utils/arm/ |
| H A D | assembler_thumb2_test.cc | 231 __ subs(arm::R1, arm::R0, arm::ShifterOperand(42));
235 "subs r1, r0, #42\n"
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| H A D | assembler_arm32.cc | 99 void Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so, function in class:art::arm::Arm32Assembler
1397 subs(rd, rn, shifter_op, cond);
1405 subs(rd, rn, ShifterOperand(IP), cond);
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| H A D | assembler_arm32.h | 47 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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| H A D | assembler_arm32_test.cc | 639 T4Helper(&arm::Arm32Assembler::subs, false, "sub{cond}s {reg1}, {reg2}, {shift}", "subs");
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| H A D | assembler_thumb2.h | 69 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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| H A D | assembler_arm.h | 356 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
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| H A D | assembler_thumb2.cc | 96 void Thumb2Assembler::subs(Register rd, Register rn, const ShifterOperand& so, function in class:art::arm::Thumb2Assembler
2502 subs(rd, rn, shifter_op, cond);
2510 subs(rd, rn, ShifterOperand(IP), cond);
|
| /art/compiler/optimizing/ |
| H A D | code_generator_arm.cc | 2067 __ subs(out.AsRegisterPairLow<Register>(),
2537 __ subs(temp, o_l, ShifterOperand(kArmBitsPerWord));
2551 __ subs(temp, o_h, ShifterOperand(kArmBitsPerWord));
2563 __ subs(temp, o_h, ShifterOperand(kArmBitsPerWord));
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| H A D | intrinsics_arm.cc | 746 __ subs(tmp_lo, tmp_lo, ShifterOperand(expected_lo));
|